CN107731671A - The technique for improving the injection boron element diffusion of growing epitaxial silicon intermediate ion - Google Patents
The technique for improving the injection boron element diffusion of growing epitaxial silicon intermediate ion Download PDFInfo
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- CN107731671A CN107731671A CN201710733222.8A CN201710733222A CN107731671A CN 107731671 A CN107731671 A CN 107731671A CN 201710733222 A CN201710733222 A CN 201710733222A CN 107731671 A CN107731671 A CN 107731671A
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- silicon
- growing epitaxial
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- boron element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Abstract
The invention provides the technique for improving the injection boron element diffusion of growing epitaxial silicon intermediate ion in a kind of 3D NAND flash memory structures, corona treatment is carried out to the silicon groove interface of growing epitaxial silicon by using the gas containing F and/or Cl, effectively the monocrystalline silicon at growing epitaxial silicon interface can be destroyed and then be converted into non-crystalline silicon, and the growing epitaxial silicon speed at non-crystalline silicon interface is slower than the growing epitaxial silicon speed of monocrystalline silicon interface, so as to advantageously form the room between silicon epitaxy layer and substrate (Void)；The room (Void) of formation becomes the barrier (Barrier) of boron element interface diffusion, the boron element for effectively blocking ion implantation doping diffuses to silicon substrate from silicon epitaxy layer, so as to improve the threshold voltage of silicon epitaxy layer (Vt) characteristic, and then finally improve the overall performance of 3D nand flash memories.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of 3D NAND flash memory structures and preparation method thereof, especially
It is a kind of technique that can improve the injection boron element diffusion of silicon epitaxy intermediate ion.
Background technology
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges：Physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty and most ask being produced into for lower unit storage unit that planar flash memory runs into
This, a variety of three-dimensional (3D) flash memories structures are arisen at the historic moment, such as 3D NOR (3D or non-) flash memories and 3D NAND
(3D with non-) flash memory.
Wherein, in the 3D flash memories of NOR-type structure, memory cell is arranged in parallel between bit line and ground wire, and in NAND
In the 3D flash memories of type structure, memory cell tandem between bit line and ground wire arranges.NAND-type flash memory tool with cascaded structure
There is relatively low reading speed, but there is higher writing speed, so as to which NAND-type flash memory is suitable for data storage, its is excellent
Point is that small volume, capacity are big.Flush memory device can be divided into stacked grid type and separate gate type according to the structure of memory cell, and
And floating gate device and silicon-oxide-nitride-oxide (SONO) device are divided into according to the shape of charge storage layer.Its
In, SONO types flush memory device has the reliability more excellent than floating grid polar form flush memory device, and can be performed with relatively low voltage
Programming and erasing operation, and ONOS types flush memory device has very thin unit, and be easy to manufacture.
In the preparation of 3D NAND (3D with non-) flash memory, it usually needs one layer of degree of purity of extension is higher on a silicon substrate
Silicon epitaxial layer, or silicon substrate growing epitaxial layers are mixed up to prevent the breech lock of device (Latch Up) effect etc. from asking in height
Topic, specific growing epitaxial silicon technique generally include following steps：
S1：Channel etching, referring to Fig. 1 a, specifically, providing substrate 1, the substrate surface is formed with multi-layer intercrossed stacking
Interlayer dielectric layer 2 and sacrificial dielectric layer 3, the sacrificial dielectric layer 3 be formed between adjacent interlayer dielectric layer 2；The layer
Between dielectric layer 2 be oxide skin(coating), the sacrificial dielectric layer 3 is nitride layer, so as to form NO stacked structures (NO Stacks)；
After NO stacked structures surface deposited hard mask oxide skin(coating) (Hard Mask Oxide), the interlayer dielectric layer 2 and sacrificial is etched
To form raceway groove 4, the raceway groove 4 passes to the substrate 1 and forms the silicon groove 5 of certain depth domestic animal dielectric layer 3.
S2：Etching post processing (Post Etch Treatment) (not shown), specifically, using nitrogen (N2), nitrogen
(N2) and carbon monoxide (CO) or nitrogen (N2) and hydrogen (H2) the silicon groove region being etched is purged, locate after this etching
The method of reason, there is more preferable polymer removal effect than common cleaning.
S3：Growing epitaxial silicon, referring to Fig. 1 b, specifically, first, using wet-cleaning and/or plasma clean to silicon
Groove region carries out prerinse processing；Silicon is then carried out at silicon groove 5 is epitaxially-formed silicon epitaxy layer 6 (SEG).
S4：Ion implantation doping boron element, referring to Fig. 1 c, ion implanting processing specially is carried out to the silicon epitaxy layer 6
To adulterate boron element.
After above-mentioned operation, it may also need to carry out the deposition such as ONOP (oxide/nitride/oxide/polysilicon), etching
Process, these subsequent process steps can produce substantial amounts of heat and form pyroprocess, and the atomic number of the boron element due to doping
Number the, molecular weight are small, are easy to produce diffusion in these follow-up pyroprocesses, so as to cross between silicon epitaxy layer and substrate
Interface, go in the middle of silicon substrate that (referring to Fig. 2 a-b, lower section white arrow is boron element diffusion in Fig. 2 a by silicon epitaxy layer
Direction), so as to influence threshold voltage (Vt) control, and then the final performance for influenceing 3D nand flash memories.
Therefore, the interface diffusion of ion implantation doping boron element how is effectively reduced, to improve silicon epitaxial layer
Threshold voltage characteristic, the direction of research is endeavoured by those skilled in the art always.
The content of the invention
It is an object of the invention to provide a kind of preparation method of 3D nand flash memories, can realize and reduce in silicon epitaxy layer
Boron ion implantation elements diffusion, so as to improve the performance of 3D nand flash memories.
To achieve these goals, the present invention proposes a kind of improvement growing epitaxial silicon intermediate ion injection boron element diffusion
Technique, it is characterised in that comprise the following steps：
Channel etching, specifically, first, there is provided substrate, and form NO stacked structures (NO Stacks) in substrate surface；
Then, perform etching to form raceway groove, the raceway groove passes to the substrate and forms the silicon groove of certain depth；
Etching post processing (Post Etch Treatment), to destroy silicon rooved face, amorphous is converted into by it by monocrystalline silicon
Silicon；
Growing epitaxial silicon, specifically, silicon is carried out at silicon groove is epitaxially-formed silicon epitaxy layer (SEG)；
Boron element is adulterated, ion implanting processing is specially carried out to the silicon epitaxy layer to adulterate boron element.
Further, the formation NO stacked structures (NO Stacks), specifically, forming multilayer in the substrate surface
The interlayer dielectric layer and sacrificial dielectric layer being staggeredly stacked, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；Institute
It is oxide skin(coating) to state interlayer dielectric layer, and the sacrificial dielectric layer is nitride layer, so as to form NO stacked structures (NO
Stacks)。
Further, in the channel etching step, in addition to before etching, formed on the NO stacked structures surface and covered firmly
Mould oxide skin(coating) (Hard Mask Oxide).
Further, the etching, specifically, etching the NO vertically downward using anisotropic dry etch process
Stacked structure is to form the raceway groove.
Further, the etching post processing, is to carry out corona treatment using the gas containing F and/or Cl, to have
The monocrystalline silicon at growing epitaxial silicon interface is destroyed and is converted into non-crystalline silicon by effect.
Further, in the growing epitaxial silicon step, there is room between obtained silicon epitaxy layer and substrate
(Void)。
Further, the height of the room (Void) can ensure so that polysilicon passage and institute in subsequent technique
State and current path is formed between silicon epitaxy layer and substrate.
Further, the height of the room (Void) is less than the depth of the silicon groove.
Present invention also offers a kind of 3D NAND flash memory structures, the silicon epitaxy layer in described flash memory structure is by above-mentioned
Process is prepared.
Compared with prior art, the beneficial effects are mainly as follows：
First, after channel etching, the silicon groove interface of growing epitaxial silicon is carried out by using the gas containing F and/or Cl
Corona treatment, effectively the monocrystalline silicon at growing epitaxial silicon interface can be destroyed and then be converted into non-crystalline silicon, and non-crystalline silicon circle
The growing epitaxial silicon speed in face is slower than the growing epitaxial silicon speed of monocrystalline silicon interface, so as to advantageously form silicon epitaxy layer and lining
Room (Void) between bottom；
Second, the room (Void) of formation becomes the barrier (Barrier) of boron element interface diffusion, effectively block from
The boron element of son injection doping diffuses to silicon substrate from silicon epitaxy layer, so as to improve the threshold voltage of silicon epitaxy layer (Vt) spy
Property；
3rd, technique of the invention can effectively control room (Void) height, so as to ensure effectively to stop that boron element spreads
While, it also can guarantee that and form circuit pathways between the polysilicon passage in subsequent technique, silicon epitaxy layer, substrate.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 a-c are the process chart of the growing epitaxial silicon of 3D NAND flash memory structures in the prior art；
The principle schematic and ESEM that Fig. 2 a-b spread for boron element interface in growing epitaxial silicon in the prior art are shone
Piece；
Fig. 3 a-d are the process chart of the growing epitaxial silicon of 3D NAND flash memory structures in the present invention；
Fig. 4 is that the electric current in the present invention between the polysilicon passage of 3D NAND flash memory structures, silicon epitaxy layer, silicon substrate leads to
Road schematic diagram.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in accompanying drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs
The scope opened completely is communicated to those skilled in the art.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expended
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Fig. 3 is refer to, in the present embodiment, it is proposed that a kind of to improve what growing epitaxial silicon intermediate ion injection boron element spread
Technique, specifically include following steps：
S100：Channel etching, specifically, first, there is provided substrate, and form NO stacked structures (NO in substrate surface
Stacks)；Then, perform etching to form raceway groove, the raceway groove passes to the substrate and forms the silicon groove of certain depth；
S200：Etching post processing (Post Etch Treatment), to destroy silicon rooved face, it is converted by monocrystalline silicon
For non-crystalline silicon；
S300：Growing epitaxial silicon, specifically, silicon is carried out at silicon groove is epitaxially-formed silicon epitaxy layer (SEG)；
S400：Boron element is adulterated, ion implanting processing is specially carried out to the silicon epitaxy layer to adulterate boron element.
Specifically, refer to Fig. 3 a, in the step s 100, step S110 is carried out first, there is provided substrate 100, and in substrate
100 surfaces form the interlayer dielectric layer 110 and sacrificial dielectric layer 120 of multi-layer intercrossed stacking, and the sacrificial dielectric layer 120 is formed at
Between adjacent interlayer dielectric layer 110；The interlayer dielectric layer 110 is oxide skin(coating), such as silicon oxide layer, the sacrificial dielectric
Layer 120 is nitride layer, such as silicon nitride layer, so as to form NO stacked structures (NO Stacks)；Step S120 is then carried out,
Hard mask oxide skin(coating) (Hard Mask Oxide) is formed on the NO stacked structures surface；Followed by step S130, adopt
The NO stacked structures are etched vertically downward with anisotropic dry etch process to form raceway groove 130, and the raceway groove 130 leads to
To the substrate 100 and form the silicon groove 140 of certain depth.
Fig. 3 b are refer to, in step s 200, the etching of corona treatment are carried out using the gas containing F and/or Cl
(Post Etch Treatment) technique is post-processed, to destroy silicon rooved face, by the growing epitaxial silicon interface of silicon rooved face by list
Crystal silicon is converted into non-crystalline silicon.
Fig. 3 c are refer to, in step S300, silicon is carried out at silicon groove 140 is epitaxially-formed silicon epitaxy layer 150
(SEG).Because the etching for carrying out S200 post-processes (Post Etch Treatment) so that growing epitaxial silicon interface is by list
Crystal silicon is converted into non-crystalline silicon, and the growing epitaxial silicon speed at non-crystalline silicon interface is than the growing epitaxial silicon speed of monocrystalline silicon interface
Slowly, so as to form the room (Void) 160 between silicon epitaxy layer 150 and substrate 100 during growing epitaxial silicon.
Fig. 3 d are refer to, in step S400, ion implanting processing is carried out to the silicon epitaxy layer 150 to adulterate boron member
Element.
Silicon epitaxy layer that present invention process is prepared, it is necessary to room (Void) 160 height is carried out effectively regulation and
Control, so as to ensure to form effective electric current between the polysilicon passage 170, silicon epitaxy layer 150 and silicon substrate 100 subsequently prepared
Path, therefore room (Void) 160 height (should refer to Fig. 4, graphical dots dash-dot curve is electricity less than the depth H of silicon groove
Logical circulation road is illustrated).
To sum up, after channel etching, the silicon groove interface of growing epitaxial silicon is carried out by using the gas containing F and/or Cl
Corona treatment, effectively the monocrystalline silicon at growing epitaxial silicon interface can be destroyed and then be converted into non-crystalline silicon, and non-crystalline silicon circle
The growing epitaxial silicon speed in face is slower than the growing epitaxial silicon speed of monocrystalline silicon interface, so as to advantageously form silicon epitaxy layer and lining
Room (Void) between bottom；The room (Void) of formation becomes the barrier (Barrier) of boron element interface diffusion, effectively resistance
The boron element for having kept off ion implantation doping diffuses to silicon substrate from silicon epitaxy layer, so as to improve the threshold voltage of silicon epitaxy layer
(Vt) characteristic；Meanwhile technique of the invention can effectively control room (Void) height, so as to ensure effectively to stop that boron element spreads
While, it also can guarantee that and form circuit pathways between the polysilicon passage in subsequent technique, silicon epitaxy layer, substrate.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Enclose and be defined.
Claims (9)
1. a kind of technique for improving the injection boron element diffusion of growing epitaxial silicon intermediate ion, it is characterised in that comprise the following steps：
Channel etching, specifically, first, there is provided substrate, and form NO stacked structures (NO Stacks) in substrate surface；Then,
Perform etching to form raceway groove, the raceway groove passes to the substrate and forms the silicon groove of certain depth；
Etching post processing (Post Etch Treatment), to destroy silicon rooved face, non-crystalline silicon is converted into by it by monocrystalline silicon；
Growing epitaxial silicon, specifically, silicon is carried out at silicon groove is epitaxially-formed silicon epitaxy layer (SEG)；
Boron element is adulterated, ion implanting processing is specially carried out to the silicon epitaxy layer to adulterate boron element.
2. technique according to claim 1, it is characterised in that：
The formation NO stacked structures (NO Stacks), specifically, forming the interlayer of multi-layer intercrossed stacking in the substrate surface
Dielectric layer and sacrificial dielectric layer, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；The interlayer dielectric layer is
Oxide skin(coating), the sacrificial dielectric layer are nitride layer, so as to form NO stacked structures (NO Stacks).
3. technique according to claim 1, it is characterised in that：
In the channel etching step, in addition to before etching, hard mask oxide skin(coating) is formed on the NO stacked structures surface
(Hard Mask Oxide)。
4. technique according to claim 1, it is characterised in that：
The etching, specifically, using anisotropic dry etch process to etch the NO stacked structures vertically downward with shape
Into the raceway groove.
5. technique according to claim 1, it is characterised in that：
The etching post processing, is to carry out corona treatment using the gas containing F and/or Cl, effectively to give birth to silicon epitaxy
The monocrystalline silicon at long interface destroys and is converted into non-crystalline silicon.
6. technique according to claim 5, it is characterised in that：
In the growing epitaxial silicon step, there is room (Void) between obtained silicon epitaxy layer and substrate.
7. technique according to claim 6, it is characterised in that：
The height of the room (Void) can ensure so that polysilicon passage and the silicon epitaxy layer and lining in subsequent technique
Current path is formed between bottom.
8. the technique according to claim 6 or 7, it is characterised in that：
The height of the room (Void) is less than the depth of the silicon groove.
A kind of 9. 3D NAND flash memory structures, it is characterised in that：The silicon epitaxy layer of the flash memory structure is any by claim 1-8
Technique described in one is prepared.
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| CN107731671B (en) | 2019-11-12 |
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