CN108666318B - Form the method and three-dimensional storage of the underlying semiconductor pattern of three-dimensional storage - Google Patents
Form the method and three-dimensional storage of the underlying semiconductor pattern of three-dimensional storage Download PDFInfo
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- CN108666318B CN108666318B CN201810489031.6A CN201810489031A CN108666318B CN 108666318 B CN108666318 B CN 108666318B CN 201810489031 A CN201810489031 A CN 201810489031A CN 108666318 B CN108666318 B CN 108666318B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The present invention relates to the methods and three-dimensional storage of a kind of underlying semiconductor pattern for forming three-dimensional storage.Method includes the following steps: providing semiconductor structure, the semiconductor structure has substrate and the stack layer on the substrate, and the stack layer includes the multiple first material layers and multiple second material layers being alternately stacked；Form the multiple channel holes for extending vertically through the stack layer and reaching the substrate；The impurity in the substrate is removed by the multiple channel hole, the removal step forms the notch protruded out from the multiple channel hole side wall to the substrate side；And the semiconductor material with dopant is formed as underlying semiconductor pattern in the multiple channel hole bottom, the semiconductor material fills the notch.The homogeneity of the threshold voltage of the bottom selection grid of three-dimensional storage can be improved in the present invention.
Description
Technical field
The invention mainly relates to semiconductor making methods, are particularly to the formation of the underlying semiconductor pattern of three-dimensional storage
Method and three-dimensional storage.
Background technique
In order to overcome the limitation of two-dimensional storage device, industry has been developed that the memory device with three-dimensional (3D) structure,
Integration density is improved by the way that memory cell is three-dimensionally disposed in substrate.
In the three-dimensional storage part of such as 3D nand flash memory, storage array may include the area core (core).Core
(core) area has substrate and stacked structure, is formed in stacked structure many for storing the transistor of charge.It is dodged in 3D NAND
It deposits in processing procedure, needs the threshold voltage vt of each layer transistor of strict control.Here, bottom selection grid (Bottom Select
Gate, BSG) threshold voltage vt by pass through stack layer lower part and be connected to substrate underlying semiconductor pattern manufacture craft
It influences, homogeneity is difficult to control.
Summary of the invention
The present invention provides the method and three-dimensional storage of a kind of underlying semiconductor pattern for forming three-dimensional storage, can be with
Improve the homogeneity of the threshold voltage of the bottom selection grid of three-dimensional storage.
A kind of method that one aspect of the present invention proposes underlying semiconductor pattern for forming three-dimensional storage, including it is following
Step: providing semiconductor structure, and the semiconductor structure has substrate and the stack layer on the substrate, the stack layer
Including the multiple first material layers and multiple second material layers being alternately stacked；Formation extends vertically through described in the stack layer and arrival
Multiple channel holes of substrate；The impurity in the substrate is removed by the multiple channel hole, the removal step is formed from institute
State the notch that multiple channel holes side wall is protruded out to the substrate side；And it is formed in the multiple channel hole bottom with doping
The semiconductor material of agent fills the notch as underlying semiconductor pattern, the semiconductor material.
In one embodiment of this invention, the above method further includes forming bottom selection grid in the substrate.
In one embodiment of this invention, the method for removing the impurity in the substrate includes being carried out clearly using hydrogen chloride
It removes.
In one embodiment of this invention, the method for forming the semiconductor material with dopant is included in form described half
The impurity gas for having the dopant is added during conductor material.
In one embodiment of this invention, the method for forming the semiconductor material includes selective epitaxial growth.
In one embodiment of this invention, the dopant dose of the dopant is 7*1013To 1*1014atom/cm2。
In one embodiment of this invention, the profile of notch is not between at least partly channel hole in the multiple channel hole
Together.
In one embodiment of this invention, the semiconductor structure is wafer.
In one embodiment of this invention, middle section and marginal zone of the multiple channel pore size distribution in the wafer
Domain.
In one embodiment of this invention, the first material layer is dummy gate layer, and the second material layer is dielectric layer.
In one embodiment of this invention, the dopant contains boron.
Another aspect of the present invention also proposes a kind of three-dimensional storage, including substrate, stack layer, multiple channel holes and under
Portion's semiconductor pattern.Stack layer is located on the substrate, and the stack layer includes the grid layer at interval.Multiple channel holes are vertically passed through
Wear the stack layer and reach the substrate, wherein the multiple channel hole bottom have from the multiple channel hole side wall to
The notch that the substrate side protrudes out.The underlying semiconductor pattern fills the notch, wherein the underlying semiconductor pattern
It is through overdoping.
In one embodiment of this invention, three-dimensional storage further includes the bottom selection grid in the substrate.
In one embodiment of this invention, the profile of notch is not at least partly between channel hole in the multiple channel hole
Together.
In one embodiment of this invention, the doping type of the underlying semiconductor pattern is that p-type is adulterated or N-type is mixed
It is miscellaneous.
In one embodiment of this invention, the impurity of the underlying semiconductor pattern is boron.
In the method for the underlying semiconductor pattern of formation three-dimensional storage of the invention and three-dimensional storage, by
The doping of agent is doped when forming underlying semiconductor pattern, come make up to form underlying semiconductor pattern before remove impurity the step of
Caused substrate defects, to be effectively improved the problem of the threshold voltage vt homogeneity difference of bottom selection grid.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Fig. 1 is the method flow diagram of the underlying semiconductor pattern of the formation three-dimensional storage of one embodiment of the invention.
Fig. 2A -2D is the exemplary of the method for the underlying semiconductor pattern of the formation three-dimensional storage of one embodiment of the invention
Diagrammatic cross-section in the process.
Fig. 3 is the horizontal profile schematic diagram for illustrating substrate damage.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
The embodiment of the present invention describes to form the method and three-dimensional storage of the underlying semiconductor pattern of three-dimensional storage,
The homogeneity of the threshold voltage of the bottom selection grid of three-dimensional storage can be improved.
Fig. 1 is the flow chart of the underlying semiconductor pattern of the formation three-dimensional storage part of one embodiment of the invention.Fig. 2A -2D
It is the example process schematic diagram of the method for the underlying semiconductor pattern of the formation three-dimensional storage part of one embodiment of the invention.Under
The method of the formation underlying semiconductor pattern of face description the present embodiment with reference to shown in Fig. 1-2 D.
In step 102, semiconductor structure is provided.
This semiconductor structure is at least one for being used for structure of the follow-up process to ultimately form three-dimensional storage part
Point.Semiconductor structure may include array area, and array area may include core space.In terms of vertical direction, core space can have substrate and
Stack layer on substrate.Stack layer includes the multiple first material layers and multiple second material layers being alternately stacked.
In one embodiment of this invention, first material layer can be dummy gate layer, will be gone in subsequent technique
It removes and replaces with grid layer.In another embodiment of the invention, first material layer can be grid layer, will remain into always
Grid layer is used as in final three-dimensional storage product.In an embodiment of the present invention, second material layer is dielectric layer, for every
Open first material layer.
In this semiconductor structure, bottom selection grid is formd in the substrate.The method for forming bottom selection grid can
To be known various methods, such as ion implanting.
In the sectional view of semiconductor structure exemplified by Fig. 2A, semiconductor structure 200a may include substrate 201 and be located at
Stack layer (stack) 210 on substrate 401.Stack layer 210 is that first material layer 211 and second material layer 212 are alternately stacked
Lamination.
In an embodiment of the present invention, the material of substrate 201 is, for example, silicon.First material layer 211 and second material layer 212
The e.g. combination of silicon nitride and silica.By taking the combination of silicon nitride and silica as an example, chemical vapor deposition can be used
(CVD), atomic layer deposition (ALD) or other suitable deposition methods successively replace deposited silicon nitride and oxidation on substrate 201
Silicon forms stack layer 210.In another embodiment, first material layer 211 and second material layer 212 are, for example, polysilicon and oxygen
The combination of SiClx.
Although there is described herein the exemplary composition of initial semiconductor structure, it is to be understood that, one or more features
It can be omitted, substitute or increase to from this semiconductor structure in this semiconductor structure.Such as semiconductor interface can wrap
Include the structure of wordline bonding pad.For example, various well regions can be formed in substrate as needed.In addition, the material for each layer illustrated
It is only exemplary, such as substrate 401 can also be other siliceous substrates, such as SOI (silicon-on-insulator), SiGe, Si:
C etc..
In step 104, the multiple channel holes for extending vertically through stack layer and reaching substrate are formed.
In this step, multiple channel holes perpendicular to substrate surface are formed in stack layer.Channel bore portion is through lining
Bottom.Channel hole is used to accommodate the memory element being subsequently formed.
One of lithographic process can be used to form channel hole in the stack layer of core space.For example, a photomask pair can be used
Core space is exposed, and is cooperated corresponding etching, is formed channel hole.
In the sectional view of the semiconductor structure exemplified by Fig. 2 B, channel hole 213 is formd in semiconductor structure 200b.
Very strong plasma is had when etching channel hole 213, to introduce silicon source (Si Source).In this way, 213, channel hole
Surface in substrate 201 has impurity 214, such as silicon source and amorphous silicon.
In step 106, the impurity in substrate is removed by multiple channel holes.
In this step, it in the case where taking into account characteristic size (CD), defect and quality, can carry out forming lower semiconductor
Pre-processing (Pre bake) before pattern.Pre-processing includes removal impurity.
For example, pre-processing is carried out by hydrogen chloride (HCl), wherein HCl is very high to the selectivity of silicon, can remove
Silicon source and amorphous silicon.Here, preferably the silicon source of clean channel hole interface is removed in the flow of strict control HCl, guarantee.However
HCl amount is still difficult to control, and if HCl amount is very little, silicon source is not cleaned up, and the defect of underlying semiconductor pattern is obvious,
It is second-rate.If HCl amount is too many, substrate is damaged, will form and protruded out from multiple channel holes side wall to substrate side
Notch.
In the sectional view of semiconductor structure 200c exemplified by Fig. 2 C, the impurity in channel hole 213 is had been removed.So
And the undesirable side wall from multiple channel holes 213 is formed to 201 side of substrate to the notch 215 protruded out.
Fig. 3 is the horizontal profile schematic diagram for illustrating substrate damage, and notch is on greater area of substrate as seen from Figure 3
Distribution.In Fig. 3, section many channel holes 213 roughly circular, from side wall to 201 side of substrate to protruded out permitted
More notches 215.It can be seen that the profile of notch 215 is different between at least partly channel hole 213 in multiple channel holes 213.Thing
In reality, the profile of notch 215 is difficult to control, and shape is also very random.
In step 108, the semiconductor material that contains impurity is formed as underlying semiconductor pattern in multiple channel holes bottom,
Semiconductor material fills notch.
In this step, the doping gas with dopant can be added during the underlying semiconductor pattern of formation
Body, so that being formed by underlying semiconductor pattern is through overdoping.Here, doping can be p-type (first kind) and mix
It is miscellaneous, it is also possible to N-type (Second Type) doping.For being adulterated with p-type, dopant may include group-III element, with n-type doping
For, dopant may include V group element.It is to be appreciated here that underlying semiconductor pattern can be doped to so that impurity reaches
Predetermined concentration is horizontal.Such as be removed the comparable concentration level of substrate material that side is drawn.
In the process of the underlying semiconductor pattern of formation, the semiconductor material containing impurity can also enter channel hole side
In notch, so that also containing impurity in the semiconductor material of notch.
It in this step, can be by accurately controlling the doping of dopant, to guarantee the threshold voltage of bottom selection grid
(Vt) it suits the requirements.
In the sectional view of semiconductor structure 200d exemplified by Fig. 2 D, formed in the bottom in each channel hole 213 containing miscellaneous
The semiconductor material 216 of matter is used as underlying semiconductor pattern.Semiconductor material 216 fills notch simultaneously.Form semiconductor material
216 mode is, for example, selective epitaxial growth (Selective Epitaxial Growth, SEG).Semiconductor material 216
Material is, for example, silicon.For being adulterated with p-type, the dopant of addition can be boron (B).Impurity gas with dopant can be
Borine.The dopant dose of dopant can be 7*1013To 1*1014atom/cm2。
Flow chart has been used to be used to illustrate operation performed by method according to an embodiment of the present application herein.It should be understood that
, the operation of front not necessarily accurately carries out in sequence.On the contrary, various steps can be handled according to inverted order or simultaneously
Suddenly.Meanwhile or during other operations are added to these, or from these processes remove a certain step or number step operation.
By above-mentioned processing, the homogeneity of the concentration of impurity everywhere can be obviously improved in substrate, to significantly improve bottom
The homogeneity of the threshold voltage of portion's selection grid.In this way, the yield of three-dimensional storage can be promoted.
Another advantage of the present embodiment is that the threshold value of bottom selection grid is solved in the step of forming underlying semiconductor pattern
The homogeneity problem of voltage, so as to simplify technique.In contrast, it is a kind of formed underlying semiconductor pattern method be first by
Conventional method forms underlying semiconductor pattern, then carries out ion implanting to underlying semiconductor pattern and forms doping.This side
Method not only needs additional step, but also since ion implanting is vertical injection, the notch that cannot be injected into except channel hole
Region, and cause Impurity Distribution uneven.
Further, in the wafer comprising multiple memory naked cores (die), the method for the present embodiment can improve middle section
In fringe region, the homogeneity problem of the threshold voltage of bottom selection grid.Specifically, refering to what is shown in Fig. 3, if what it showed
For whole wafer, then channel hole 213 is distributed in the middle section and fringe region of wafer.Substrate of the notch 215 in whole wafer
On profile differences it is significant, such as in the middle section of wafer, 215 lateral dimensions of notch is big, and lacks in the fringe region of wafer
The lateral dimensions of mouth 215 is small.The semiconductor material with impurity is consistently filled into each region in through this embodiment
In notch 215, being evenly distributed for impurity can be made, so as to improve whole wafer upper bottom portion selection grid threshold voltage it is uniform
Property.
After the completion of above-mentioned steps 102-108 technique, along with conventional technique, such as formed memory layer, channel layer,
Channel hole technique can be completed in filled layer and top electrodes, and along with the technique in other regions, implementation of the present invention can be obtained
The three-dimensional storage of example.Three-dimensional storage may include array area (array), and array area may include that core space (core) and wordline connect
Meet area.Core space is the region for including storage unit, and wordline bonding pad is the region for including wordline connection circuit.Wordline bonding pad
It is typically ladder (stair step, SS) structure.It is to be understood that the limitation of this and non-present invention.Completely may be used wordline bonding pad
To use other structures, such as flat structures.In terms of vertical direction, array area can have substrate and stack layer, in core space
Channel hole array is formed on stack layer.Three-dimensional storage according to an embodiment of the invention is described below with reference to Fig. 2 D.To keep away
Exempt to obscure emphasis of the invention, the core space in three-dimensional storage comprising several channel holes is only shown in Fig. 2 D.Such as Fig. 2 D institute
Show, three-dimensional storage may include substrate 201 and stack layer 210.There is selection grid (not shown) in bottom in substrate 201.Stack layer
210 are located on substrate 201, and stack layer 210 includes multiple grid layers 211 at interval.Adjacent grid layer in multiple grid layers 211
It can for example be separated by insulating layer 212 between 211.The number of plies of grid layer 211 and the number of plies of three-dimensional storage are related.
Multiple channel holes 213 extend vertically through stack layer 210 and reach substrate 201, wherein having in multiple channel holes bottom
The notch 215 protruded out from multiple channel holes side wall to substrate side.Underlying semiconductor pattern 216 is formed in the bottom in channel hole 213
Portion, and underlying semiconductor pattern 216 fills notch 215, and underlying semiconductor pattern 216 is through overdoping.
In an embodiment of the present invention, the profile of notch 215 is not at least partly between channel hole in multiple channel holes 213
Together.It may be noted that the profile of notch 215 shown in Fig. 2 D is merely exemplary, the lateral depth and shape of actual profile
Be it is diversified, this can be with reference to shown in Fig. 3.
In an embodiment of the present invention, grid layer 211 is, for example, metal or polysilicon.Insulating layer 212 is, for example, to aoxidize
Silicon.
In an embodiment of the present invention, channel hole 213 can be cylindrical hole, although being not intended as limiting.
In an embodiment of the present invention, 216 doping type of underlying semiconductor pattern can be p-type doping or n-type doping.
Memory layer is for example including barrier layer, electric charge capture layer and tunnel layer.Memory layer, which can be, to be arranged in channel hole
The FGS floating gate structure in first material layer in the lateral trench in channel hole also can be set in inner medium layer.It is appreciated that having
Close the structure and its formation process of memory layer and channel layer and the emphasis of non-present invention, herein not reinflated description.
Three-dimensional storage shown in Fig. 2 D can be charge storage type memory (CTF), and wherein electric charge capture layer is to pass through Jie
Electric layer is realized.It will be understood, however, that the embodiment of the present invention can also be implemented in floating gate type memory, wherein charge-trapping
Layer is realized by floating grid.Electric charge capture layer is for example including polycrystalline silicon material.
Other details of three-dimensional storage part, such as wordline bonding pad, periphery interconnection etc., and the emphasis of non-present invention,
This not reinflated description.
In the context of the present invention, three-dimensional storage part can be 3D flash memory, such as 3D nand flash memory.
The application has used particular words to describe embodiments herein.As " one embodiment ", " embodiment ",
And/or " some embodiments " means a certain feature relevant at least one embodiment of the application, structure or feature.Therefore, it answers
Emphasize and it is noted that " embodiment " or " one embodiment " that is referred to twice or repeatedly in this specification in different location or
" alternate embodiment " is not necessarily meant to refer to the same embodiment.In addition, certain in one or more embodiments of the application
Feature, structure or feature can carry out combination appropriate.
Although the present invention is disclosed as above with preferred embodiment, however, it is not to limit the invention, any this field skill
Art personnel, without departing from the spirit and scope of the present invention, when can make a little modification and perfect therefore of the invention protection model
It encloses to work as and subject to the definition of the claims.
Claims (16)
1. a kind of method for the underlying semiconductor pattern for forming three-dimensional storage, comprising the following steps:
Semiconductor structure is provided, the semiconductor structure has substrate and the stack layer on the substrate, the stack layer
Including the multiple first material layers and multiple second material layers being alternately stacked；
Form the multiple channel holes for extending vertically through the stack layer and reaching the substrate；
The impurity in the substrate is removed by the multiple channel hole, the removal step is formed from the multiple channel hole side
The notch that wall is protruded out to the substrate side；
In the multiple channel hole bottom, semiconductor material of the formation with dopant is described partly to lead as underlying semiconductor pattern
Body material fills the notch, the doping concentration of the dopant be removed and the doping of the substrate material that forms the notch
Concentration is suitable.
2. the method as described in claim 1, which is characterized in that further include forming bottom selection grid in the substrate.
3. the method as described in claim 1, which is characterized in that the method for removing the impurity in the substrate includes using chlorination
Hydrogen is purged.
4. the method as described in claim 1, which is characterized in that the method for forming the semiconductor material with dopant is included in
The impurity gas for having the dopant is added during forming the semiconductor material.
5. method as described in claim 1 or 4, which is characterized in that the method for forming the semiconductor material includes selectivity
Epitaxial growth.
6. method as described in claim 1 or 4, which is characterized in that the dopant dose of the dopant is 7*1013To 1*
1014atom/cm2。
7. the method as described in claim 1, which is characterized in that lacked between at least partly channel hole in the multiple channel hole
The profile of mouth is different.
8. the method as described in claim 1, which is characterized in that the semiconductor structure is wafer.
9. method according to claim 8, which is characterized in that middle section of the multiple channel pore size distribution in the wafer
And fringe region.
10. the method as described in claim 1, which is characterized in that the first material layer is dummy gate layer, second material
Layer is dielectric layer.
11. the method as described in claim 1, which is characterized in that the dopant contains boron.
12. a kind of three-dimensional storage, comprising:
Substrate；
Stack layer is located on the substrate, and the stack layer includes the grid layer at interval；
Multiple channel holes extend vertically through the stack layer and reach the substrate, wherein having in the multiple channel hole bottom
The notch protruded out from the multiple channel hole side wall to the substrate side；
Underlying semiconductor pattern, the underlying semiconductor pattern fill the notch, wherein the underlying semiconductor pattern be through
Overdoping, the concentration of the doping is suitable with the doping concentration of substrate material for being removed and forming the notch.
13. three-dimensional storage as claimed in claim 12, which is characterized in that further include the bottom selection in the substrate
Grid.
14. three-dimensional storage as claimed in claim 12, which is characterized in that in the multiple channel hole at least partly channel hole
Between notch profile it is different.
15. three-dimensional storage as claimed in claim 12, which is characterized in that the doping type of the underlying semiconductor pattern is
P-type doping or n-type doping.
16. three-dimensional storage as claimed in claim 12, which is characterized in that the impurity of the underlying semiconductor pattern is boron.
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