DE102004023405B4 - Dicing ultra-thin wafer in to multiple integrated circuits, by fixing carrier wafer to front of product wafer, forming separating trenches between integrated circuits - Google Patents
Dicing ultra-thin wafer in to multiple integrated circuits, by fixing carrier wafer to front of product wafer, forming separating trenches between integrated circuits Download PDFInfo
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- DE102004023405B4 DE102004023405B4 DE200410023405 DE102004023405A DE102004023405B4 DE 102004023405 B4 DE102004023405 B4 DE 102004023405B4 DE 200410023405 DE200410023405 DE 200410023405 DE 102004023405 A DE102004023405 A DE 102004023405A DE 102004023405 B4 DE102004023405 B4 DE 102004023405B4
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
Die vorliegende Erfindung bezieht sich auf ein Verfahren zum Vereinzeln eines ultradünnen Wafers sowie eine zugehörige Haltevorrichtung und insbesondere auf ein Verfahren zum Vereinzeln eines ultradünnen Wafers in eine Vielzahl von rückseitenprozessierten Einzelbausteinen, wobei mit einem herkömmlichen Wafer-Test-Equipment ein Chiptest durchgeführt werden kann.The The present invention relates to a method of dicing an ultrathin Wafers and an associated Holding device and in particular to a method for separating an ultrathin Wafers in a variety of back-processed Single building blocks, using a conventional wafer test equipment performed a chip test can be.
Für eine Vielzahl von gegenwärtigen und zukünftigen Anwendungen von elektronischen Bauelementen und insbesondere von integrierten Schaltungen (IC, Integrated Circuit) ist es vorteilhaft, die Gesamtdicke dieser integrierten Schaltungen bzw. Halbleiterschaltungen auf wenige Mikrometer zu beschränken. Derart dünne Halbleiterschaltungen bzw. Chips haben eine sehr geringe Masse sowie Bauhöhe, weshalb sie für eine Vielzahl von Anwendungsfeldern, beispielsweise in der zukünftigen Wegwerf-Elektronik sowie für Chipkarten und Smartcards, von Bedeutung sind.For a variety from present and future ones Applications of electronic components and in particular of integrated circuit (IC), it is advantageous the total thickness of these integrated circuits or semiconductor circuits limited to a few microns. Such a thin one Semiconductor circuits or chips have a very low mass as well height, why she for a variety of application fields, for example in the future Disposable electronics as well as for Smart cards and smart cards are of importance.
Entsprechende ultradünne Wafer können beispielsweise anhand von herkömmlichen Halbleiterwafern hergestellt werden, die eine Ausgangsdicke von ca. 500 bis 1000 Mikrometer aufweisen und nach der Herstellung von jeweiligen Schaltelementen bis auf eine entsprechende Dicke dünn geschliffen werden.Appropriate ultrathin Wafers can, for example by conventional Semiconductor wafers are manufactured, which have an initial thickness of about 500 to 1000 microns and after the production of respective switching elements are ground thin to a corresponding thickness.
Da jedoch für zukünftige Halbleiterbauelemente Dicken von deutlich weniger als 100 Mikrometer erwünscht sind, wobei ferner insbesondere eine beidseitige Strukturierung bzw. eine zusätzliche Rückseitenprozessierung zur Ausbildung von neuartigen Halbleiterelementen gefordert ist, besteht ein wesentliches Problem bei der Herstellung von ultradünnen Halbleiterschaltungen in der Vermeidung eines Bruches von Dünnwafern bzw. gedünnten Halbleiterwafern sowohl während einer Herstellung als auch insbesondere bei einem Schaltungstest.There however for future Semiconductor devices have thicknesses of significantly less than 100 microns he wishes In particular, a two-sided structuring or an additional backside processing is required for the formation of novel semiconductor elements, There is a significant problem in the production of ultra-thin semiconductor circuits in avoiding breakage of thin wafers or thinned semiconductor wafers both during a production and in particular in a circuit test.
Zur Vermeidung eines derartigen Waferbruchs können die bruchgefährdeten ultradünnen Produktwafer mit einem normal dicken Trägerwafer verbunden werden, wodurch zumindest während der Waferherstellung für eine einseitige Prozessierung ein Waferbruch zuverlässig verhindert werden kann. Spätestens bei einem Wafertest bzw. bei einem Vereinzelungsvorgang ergeben sich jedoch erhöhte Probleme. Während eines (Rückseiten-) Wafertests werden diese Probleme bisher durch angepasstes, schonendes Hantieren der ultradünnen Wafer gelöst oder durch Verbinden des Waferrandes mit einem stabilisierenden Ring. Gleichwohl bleibt auch dann die auf dem Ring aufgespannte ultradünne Wafermembran bruchgefährdet. Ferner ist ein Vereinzeln des ultradünnen Wafers in Einzelbausteine bzw. Chips mit einer herkömmlichen Wafersäge nicht möglich, solange sich der verstärkende Ring am Waferrand befindet.to Prevention of such a wafer break can be the risk of breakage ultrathin product wafers connected to a normally thick carrier wafer be, at least during Wafer production for One-sided processing reliably prevents a wafer break can be. No later than result in a wafer test or a singulation process but increased Problems. While one (back) Wafer testing these problems so far by adapted, gentle Handling the ultrathin Wafers solved or by connecting the wafer edge to a stabilizing one Ring. Nevertheless, even then the spanned on the ring remains ultrathin Wafer membrane vulnerable to breakage. Furthermore, a singulation of the ultra-thin wafer into individual components or chips with a conventional one wafer saw not possible, as long as the reinforcing Ring is located at the wafer edge.
Aus
der Druckschrift
Der Erfindung liegt daher die Aufgabe zu Grunde ein alternatives Verfahren zum Vereinzeln eines ultradünnen Wafers sowie eine zugehörige Haltevorrichtung zu schaffen, wobei eine Bruchgefahr wesentlich verringert und ein Testen der integrierten Schaltungen mit herkömmlichem Wafer-Test-Equipment ermöglicht ist.Of the The invention is therefore based on the object of an alternative method for separating an ultrathin Wafers and an associated To provide holding device, wherein a risk of breakage essential reduces and testing the integrated circuits with conventional Wafer test equipment allows is.
Erfindungsgemäß wird diese Aufgabe hinsichtlich des Verfahrens durch die Maßnahmen des Patentanspruchs 1 und hinsichtlich der Haltevorrichtung durch die Merkmale des Patentanspruchs 21 gelöst.According to the invention this Task with regard to the method by the measures of the claim 1 and with regard to the holding device by the features of the patent claim 21 solved.
Insbesondere durch ein Befestigen eines Trägerwafers mit einem Bindemittel an einem Produktwafer, dem nachfolgenden Dünnen des Produktwafers, dem nachfolgenden Durchführen einer Rückseitenprozessierung und dem Ausbilden von Trenngräben zwischen den integrierten Schaltungen in einem Sägerahmenbereich des Produktwafers zur Realisierung von Einzelbausteinen können nach einem Ablegen des Trägerwafers mit den daran be festigten vorvereinzelten Einzelbausteinen auf einer Haltevorrichtung mit Stegen zum Festlegen von Baustein-Aufnahmebereichen, wobei die Stege in die Trenngräben eingreifen, und einem abschließenden Lösen des Trägerwafers bzw. des Bindemittels eine Vielzahl von vereinzelten Einzelbausteinen mit herkömmlichem Wafer-Equipment weiter verarbeitet und insbesondere auf seine Funktionsfähigkeit getestet werden.Especially by attaching a carrier wafer with a binder on a product wafer, the subsequent thinning of the Product wafers, then performing a back side processing and forming isolation trenches between the integrated circuits in a saw frame area of the product wafer for the realization of individual components can after a drop of the carrier wafer with the pre-separated individual components on one Retaining device with webs for defining component receiving areas, the webs in the separation trenches intervene, and a final release of the carrier wafer or the binder, a plurality of isolated individual components with conventional Wafer equipment further processed and in particular on its functionality be tested.
Obwohl die Trenngräben vorzugsweise nach der Rückseitenprozessierung ausgebildet werden, können sie auch vor dieser Rückseitenprozessierung ausgebildet werden und insbesondere auch bereits vor dem Befestigen des Trägerwafers an der Vorderseite des Produktwafers in üblicher Weise hergestellt werden.Although the isolation trenches are preferably formed after the backside processing, they may also prior to this backside processing be formed and in particular also already prepared before attaching the carrier wafer to the front of the product wafer in the usual way.
Beim Ausbilden der Trenngräben insbesondere von der Rückseite ergeben sich hierbei zusätzliche Entwicklungsmöglichkeiten zur Realisierung eines optimierten Randabschlusses. Beispielsweise bei Verwendung von integrierten Schaltungen mit pn-Übergängen, die bis zu den Trenngräben reichen, können die Trenngräben bzw. deren Geometrie an den Orten der pn-Übergänge derart ausgebildet werden, dass sich positive Bevel-Winkel ergeben. Auf diese Weise kann eine Feldlinienverdichtung bzw. -konzentration aufgefächert bzw. abgeschwächt werden, wodurch die elektrischen Eigenschaften für einen Randdurchbruch wesentlich verbessert sind.At the Forming the separation trenches especially from the back this will give additional development opportunities for the realization of an optimized edge termination. For example, at The use of integrated circuits with pn-junctions that extend to the trenches, the separating trenches or their geometry at the locations of the pn junctions in such a way be formed that give positive Bevel angle. To this Way, a field line compression or concentration can be fanned out or attenuated which makes the electrical properties essential for edge penetration are improved.
Insbesondere bei Verwendung einer elektrisch leitenden Haltevorrichtung können die bereits vereinzelten Einzelbausteine ohne Bruchgefahr und unter Verwendung von herkömmlichem Wafer-Equipment weiter verarbeitet und insbesondere getestet werden.Especially when using an electrically conductive holding device, the already isolated individual components without risk of breakage and under Use of conventional Wafer equipment further processed and tested in particular.
Die Haltevorrichtung zum Aufnehmen der vereinzelten Einzelbausteine weist hierbei einen waferförmigen Grundkörper und eine Vielzahl von an der Oberfläche des Grundkörpers ausgebildeten Stegen zum Festlegen von Baustein-Aufnahmebereichen auf, wodurch bereits unter Ausnutzung der Schwerkraft eine Aufnahme und weiterführende Bearbeitung der bereits vereinzelten Halbleiterbausteine auf Waferebene bzw. mit herkömmlichem Wafer-Equipment ermöglicht ist. Vorzugsweise weist die Haltevorrichtung für jeden Baustein-Aufnahmebereich ein Durchgangsloch zum Anlegen eines Unterdrucks auf, wodurch zusätzliche Haltekräfte wirken können und eine Handhabung beispielsweise auch in senkrechter oder sonstiger Position ermöglicht ist.The Holding device for receiving the isolated individual components here has a wafer-shaped body and a plurality of formed on the surface of the main body Jambs for defining block pickup areas, thereby already taking advantage of gravity recording and further processing the already isolated semiconductor devices at the wafer level or with conventional Wafer equipment allows is. Preferably, the holding device for each module receiving area a through hole for applying a negative pressure, whereby additional holding forces can act and handling, for example, in vertical or otherwise Position allows is.
Vorzugsweise ist eine Höhe der Stege hierbei kleiner als eine Dicke der ultradünnen Einzelbausteine, wodurch beispielsweise ein Anstoßen von Testnadeln an den Stegen zuverlässig verhindert werden kann.Preferably is a height the webs in this case smaller than a thickness of the ultrathin individual components, whereby, for example, an impact of test needles on the webs reliable can be prevented.
In den weiteren Unteransprüchen sind weitere vorteilhafte Ausgestaltungen der Erfindung gekennzeichnet.In the further subclaims Further advantageous embodiments of the invention are characterized.
Die Erfindung wird nachstehend anhand von Ausführungsbeispielen unter Bezugnahme auf die Zeichnung näher beschrieben.The Invention will now be described by way of embodiments with reference closer to the drawing described.
Es zeigen:It demonstrate:
Gemäß
Nach
einer derartigen Vorderseitenprozessierung wird mittels eines Bindemittels
Nach
diesem Befestigen des Trägerwafers
Anschließend erfolgt
eine Rückseitenprozessierung
des gedünnten
Produktwafers
Gemäß
Wesentlich
bei der Ausbildung der Trenngräben
Gemäß
Obwohl
das Ausbilden der Gräben
Gemäß
Vorzugsweise
besitzt die in der Art eines waferförmigen Magazins ausgebildete
Haltevorrichtung
Zum
Lösen des
Bindemittels
Auf diese Weise können hochgradig bruchgefährdete ultradünne Wafer (<< 100μm) in vorteilhafter Weise vereinzelt und anschließend mit herkömmlichem Wafer-Equipment weiter verarbeitet und insbesondere getestet werden.On this way you can high risk of breakage ultrathin Wafer (<< 100μm) in an advantageous Way isolated and then with conventional Wafer equipment further processed and tested in particular.
Zu
Realisierung eines Wafertests insbesondere der beschriebenen rückseitig
prozessierten Leistungshalbleiter-Bauelemente, besteht das waferförmige Magazin
bzw. die Haltevorrichtung
Gemäß
Alternativ
zu dieser durchgehenden Struktur der Stege
Ferner
können
die Stege
Wieder
zurückkehrend
zu
Die Erfindung wurde vorstehend anhand eines in einem Silizium-Halbleiterwafer hergestellten Leistungshalbleiter-Bauelements mit speziellen Dotierungen beschrieben. Sie ist jedoch nicht darauf beschränkt und umfasst in gleicher Weise auch alternative Halbleitermaterialien mit alternativen Dotiergebieten zur Ausbildung von alternativen integrierten Schaltungen.The The invention has been described above with reference to a silicon semiconductor wafer manufactured power semiconductor device with special dopants described. However, it is not limited to and includes the same Also alternative semiconductor materials with alternative doping regions for the formation of alternative integrated circuits.
Ferner
wurde zur Realisierung einer Haltekraft ein Vakuum-Durchgangsloch in
der Haltevorrichtung beschrieben. Die Erfindung ist jedoch nicht darauf
beschränkt
und umfasst zur Realisierung von Haltekräften auf die Einzelbausteine
Claims (27)
Priority Applications (1)
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DE200410023405 DE102004023405B4 (en) | 2004-05-12 | 2004-05-12 | Dicing ultra-thin wafer in to multiple integrated circuits, by fixing carrier wafer to front of product wafer, forming separating trenches between integrated circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200410023405 DE102004023405B4 (en) | 2004-05-12 | 2004-05-12 | Dicing ultra-thin wafer in to multiple integrated circuits, by fixing carrier wafer to front of product wafer, forming separating trenches between integrated circuits |
Publications (2)
Publication Number | Publication Date |
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DE102004023405A1 DE102004023405A1 (en) | 2005-12-15 |
DE102004023405B4 true DE102004023405B4 (en) | 2006-07-13 |
Family
ID=35404194
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006046788A1 (en) * | 2006-10-02 | 2008-04-03 | Infineon Technologies Ag | Method for manufacturing semiconductor circuit arrangement, involves preparing semiconductor substrate and implementing processing on back side of semiconductor substrate |
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Publication number | Priority date | Publication date | Assignee | Title |
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DE102009054659A1 (en) * | 2009-12-15 | 2011-06-16 | Robert Bosch Gmbh | Production of a component |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1255296A2 (en) * | 2001-04-25 | 2002-11-06 | Filtronic Compound Semiconductor Limited | Semi-conductor wafer handling method |
-
2004
- 2004-05-12 DE DE200410023405 patent/DE102004023405B4/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1255296A2 (en) * | 2001-04-25 | 2002-11-06 | Filtronic Compound Semiconductor Limited | Semi-conductor wafer handling method |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006046788A1 (en) * | 2006-10-02 | 2008-04-03 | Infineon Technologies Ag | Method for manufacturing semiconductor circuit arrangement, involves preparing semiconductor substrate and implementing processing on back side of semiconductor substrate |
DE102006046788B4 (en) * | 2006-10-02 | 2009-06-25 | Infineon Technologies Ag | Method for producing a semiconductor circuit arrangement |
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