US20160372336A1 - Method for Manufacturing a Semiconductor Device by Hydrogen Treatment - Google Patents
Method for Manufacturing a Semiconductor Device by Hydrogen Treatment Download PDFInfo
- Publication number
- US20160372336A1 US20160372336A1 US15/253,418 US201615253418A US2016372336A1 US 20160372336 A1 US20160372336 A1 US 20160372336A1 US 201615253418 A US201615253418 A US 201615253418A US 2016372336 A1 US2016372336 A1 US 2016372336A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor
- porous area
- semiconductor layer
- forming
- porosity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 174
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 title claims abstract description 31
- 229910052739 hydrogen Inorganic materials 0.000 title claims abstract description 31
- 239000001257 hydrogen Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 title claims description 25
- 238000011282 treatment Methods 0.000 title description 2
- 238000000926 separation method Methods 0.000 claims abstract description 10
- 238000007669 thermal treatment Methods 0.000 claims abstract description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 11
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000004090 dissolution Methods 0.000 claims description 7
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 2
- 239000000126 substance Substances 0.000 claims 2
- 239000011148 porous material Substances 0.000 description 18
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 9
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 5
- ZMXDDKWLCZADIW-UHFFFAOYSA-N N,N-Dimethylformamide Chemical compound CN(C)C=O ZMXDDKWLCZADIW-UHFFFAOYSA-N 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 2
- 239000005052 trichlorosilane Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3223—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering using cavities formed by hydrogen or noble gas ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02378—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02513—Microstructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
Definitions
- the overall thickness of the semiconductor device and the integrated circuits are advantageous.
- low weight and small dimensions are relevant for chip cards and smartcards.
- the electrical properties of devices such as vertical power semiconductor elements can be improved by specific adjustment of the thickness of the semiconductor body. By matching the thickness of the semiconductor body to the voltage class of the respective power semiconductor element, unwanted electric resistance of oversized semiconductor bodies may be prevented.
- a precise and reliable adjustment of a thickness of a semiconductor body is desirable to avoid losses in the yield of manufacturing and to assure reliable electrical characteristics of semiconductor devices and integrated circuits, respectively.
- the method includes forming a porous area at a surface of a semiconductor body.
- the semiconductor body includes a porous structure in the porous area.
- the method further includes forming a semiconductor layer on the porous area, and forming semiconductor regions in the semiconductor layer.
- the method further includes separating the semiconductor layer from the semiconductor body along the porous area. Separating the semiconductor layer from the semiconductor body includes introducing hydrogen into the porous area by a thermal treatment.
- FIGS. 1A to 1E illustrate schematic views of cross sections of a semiconductor body to which the manufacturing method according to an embodiment is applied.
- FIGS. 2A and 2B illustrate schematic views of cross sections of semiconductor bodies, which are subject to manufacturing methods according to embodiments.
- lateral and “horizontal” as used in this specification intends to describe an orientation parallel to a first surface of a semiconductor substrate or semiconductor body. This can be for instance the surface of a wafer or a die.
- vertical as used in this specification intends to describe an orientation which is arranged perpendicular to the first surface of the semiconductor substrate or semiconductor body.
- FIGS. 1A to 1D illustrate schematic vie s of cross sections of a semiconductor device during different phases of a manufacturing method.
- the schematic cross section of FIG, 1 A illustrates a semiconductor body 100 .
- the semiconductor body 100 includes or is made of silicon (Si).
- the semiconductor body 100 includes or is made of silicon carbide (SiC).
- Si and SEC semiconductor bodies are made of single crystalline material, but the semiconductor body may also include polycrystalline or amorphous material parts.
- a porous area 101 is formed at a first surface of the semiconductor body 100 by altering the crystal structure of the semiconductor body 100 at the first surface from e.g. a single- or multi-crystalline structure into a porous structure. Then, the semiconductor body 100 includes a porous structure in the porous area 101 .
- the porous structure in the porous area 101 can be manufactured by anodic oxidation of Si or SiC using one or more solution(s) containing fluoride (F). As an example, a solution containing hydrofluoric acid (HF) and ethanol or acetic acid is used. Also other solutions which are configured to alter the crystal structure to a porous structure can be employed (e.g. HF/Dimethylformamide, HF/acenitrile, etc.) optionally using or avoiding an external light source.
- the solution Upon physical contact of the solution and the semiconductor body 100 , a reaction occurs which causes the semiconductor body 100 to alter its structure into a porous structure, This reaction as well as the respective effect begins at the surface of the semiconductor body 100 and propagates into the semiconductor body 100 .
- the solution is typically applied from a front surface 100 f of the semiconductor body 100 .
- the porosity of the porous area can be controlled by choosing proper values for parameters such as current density and HF concentration in the solution.
- the porous structure of the porous area 101 includes a plurality of cavities such as meso-pores and/or nano-pores. Typical pore sizes for nano-pores are below approximately 2 nm, meso-pores have 2 nm up to approximately 100 nm pore size and macro-pores can have sizes in the ⁇ m range. Porosities of up to or more than 70% may be achieved. According to an embodiment, the porosity at the surface is kept small enough so as to allow appropriate growth of further layers on the porous area 101 .
- Such further layers may also be grown on a porous area 101 with pores including dimensions in the nm up to ⁇ m range, e.g. nano-pores, meso-pores or even macro-pores.
- a high temperature TCS (trichlorosilane) epitaxial growth process with temperatures in the range of 1050° C. up to 1230° C. or in the range of 1150° C. up to 1200° C. may be employed for growing a further layer on the porous area 101 .
- a semiconductor layer 102 is formed on the porous area 101 .
- the semiconductor layer 102 corresponds to a further layer to be arranged on the porous area 101 as described above, and is for example grown or deposited on the porous area 101 having the porous structure.
- the semiconductor layer 102 is formed by epitaxial growth so as to have a desired thickness.
- the semiconductor layer 102 is formed so as to have a thickness in a range of 5 ⁇ m to 200 ⁇ m, or in a range of 20 ⁇ m to 170 ⁇ m or in a range of 35 ⁇ m to 150 ⁇ m.
- regions 103 a, 103 b, 103 c are formed in the semiconductor layer 102 , so as to form functional elements.
- the regions 103 a, 103 b, 103 c may include semiconductor regions formed by ion implantation and/or diffusion of impurities into the semiconductor layer 102 .
- the semiconductor regions may be formed by different lithographic steps, for example.
- the semiconductor regions may include n-type, p-type or a combination of n-type and p-type regions. Examples for the semiconductor regions include source, drain, body, emitter, base, and/or collector regions.
- the regions 103 a, 103 b, 103 c may also include dielectric and conductive materials on or close to the surface of the semiconductor regions including a planar gate dielectric and a planar gate electrode.
- the regions 103 a, 103 b, 103 c may also include trench structures including dielectric and conductive materials therein, e.g. a trench including a gate dielectric and a gate electrode.
- the regions 103 a, 103 b and 103 c may include electrical and/or micromechanical elements formed in the semiconductor layer 102 .
- a plurality of processes can be applied for forming the regions 103 a, 103 b , 103 c in the semiconductor layer 102 , such as etching, application of laser light, doping, polishing, material deposition or growth, and other treatments, and in particular also various combinations of such processes.
- regions 103 of the semiconductor layer 102 can be appropriately doped so as to achieve desired doping concentrations for a respective desired functions of a semiconductor device.
- the semiconductor layer 102 is separated from the semiconductor body 100 along the porous area 101 .
- Separating the semiconductor layer 102 from the semiconductor body 100 includes introducing hydrogen into the porous area 101 of the semiconductor body 100 by a thermal treatment.
- introducing hydrogen into the porous area 101 can also come along with introducing hydrogen into the overall semiconductor body 100 , as long as the introduced hydrogen is applied to the porous area 101 . Therefore, the hydrogen to be introduced into the porous a ea 101 can for example be applied from a rear side 100 b of the semiconductor body 100 . Alternatively, or in addition to introducing hydrogen from the rear side 102 b , hydrogen is introduced from the front surface 100 f of the semiconductor body 100 , which means from or through the semiconductor layer 102 to be separated.
- a thermal treatment supports introduction of hydrogen into the porous area 101 by e.g. enhanced diffusion.
- a thermal treatment of semiconductor material adjacent to a hydrogen containing atmosphere which is then present in the pores can lead to an increased surface mobility of the semiconductor atoms and thus to an easier re-arrangement or reallocation of the semiconductor atoms.
- the hydrogen can be introduced into or near the porous area 101 by way of diffusion, for example. However, it is also possible to implant hydrogen into the porous area 101 . Also a combination of diffusing hydrogen into the semiconductor body 100 and implanting hydrogen into the semiconductor body 100 may be used.
- an implant dose of hydrogen can for example be lower than 10 16 cm ⁇ 2 . e.g. in a range of 5 ⁇ 10 ⁇ 2 to 5 ⁇ 10 16 cm ⁇ 2 .
- the energy can for example be in the range of 150 keV to 4 MeV.
- forming the porous area 101 of the semiconductor body can include—in particular partial—anodic dissolution of the semiconductor body 100 .
- meso-pores i.e. pores with an average size between approximately 2 nm and approximately 100 nm may be advantageous, since they come along with smaller Si or SiC structures around the actual pores. This allows an easier separation of the semiconductor layer 102 from the semiconductor body 100 due to a higher surface mobility of the Si atoms and/or C atoms and/or formation of volatile C—H compounds, respectively, as well as higher radii of curvature and a larger overall surface area in the separation volume. These effects and benefits can also be achieved with porosities including pore sizes in the range of nm or sub-nm, i.e. nano-pores.
- the above described separation process of the semiconductor layer 102 that may have undergone processing of devices and wiring at the front surface leads to a semiconductor device having a precisely adjusted thickness of its semiconductor body.
- the variation of the thickness over the semiconductor body is small and may be smaller than 10%, smaller than 8%, smaller than 4% or even smaller than 2% of the total thickness of the semiconductor body to assure reliable electrical characteristics of semiconductor devices and integrated circuits formed therein, respectively.
- FIG. 1E In the schematic cross section of FIG. 1E , a semiconductor body 100 , a porous area 101 , a semiconductor layer 102 , and regions 103 a, 103 b, 103 c in the semiconductor layer 102 similar to FIGS. 1B and 1D are illustrated. Moreover, trenches 104 a and 104 b are illustrated, which are provided in order to facilitate the application of hydrogen to the porous structure.
- the trenches 104 a and 104 b can be provided alternatively or in arbitrary combinations and number and may include trench side walls having no or different degrees of taper.
- Trench 104 a is formed in the semiconductor layer 102 and may extend through the semiconductor layer 102 to the porous area 101 or end within the semiconductor layer 102 .
- Trench 104 a facilitates the application of hydrogen to the porous area 101 because the hydrogen can more easily reach the porous area 101 .
- a trench 104 b is provided at the reverse side of the semiconductor body 100 .
- Trench 104 b can also extended up to the porous area 101 or end within the semiconductor body 100 before reaching the porous area 101 .
- trench 104 b facilitates the application of hydrogen to the porous area 101 because the hydrogen can more easily reach the porous area 101 .
- trench 104 a may be formed after forming the semiconductor layer 102 on the semiconductor body 100
- trench 104 b may be formed before or after forming the semiconductor layer 102 on the semiconductor body 100 .
- forming the porous area 101 includes forming a double porosity structure including a first porous area having a first porosity and a second porous area deeper within the semiconductor body 100 having a second porosity.
- the porosity of the porous areas can be controlled by choosing proper values for parameters such as current density and/or HF concentration in the solution and/or intensity of light irradiation.
- the first porosity is set to be smaller than the second porosity.
- FIG. 2A where a first porous area 101 a is formed in the semiconductor body 100 , and a second porous area 101 b is also formed below the first porous area 101 a, i.e. deeper in the semiconductor body 100 .
- a porosity of the first porous area 101 a is set in a range between 10% and 50% and the porosity of the second porous area 101 b is set in a range between the porosity of the first porous area 101 a and 80%.
- Selecting the first porosity smaller than the second porosity allows to improve the crystal quality of a semiconductor layer 102 grown on the first porous area 101 a by adjusting the first porosity and to improve separation of the semiconductor layer 102 from the semiconductor body 100 by adjusting the second porosity in the second porous area 101 b.
- FIG. 2B illustrates yet another embodiment including, in addition the embodiment illustrated in FIG. 2A , a third porous area 101 c that is arranged deeper within the semiconductor body 100 with respect to both the first and the second porous areas 101 a and 101 b. Accordingly, the porosity of the first porous area 101 a is set smaller than the porosity of the second and the third porous areas 101 b and 101 c. Also, the third porous area 101 c has the largest porosity of the three porous areas 101 a, 101 a, and 101 c.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Weting (AREA)
Abstract
Description
- For a plurality of applications of electronic semiconductor devices and integrated circuits (IC) it is advantageous to limit the overall thickness of the semiconductor device and the integrated circuits, respectively. For example, low weight and small dimensions are relevant for chip cards and smartcards. Likewise, the electrical properties of devices such as vertical power semiconductor elements can be improved by specific adjustment of the thickness of the semiconductor body. By matching the thickness of the semiconductor body to the voltage class of the respective power semiconductor element, unwanted electric resistance of oversized semiconductor bodies may be prevented.
- Thus, a precise and reliable adjustment of a thickness of a semiconductor body is desirable to avoid losses in the yield of manufacturing and to assure reliable electrical characteristics of semiconductor devices and integrated circuits, respectively.
- According to one embodiment of a method of manufacturing a semiconductor device, the method includes forming a porous area at a surface of a semiconductor body. The semiconductor body includes a porous structure in the porous area. The method further includes forming a semiconductor layer on the porous area, and forming semiconductor regions in the semiconductor layer. The method further includes separating the semiconductor layer from the semiconductor body along the porous area. Separating the semiconductor layer from the semiconductor body includes introducing hydrogen into the porous area by a thermal treatment.
- Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
- The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other.
- Embodiments are depicted in the drawings and are detailed in the description which follows.
-
FIGS. 1A to 1E illustrate schematic views of cross sections of a semiconductor body to which the manufacturing method according to an embodiment is applied. -
FIGS. 2A and 2B illustrate schematic views of cross sections of semiconductor bodies, which are subject to manufacturing methods according to embodiments. - In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in 25 which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, “leading”, “trailing”, “over”, “above”, “below”, etc., is used with reference to the orientation of the Figure(s) being described. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing processes have been designated by the same references in the different drawings if not stated otherwise.
- The terms “lateral” and “horizontal” as used in this specification intends to describe an orientation parallel to a first surface of a semiconductor substrate or semiconductor body. This can be for instance the surface of a wafer or a die. The term “vertical” as used in this specification intends to describe an orientation which is arranged perpendicular to the first surface of the semiconductor substrate or semiconductor body.
- In the following, exemplary embodiments are explained with reference to the Figures. The invention is, however, not limited to the embodiments which are described in detail, but can be modified and varied in appropriate ways. Particular features and combination of features of an embodiment can be appropriately combined with features and combinations of features of another embodiment, as far as this is not explicitly excluded.
-
FIGS. 1A to 1D illustrate schematic vie s of cross sections of a semiconductor device during different phases of a manufacturing method. - The schematic cross section of FIG, 1A illustrates a
semiconductor body 100. According to one embodiment, thesemiconductor body 100 includes or is made of silicon (Si). According to another embodiment, thesemiconductor body 100 includes or is made of silicon carbide (SiC). Typically, Si and SEC semiconductor bodies are made of single crystalline material, but the semiconductor body may also include polycrystalline or amorphous material parts. - Referring to the schematic cross section of
FIG. 1B , aporous area 101 is formed at a first surface of thesemiconductor body 100 by altering the crystal structure of thesemiconductor body 100 at the first surface from e.g. a single- or multi-crystalline structure into a porous structure. Then, thesemiconductor body 100 includes a porous structure in theporous area 101. The porous structure in theporous area 101 can be manufactured by anodic oxidation of Si or SiC using one or more solution(s) containing fluoride (F). As an example, a solution containing hydrofluoric acid (HF) and ethanol or acetic acid is used. Also other solutions which are configured to alter the crystal structure to a porous structure can be employed (e.g. HF/Dimethylformamide, HF/acenitrile, etc.) optionally using or avoiding an external light source. - Upon physical contact of the solution and the
semiconductor body 100, a reaction occurs which causes thesemiconductor body 100 to alter its structure into a porous structure, This reaction as well as the respective effect begins at the surface of thesemiconductor body 100 and propagates into thesemiconductor body 100. Hence, the solution is typically applied from afront surface 100 f of thesemiconductor body 100. The porosity of the porous area can be controlled by choosing proper values for parameters such as current density and HF concentration in the solution. - The porous structure of the
porous area 101 includes a plurality of cavities such as meso-pores and/or nano-pores. Typical pore sizes for nano-pores are below approximately 2 nm, meso-pores have 2 nm up to approximately 100 nm pore size and macro-pores can have sizes in the μm range. Porosities of up to or more than 70% may be achieved. According to an embodiment, the porosity at the surface is kept small enough so as to allow appropriate growth of further layers on theporous area 101. - However, such further layers may also be grown on a
porous area 101 with pores including dimensions in the nm up to μm range, e.g. nano-pores, meso-pores or even macro-pores. In this case, a high temperature TCS (trichlorosilane) epitaxial growth process with temperatures in the range of 1050° C. up to 1230° C. or in the range of 1150° C. up to 1200° C. may be employed for growing a further layer on theporous area 101. - After forming the
porous area 101, and as illustrated in the schematic cross section ofFIG. 10 , asemiconductor layer 102 is formed on theporous area 101. Thesemiconductor layer 102 corresponds to a further layer to be arranged on theporous area 101 as described above, and is for example grown or deposited on theporous area 101 having the porous structure. Typically, thesemiconductor layer 102 is formed by epitaxial growth so as to have a desired thickness. According to an embodiment, thesemiconductor layer 102 is formed so as to have a thickness in a range of 5 μm to 200 μm, or in a range of 20 μm to 170 μm or in a range of 35 μm to 150 μm. - Then,
regions semiconductor layer 102, so as to form functional elements. As an example theregions semiconductor layer 102. The semiconductor regions may be formed by different lithographic steps, for example. The semiconductor regions may include n-type, p-type or a combination of n-type and p-type regions. Examples for the semiconductor regions include source, drain, body, emitter, base, and/or collector regions. Theregions regions regions semiconductor layer 102. Accordingly, a plurality of processes can be applied for forming theregions semiconductor layer 102, such as etching, application of laser light, doping, polishing, material deposition or growth, and other treatments, and in particular also various combinations of such processes. For example,regions 103 of thesemiconductor layer 102 can be appropriately doped so as to achieve desired doping concentrations for a respective desired functions of a semiconductor device. - Then, as illustrated in the cross section of
FIG. 1D , thesemiconductor layer 102 is separated from thesemiconductor body 100 along theporous area 101. Separating thesemiconductor layer 102 from thesemiconductor body 100 includes introducing hydrogen into theporous area 101 of thesemiconductor body 100 by a thermal treatment. - In particular, introducing hydrogen into the
porous area 101 can also come along with introducing hydrogen into theoverall semiconductor body 100, as long as the introduced hydrogen is applied to theporous area 101. Therefore, the hydrogen to be introduced into the porous aea 101 can for example be applied from arear side 100 b of thesemiconductor body 100. Alternatively, or in addition to introducing hydrogen from the rear side 102 b, hydrogen is introduced from thefront surface 100 f of thesemiconductor body 100, which means from or through thesemiconductor layer 102 to be separated. A thermal treatment supports introduction of hydrogen into theporous area 101 by e.g. enhanced diffusion. Furthermore, a thermal treatment of semiconductor material adjacent to a hydrogen containing atmosphere which is then present in the pores can lead to an increased surface mobility of the semiconductor atoms and thus to an easier re-arrangement or reallocation of the semiconductor atoms. - When the hydrogen is introduced into the
porous area 101, respective pores of the porous structure in theporous area 101 are reallocated, i.e. rearranged in such way, that cavities are arranged along a level of thesemiconductor body 100 and thesemiconductor body 100 is separated from thesemiconductor layer 102 along theporous area 101. - The hydrogen can be introduced into or near the
porous area 101 by way of diffusion, for example. However, it is also possible to implant hydrogen into theporous area 101. Also a combination of diffusing hydrogen into thesemiconductor body 100 and implanting hydrogen into thesemiconductor body 100 may be used. - When the hydrogen is introduced into the
porous area 101 by way of ion-implantation, an implant dose of hydrogen can for example be lower than 1016 cm−2. e.g. in a range of 5·10−2 to 5·1016 cm−2. Moreover, the energy can for example be in the range of 150 keV to 4 MeV. - Moreover, forming the
porous area 101 of the semiconductor body can include—in particular partial—anodic dissolution of thesemiconductor body 100. - As already described above, meso-pores, i.e. pores with an average size between approximately 2 nm and approximately 100 nm may be advantageous, since they come along with smaller Si or SiC structures around the actual pores. This allows an easier separation of the
semiconductor layer 102 from thesemiconductor body 100 due to a higher surface mobility of the Si atoms and/or C atoms and/or formation of volatile C—H compounds, respectively, as well as higher radii of curvature and a larger overall surface area in the separation volume. These effects and benefits can also be achieved with porosities including pore sizes in the range of nm or sub-nm, i.e. nano-pores. - When hydrogen is introduced into the
porous area 101, a relocation of Si or SiC, respectively, takes place, which is thermally activated. The relocation is also further supported by the hydrogen introduced into theporous area 101 and corresponds to a reduction of the surface area quantity in theporous area 101, causing actual cavities to be generated. By further increasing the Si or SiC mobility in theporous area 101, besides the separation of thesemiconductor layer 102 from thesemiconductor body 100, also a levelling of the latter can be achieved. - This means that in case parts of the
porous area 101 will adhere to thesemiconductor layer 102 after its separation from thesemiconductor body 100, these parts do not have to be removed by etching or polishing, because such parts may have a negligible thickness and are already smoothed. Hence, as thesemiconductor layer 102 is not subject to further etching or polishing processes after the separation from thesemiconductor body 100, thesemiconductor layer 102 can be realized having a very small thickness. However, typical rear side processing such as ion implantation or laser annealing can be applied to the separatedsemiconductor body 102 without difficulty. - The above described separation process of the
semiconductor layer 102 that may have undergone processing of devices and wiring at the front surface leads to a semiconductor device having a precisely adjusted thickness of its semiconductor body. The variation of the thickness over the semiconductor body is small and may be smaller than 10%, smaller than 8%, smaller than 4% or even smaller than 2% of the total thickness of the semiconductor body to assure reliable electrical characteristics of semiconductor devices and integrated circuits formed therein, respectively. - In the schematic cross section of
FIG. 1E , asemiconductor body 100, aporous area 101, asemiconductor layer 102, andregions semiconductor layer 102 similar toFIGS. 1B and 1D are illustrated. Moreover,trenches trenches - Trench 104 a is formed in the
semiconductor layer 102 and may extend through thesemiconductor layer 102 to theporous area 101 or end within thesemiconductor layer 102. Trench 104 a facilitates the application of hydrogen to theporous area 101 because the hydrogen can more easily reach theporous area 101. - Alternatively or in addition to the
trench 104 a, atrench 104 b is provided at the reverse side of thesemiconductor body 100. Trench 104 b can also extended up to theporous area 101 or end within thesemiconductor body 100 before reaching theporous area 101. Again,trench 104 b facilitates the application of hydrogen to theporous area 101 because the hydrogen can more easily reach theporous area 101. Whiletrench 104 a may be formed after forming thesemiconductor layer 102 on thesemiconductor body 100,trench 104 b may be formed before or after forming thesemiconductor layer 102 on thesemiconductor body 100. - According to another embodiment, forming the
porous area 101 includes forming a double porosity structure including a first porous area having a first porosity and a second porous area deeper within thesemiconductor body 100 having a second porosity. The porosity of the porous areas can be controlled by choosing proper values for parameters such as current density and/or HF concentration in the solution and/or intensity of light irradiation. - According to an embodiment, the first porosity is set to be smaller than the second porosity. This is for example illustrated in
FIG. 2A , where a first porous area 101 a is formed in thesemiconductor body 100, and a second porous area 101 b is also formed below the first porous area 101 a, i.e. deeper in thesemiconductor body 100. As an example, a porosity of the first porous area 101 a is set in a range between 10% and 50% and the porosity of the second porous area 101 b is set in a range between the porosity of the first porous area 101 a and 80%. Selecting the first porosity smaller than the second porosity allows to improve the crystal quality of asemiconductor layer 102 grown on the first porous area 101 a by adjusting the first porosity and to improve separation of thesemiconductor layer 102 from thesemiconductor body 100 by adjusting the second porosity in the second porous area 101 b. -
FIG. 2B illustrates yet another embodiment including, in addition the embodiment illustrated inFIG. 2A , a thirdporous area 101 c that is arranged deeper within thesemiconductor body 100 with respect to both the first and the second porous areas 101 a and 101 b. Accordingly, the porosity of the first porous area 101 a is set smaller than the porosity of the second and the thirdporous areas 101 b and 101 c. Also, the thirdporous area 101 c has the largest porosity of the threeporous areas 101 a, 101 a, and 101 c. - It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise. Terms such as “first”, “second”, and the like, are used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description,
- As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as ell as the singular, unless the context clearly indicates otherwise.
- Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
Claims (18)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/253,418 US20160372336A1 (en) | 2011-09-12 | 2016-08-31 | Method for Manufacturing a Semiconductor Device by Hydrogen Treatment |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/229,861 US8883612B2 (en) | 2011-09-12 | 2011-09-12 | Method for manufacturing a semiconductor device |
US14/511,828 US9449847B2 (en) | 2011-09-12 | 2014-10-10 | Method for manufacturing a semiconductor device by thermal treatment with hydrogen |
US15/253,418 US20160372336A1 (en) | 2011-09-12 | 2016-08-31 | Method for Manufacturing a Semiconductor Device by Hydrogen Treatment |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/511,828 Continuation US9449847B2 (en) | 2011-09-12 | 2014-10-10 | Method for manufacturing a semiconductor device by thermal treatment with hydrogen |
Publications (1)
Publication Number | Publication Date |
---|---|
US20160372336A1 true US20160372336A1 (en) | 2016-12-22 |
Family
ID=47740333
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/229,861 Active US8883612B2 (en) | 2011-09-12 | 2011-09-12 | Method for manufacturing a semiconductor device |
US14/511,828 Active US9449847B2 (en) | 2011-09-12 | 2014-10-10 | Method for manufacturing a semiconductor device by thermal treatment with hydrogen |
US15/253,418 Abandoned US20160372336A1 (en) | 2011-09-12 | 2016-08-31 | Method for Manufacturing a Semiconductor Device by Hydrogen Treatment |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/229,861 Active US8883612B2 (en) | 2011-09-12 | 2011-09-12 | Method for manufacturing a semiconductor device |
US14/511,828 Active US9449847B2 (en) | 2011-09-12 | 2014-10-10 | Method for manufacturing a semiconductor device by thermal treatment with hydrogen |
Country Status (3)
Country | Link |
---|---|
US (3) | US8883612B2 (en) |
CN (1) | CN103000493B (en) |
DE (1) | DE102012108473B4 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102019106124A1 (en) * | 2018-03-22 | 2019-09-26 | Infineon Technologies Ag | Forming semiconductor devices in silicon carbide |
DE102019108754A1 (en) * | 2019-03-06 | 2020-09-10 | Infineon Technologies Ag | SEMICONDUCTOR DEVICE WITH A POROUS AREA, WAFER COMPOSITE STRUCTURE, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE |
US11710656B2 (en) * | 2019-09-30 | 2023-07-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor-on-insulator (SOI) substrate |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6020250A (en) * | 1994-08-11 | 2000-02-01 | International Business Machines Corporation | Stacked devices |
US20010014516A1 (en) * | 2000-02-12 | 2001-08-16 | Rohm Co., Ltd. | Method for manufacturing semiconductor device and ultrathin semiconductor device |
US20040110378A1 (en) * | 2002-08-26 | 2004-06-10 | Bruno Ghyselen | Recycling of a wafer comprising a buffer layer after having separated a thin layer therefrom by mechanical means |
US7157352B2 (en) * | 2002-10-11 | 2007-01-02 | Sony Corporation | Method for producing ultra-thin semiconductor device |
US20080286939A1 (en) * | 2007-05-17 | 2008-11-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
US7557002B2 (en) * | 2006-08-18 | 2009-07-07 | Micron Technology, Inc. | Methods of forming transistor devices |
US20090233079A1 (en) * | 2003-10-15 | 2009-09-17 | International Business Machines Corporation | Techniques for Layer Transfer Processing |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6107213A (en) * | 1996-02-01 | 2000-08-22 | Sony Corporation | Method for making thin film semiconductor |
CN1132223C (en) * | 1995-10-06 | 2003-12-24 | 佳能株式会社 | Semiconductor substrate and producing method thereof |
US6191007B1 (en) * | 1997-04-28 | 2001-02-20 | Denso Corporation | Method for manufacturing a semiconductor substrate |
US6534380B1 (en) * | 1997-07-18 | 2003-03-18 | Denso Corporation | Semiconductor substrate and method of manufacturing the same |
EP0926709A3 (en) * | 1997-12-26 | 2000-08-30 | Canon Kabushiki Kaisha | Method of manufacturing an SOI structure |
JP2000294818A (en) * | 1999-04-05 | 2000-10-20 | Sony Corp | Thin film semiconductor device and manufacture thereof |
JP4329183B2 (en) * | 1999-10-14 | 2009-09-09 | ソニー株式会社 | Method for manufacturing single cell thin film single crystal silicon solar cell, method for manufacturing back contact thin film single crystal silicon solar cell, and method for manufacturing integrated thin film single crystal silicon solar cell |
JP4708577B2 (en) * | 2001-01-31 | 2011-06-22 | キヤノン株式会社 | Method for manufacturing thin film semiconductor device |
US7622363B2 (en) * | 2003-05-06 | 2009-11-24 | Canon Kabushiki Kaisha | Semiconductor substrate, semiconductor device, light emitting diode and producing method therefor |
US7160753B2 (en) * | 2004-03-16 | 2007-01-09 | Voxtel, Inc. | Silicon-on-insulator active pixel sensors |
US7153761B1 (en) * | 2005-10-03 | 2006-12-26 | Los Alamos National Security, Llc | Method of transferring a thin crystalline semiconductor layer |
EP1798764A1 (en) * | 2005-12-14 | 2007-06-20 | STMicroelectronics S.r.l. | Process for manufacturing wafers usable in the semiconductor industry |
JP5459900B2 (en) * | 2007-12-25 | 2014-04-02 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
US7923279B2 (en) * | 2009-01-21 | 2011-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for reducing cross-talk in image sensor devices |
US8148237B2 (en) | 2009-08-07 | 2012-04-03 | Varian Semiconductor Equipment Associates, Inc. | Pressurized treatment of substrates to enhance cleaving process |
WO2012034993A1 (en) * | 2010-09-13 | 2012-03-22 | Imec | Method for fabricating thin photovoltaic cells |
US8822306B2 (en) * | 2010-09-30 | 2014-09-02 | Infineon Technologies Ag | Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core |
-
2011
- 2011-09-12 US US13/229,861 patent/US8883612B2/en active Active
-
2012
- 2012-09-11 DE DE102012108473.4A patent/DE102012108473B4/en active Active
- 2012-09-12 CN CN201210337659.7A patent/CN103000493B/en active Active
-
2014
- 2014-10-10 US US14/511,828 patent/US9449847B2/en active Active
-
2016
- 2016-08-31 US US15/253,418 patent/US20160372336A1/en not_active Abandoned
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6020250A (en) * | 1994-08-11 | 2000-02-01 | International Business Machines Corporation | Stacked devices |
US20010014516A1 (en) * | 2000-02-12 | 2001-08-16 | Rohm Co., Ltd. | Method for manufacturing semiconductor device and ultrathin semiconductor device |
US20040110378A1 (en) * | 2002-08-26 | 2004-06-10 | Bruno Ghyselen | Recycling of a wafer comprising a buffer layer after having separated a thin layer therefrom by mechanical means |
US7157352B2 (en) * | 2002-10-11 | 2007-01-02 | Sony Corporation | Method for producing ultra-thin semiconductor device |
US20090233079A1 (en) * | 2003-10-15 | 2009-09-17 | International Business Machines Corporation | Techniques for Layer Transfer Processing |
US7557002B2 (en) * | 2006-08-18 | 2009-07-07 | Micron Technology, Inc. | Methods of forming transistor devices |
US20080286939A1 (en) * | 2007-05-17 | 2008-11-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
Also Published As
Publication number | Publication date |
---|---|
US8883612B2 (en) | 2014-11-11 |
US20150056784A1 (en) | 2015-02-26 |
DE102012108473A1 (en) | 2013-03-14 |
US20130065379A1 (en) | 2013-03-14 |
CN103000493A (en) | 2013-03-27 |
US9449847B2 (en) | 2016-09-20 |
CN103000493B (en) | 2017-09-05 |
DE102012108473B4 (en) | 2019-03-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI269384B (en) | Formation of patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by porous Si engineering | |
US8470689B2 (en) | Method for forming a multilayer structure | |
US10276656B2 (en) | Method of manufacturing semiconductor devices by using epitaxy and semiconductor devices with a lateral structure | |
TW200933750A (en) | MOSFET active area and edge termination area charge balance | |
US9123769B2 (en) | Power semiconductor device and fabrication method thereof | |
CN1684243A (en) | Method for producing silicon insulator lining structure | |
US20160372336A1 (en) | Method for Manufacturing a Semiconductor Device by Hydrogen Treatment | |
US10714377B2 (en) | Semiconductor device and semiconductor wafer including a porous layer and method of manufacturing | |
KR20170005139A (en) | Simplified charge balance in a semiconductor device | |
JP4931212B2 (en) | Thin buried oxide by low dose oxygen implantation into modified silicon | |
KR20110091482A (en) | Structure and method for post oxidation silicon trench bottom shaping | |
KR20170046070A (en) | Soi structure and fabrication method | |
JP4637920B2 (en) | Porous silicon and method for producing the same | |
JP5528430B2 (en) | Formation method of oxide layer | |
US10825954B2 (en) | Porous-silicon light-emitting device and manufacturing method thereof | |
JP6273322B2 (en) | Manufacturing method of SOI substrate | |
JP4272607B2 (en) | SOI by oxidation of porous silicon | |
TW200426902A (en) | Member and member manufacturing method | |
TW493249B (en) | Manufacture method of dynamic random access memory cell capacitor | |
WO2002005341A1 (en) | Method of manufacturing power silicon transistor | |
CN1914721A (en) | Formation of patterned silicon-on-insulator (soi)/silicon-on-nothing (son) composite structure by porous si engineering | |
WO2001009943A1 (en) | Process for the forming of isolation layers of a predetermined thickness in semiconductor wafers for the manufacturing of integrated circuits | |
Philipp et al. | SWOP—Charge Carrier Depth Profiling of Boron Doped Single Crystalline Silicon | |
RU2433501C2 (en) | Method for semiconductor device fabrication | |
JPWO2023149131A5 (en) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AUSTRIA AG, AUSTRIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MAUDER, ANTON;AHRENS, CARSTEN;SANTOS RODRIGUEZ, FRANCISCO JAVIER;AND OTHERS;SIGNING DATES FROM 20141125 TO 20150204;REEL/FRAME:039606/0321 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: ADVISORY ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: ADVISORY ACTION MAILED |
|
STCV | Information on status: appeal procedure |
Free format text: NOTICE OF APPEAL FILED |
|
STCV | Information on status: appeal procedure |
Free format text: EXAMINER'S ANSWER TO APPEAL BRIEF MAILED |
|
STCV | Information on status: appeal procedure |
Free format text: ON APPEAL -- AWAITING DECISION BY THE BOARD OF APPEALS |
|
STCV | Information on status: appeal procedure |
Free format text: BOARD OF APPEALS DECISION RENDERED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION |