KR101073348B1 - Method of fabricating semiconductor thin film with a single crystal and method of fabricating a optoelectronic device using the same - Google Patents

Abstract

A method for producing a semiconductor thin film having a single crystal structure is provided. The method for manufacturing a semiconductor thin film includes forming a semiconductor nanowire on a substrate by using chemical vapor deposition at a first temperature. A semiconductor layer is formed on the nanowires by using the chemical vapor deposition method which proceeds at a second temperature lower than the first temperature. There is also provided a method of manufacturing an optoelectronic device using the same.

Metal oxide, single crystal structure

Description

Method of fabricating a semiconductor thin film having a single crystal structure and a method of manufacturing a photoelectric device using the same {Method of fabricating semiconductor thin film with a single crystal and method of fabricating a optoelectronic device using the same}

The present invention relates to a method for manufacturing a semiconductor thin film and a method for manufacturing a photovoltaic device using the same, and more particularly, to a method for manufacturing a semiconductor thin film having a single crystal structure and a method for manufacturing a photovoltaic device using the same.

The semiconductor material is a material having a constant energy band gap and is a material in which electrical characteristics and optical characteristics vary by impurity injection, light irradiation from the outside, and external thermal energy injection. Such semiconductor materials may be classified into single element semiconductors such as Si and Ge, as well as compound semiconductors such as SiC, SiGe, GaN, InAs, ZnS, and ZnO. Such a semiconductor material may be formed as a thin film on a substrate and applied to various electronic devices. For example, semiconductor thin films are used for individual circuit devices such as diodes and transistors, photoelectric devices, piezoelectric devices, pyroelectric devices, thermoelectric devices, and the like. Various properties are required for the semiconductor thin film to express excellent electrical and optical properties in the aforementioned devices. Among them, the single crystallinity and surface flatness of the semiconductor thin film may act as factors for improving various characteristics of the thin film. However, since most semiconductor thin films are formed on a substrate having a different lattice constant, it is difficult to grow into a single crystal thin film. In addition, lattice mismatch due to the difference in lattice constant, growth conditions such as temperature and supply amount during crystal growth, surface state of the substrate, and the like act as a cause of limitation in reproducing surface flatness.

Single crystallinity and surface flatness required in the formation of a semiconductor thin film are more necessary physical properties in the fabrication of an optoelectronic device. Such photovoltaic devices are manufactured by using the aforementioned compound semiconductor thin films, and recently, research into semiconductor materials emitting or detecting blue to ultraviolet rays has been actively conducted. Group III nitrides such as gallium nitride (GaN) compound semiconductors are mainly used as these materials, but zinc oxide (ZnO) compound semiconductors have been introduced as a substitute material. Zinc oxide semiconductors have been used as thin film materials for surface acoustic wave (SAW), gas detectors, piezoelectric elements and varistors, but recently they have a wide energy band gap that can emit blue to ultraviolet light and have large excitation constraints at room temperature. It has an energy (excitation binding energy) (60 meV) is attracting attention because it can emit light with higher efficiency than gallium nitride.

On the other hand, various methods have been tried to satisfy properties such as single crystallinity and surface flatness in the manufacturing process for the zinc oxide-based semiconductor thin film, and a typical process is a molecular beam epitaxy (MBE).

For example, a cell filled with solid zinc on one side is heated to vaporize a portion of the solid zinc to reach the surface of the substrate, while simultaneously reaching the substrate surface with radicalized oxygen gas on the surface of the zinc and oxygen on the substrate surface. Reaction to grow zinc oxide crystals. In this case, the crystal growth temperature is about 600 to 700 ° C. Another example is a method of growing undoped zinc oxide semiconductor crystals at very high crystal growth temperatures using a laser molecular beam epitaxy device. In this method, a zinc oxide sintered body, which is a raw material, is abraded with a KrF excimer laser and grown in crystals on a substrate heated to about 800 ° C. In the former case, the zinc oxide crystals do not sufficiently migrate to the substrate surface, so that the zinc oxide crystals are grown three-dimensionally instead of only on the horizontal plane. As a result, not only the flatness of the crystal surface is poor, but the zinc oxide crystals are not easily formed into single crystals. If the temperature is higher than the temperature mentioned in the former method, the surface flatness and single crystallinity may be improved, but the zinc and oxygen reaching the surface of the substrate are evaporated before the reaction due to the high vapor pressure of zinc and oxygen as the source. The rate of crystal growth may be lowered. On the other hand, in the latter case, due to the use of the zinc oxide sintered body, there is a problem that impurities contained in the sintered body are grown while remaining in the zinc oxide crystals.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for manufacturing a semiconductor thin film which contributes to improving surface flatness and forming a single crystal structure.

Another object of the present invention is to provide a method of manufacturing an optoelectronic device that contributes to improving surface flatness and forming a single crystal structure.

According to an aspect of the present invention for achieving the above technical problem, a method for manufacturing a semiconductor thin film is provided. The method for manufacturing a semiconductor thin film includes forming a semiconductor nanowire on a substrate by using chemical vapor deposition at a first temperature. A semiconductor layer is formed on the nanowires by using the chemical vapor deposition method which proceeds at a second temperature lower than the first temperature.

In some embodiments of the present invention, the chemical vapor deposition process proceeding to the second temperature may proceed by continuously decreasing from the first temperature to the second temperature.

In other embodiments, the semiconductor layer may be formed to have grating planes whose angle with the (0001) plane decreases toward the top surface when viewed in cross section.

In still other embodiments, the chemical vapor deposition may be performed using any one of thermal CVD, organometallic chemical vapor deposition (MOCVD), or plasma chemical vapor deposition (PECVD).

In still other embodiments, the formation of the nanowires is carried out at a pressure of less than 1 torr at a temperature of 400 to 1000 ℃ for 30 to 60 minutes, the formation of the semiconductor layer at a temperature of 200 to 300 ℃ or less for at least 10 minutes It may proceed at a pressure of less than 1 torr.

In still other embodiments, the substrate may be formed to include any one selected from the group consisting of silicon, sapphire, gallium nitride, silicon oxide, silicon nitride, zinc oxide, and ITO.

In still other embodiments, the semiconductor may be formed to include a zinc oxide based semiconductor. The zinc oxide semiconductor may be formed of a binary compound or a ternary compound further including an IIA group element or a IIB element. In addition, the zinc oxide semiconductor may be formed to be undoped. Alternatively, the zinc oxide semiconductor is formed to be doped, and the doped impurities may include gallium, nitrogen, or phosphorus (P).

In another embodiment, the zinc-containing gas in the course of the chemical vapor deposition methods are dimethylzinc [Zn (CH ₃ ) ₂ ], diethylzinc [Zn (C ₂ H ₅ ) ₂ ], zinc acetate [Zn ( OOCCH ₃ ) ₂ .H ₂ O], zinc acetate anhydride [Zn (OOCCH ₃ ) ₂ ] and zinc acetylacetonate [Zn (C ₅ H ₇ O ₂ ) ₂ ]; The oxygen-containing gas may include any one selected from the group consisting of oxygen, ozone, nitrogen dioxide, water vapor, and carbon dioxide.

According to another aspect of the present invention for achieving the above technical problem, a method of manufacturing a photoelectric device is provided. The manufacturing method of the optoelectronic device includes a zinc oxide-based semiconductor, and includes forming a semiconductor laminate including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer sequentially stacked on a substrate. The forming of the semiconductor laminate may include forming a zinc oxide-based nanowire on a substrate by using a chemical vapor deposition method at a first temperature on the substrate, and proceeding at a second temperature lower than the first temperature. Forming a zinc oxide-based semiconductor layer on the nanowires using a deposition method.

In some embodiments of the present disclosure, n-type and p-type electrodes may be formed below the n-type semiconductor layer and the p-type semiconductor layer, respectively. Before forming the n-type electrode, the substrate may be removed and a portion of the n-type semiconductor layer may be removed.

In other embodiments, the semiconductor stack may be etched to expose a portion of the n-type semiconductor layer. An n-type electrode may be formed on the exposed n-type semiconductor layer, and a p-type electrode may be formed on the p-type semiconductor layer.

According to the present invention, in forming a thin film, such as a zinc oxide-based semiconductor, on a substrate as a single crystal, a semiconductor nanowire is first formed on the substrate by chemical vapor deposition, and then the same process is performed at a lower temperature than the nanowire. A continuously grown single crystal thin film is formed. Accordingly, the nanowires grow into single crystals having a larger grain size toward the surface of the thin film due to the preferential orientation of the nanowires and horizontal growth during the low temperature process, even though the process is performed at a lower temperature than the temperature of the molecular beam epitaxy. This also contributes to improving the surface flatness of the thin film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings and the contents described below. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments disclosed herein are being provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thicknesses of the layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. Also, an element or layer is referred to as "on" or "on" of another element or layer by interposing another layer or other element in the middle as well as directly above the other element or layer. Include all cases. In addition, what is referred to as a "below" also encompasses both the case directly below another element or layer as well as intervening another layer or the like in the middle.

Hereinafter, a method of manufacturing a semiconductor thin film according to an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1D. 1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor thin film according to an exemplary embodiment of the present invention, and FIGS. 1C and 1D are enlarged views of A and B of FIG. 1B, respectively.

Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 may be formed of any one selected from, for example, silicon, sapphire, gallium nitride, silicon oxide, silicon nitride, zinc oxide, and ITO. Subsequently, ultrasonic cleaning is performed on the substrate 100, and ultrasonic cleaning may be performed by, for example, chemical cleaning with acetone and methanol, followed by cleaning with pure water. Subsequently, the substrate 100 can be dried in an oven at a predetermined temperature.

Next, the semiconductor nanowires 102 are formed on the substrate using an organic metal chemical vapor deposition (MOCVD) 10 which is performed at a first temperature. Hereinafter, a case where the semiconductor nanowires 102 are nanowires composed of a binary compound of zinc oxide will be described as an example.

Specifically, the process may proceed as follows. The cleaned substrate 100 may be loaded into a chamber (not shown) maintained at a first temperature. Temperature control in the chamber can be controlled using an induction coil, which is indirect heating. In this case, the first temperature may be 400 to 1000 ° C. as a temperature required for growth of the nanowires 102. In addition, the pressure in the chamber may be 0.0001 to 1.0 torr.

Subsequently, a precursor mixed with various gases for forming the zinc oxide nanowires 102 may be supplied to the substrate 100 through an injection member such as a shower head (not shown) in the chamber. In this case, the zinc-containing organometallic substance uses an organometallic compound containing hydrogen, and the zinc-containing gas is, for example, dimethyl zinc [Zn (CH ₃ ) ₂ ], diethyl zinc [Zn (C ₂ H _5). ) _2], zinc acetate _{[Zn (OOCCH 3) 2 ·} H 2 O], zinc acetate anhydride [Zn (OOCCH _{3) 2]} and zinc acetyl acetonate _{[Zn (C 5 H 7 O} 2) 2] one consisting of It may include any one selected from the group. In addition, the oxygen-containing gas may be any one selected from the group consisting of oxygen, ozone, nitrogen dioxide, water vapor and carbon dioxide. The supply of the gases may be carried out in simultaneous, two or a combination of the two gases depending on the process conditions, and may be carried out in various orders known to those skilled in the art. For example, the zinc containing gas may be first introduced into the chamber, and after a predetermined time, the oxygen containing gas may be introduced together with the zinc containing gas. The organometallic chemical vapor deposition process 10 of the first temperature may be performed for 30 to 90 minutes. In addition, an inert gas such as argon gas or nitrogen gas may be supplied as a carrier gas.

As a result, zinc oxide nanowires 102 may be grown and formed on the substrate 100. These nanowires 102 can be grown to have a diameter of 5 to 90 nm. Meanwhile, before the zinc oxide nanowires 102 are grown, a buffer layer (not shown) may be additionally formed to reduce lattice mismatch between the nanowires 102 and the substrate 100.

Referring to FIG. 1B, an organometallic chemical vapor deposition process 20 using the precursor described above may be performed at a second temperature lower than the first temperature. In this case, the process 20 proceeds to the conditions of the process 10 proceeded at the first temperature except for the temperature, the process 20 is less than 1torr at a temperature of 200 to 300 ℃ more than 10 minutes. May be carried out under pressure. In addition, the temperature of the process 20 may be set to start at the second temperature, or alternatively, may be set to decrease from the first temperature to the second temperature for a predetermined time during the process. This reduction can be done continuously or discontinuously with linearity.

As a result, the zinc oxide semiconductor layer 104 is continuously formed on the zinc oxide nanowires 102. Accordingly, the semiconductor thin film 110 including the zinc oxide semiconductor layer 104 and the zinc oxide nanowires 102 is formed. In this case, the semiconductor thin film 110 may remain on the substrate 100 as it is, but in another embodiment, the semiconductor thin film 110 may be separated from the substrate 100 and used as a substrate of various electronic devices.

In addition, when the process 20 proceeds to a continuous decrease in temperature, the zinc oxide semiconductor layer 104 decreases in angle with the (0001) plane toward the upper surface when viewed in the cross-sectional view as shown in FIGS. 1C and 1D. It may be formed to have a lattice plane (lattice plane). Region A of FIG. 1B is portions of the zinc oxide nanowires 102 and the zinc oxide semiconductor layer 104 adjacent thereto, and region B of FIG. 1B is the surface of the zinc oxide semiconductor layer 104 and the interior adjacent thereto. Further, the coordinate system shown in FIGS. 1C and 1D is a miller index used to indicate coordinates with respect to a wurtzite structure such as zinc oxide. Here, the coordinate (hkil) indicates a hexagonal structure lattice plane, of which h, k and l are equal to the Miller index of the cubic structure, and i is represented by -h-k.

 For example, the lattice plane shown in FIG. 1C is represented by the {10-10} lattice plane (here, representative lattice plane including the (1010) plane) with coordinates of h = 1, k = 0 and l = 0. .

Looking at the lattice planes of the zinc oxide nanowires 104 using this, the zinc oxide nanowires 102 of FIG. 1C are formed to grow in the vertical direction and have a preferred orientation in the <0001> direction, and the lattice planes of the side surfaces thereof. May be formed substantially perpendicular to the (0001) plane as the {10-10} plane. In addition, the semiconductor layer 104 adjacent to the upper portion of the zinc oxide nanowires 102 may be formed to have a {10-11} plane lattice plane therein. In this case, the {10-11} plane has an angle of about 61.61 degrees with the (0001) plane. In addition, the zinc oxide semiconductor layer 104 of FIG. 1D may grow vertically due to the preferential orientation of the zinc oxide nanowires 102. In addition, the semiconductor layer 104 of FIG. 1D may be formed to have a lattice plane of {10-12}. In this case, the {10-12} plane has an angle of about 42.5 degrees with the (0001) plane. The surface of the semiconductor layer of FIG. 1D may be formed to have a lattice plane of {0001} plane parallel to the (0001) plane. In summary, the lattice planes corresponding to the reduced temperature range are formed at different angles from the (0001) plane, and the angle decreases toward the upper surface. In view of the fact that the adsorption of zinc oxide is toward the surface energy, the growth of the thin film may progress horizontally toward the surface of the semiconductor layer 104 as the process temperature decreases. Accordingly, the semiconductor layer 104 may have a single crystal whose surface is flattened. In addition, the surface of the semiconductor layer 104 has a single crystallinity according to the preferred orientation of the zinc oxide nanowires 102. Thus, even though the process proceeds at a lower temperature than the process temperature of the molecular beam epitaxy, the semiconductor thin film 110 grown by the process can be grown to a desired thickness in a short time while having excellent surface flatness and single crystallinity. .

Meanwhile, in the present embodiment, the semiconductor thin film 110 is exemplified by a binary compound such as zinc oxide, but a zinc oxide semiconductor thin film composed of a tertiary compound additionally including an IIA element or an IIB element is also used in this embodiment. Can be prepared. Group IIA and IIB elements are used to control the energy band gap of the zinc oxide thin film. The elements may be cadmium or magnesium. In addition, various semiconductor thin films may be formed using the manufacturing method of the present embodiment. Examples of such a semiconductor may be a single element semiconductor such as Si, Ge, binary compound semiconductor, ternary compound semiconductor, and quaternary compound semiconductor. In this case, the binary compound semiconductor may be SiC, SiGe, GaN, InAs, ZnS or ZnO.

In addition, in order to control the conductivity of the zinc oxide-based thin film, in the process of supplying the precursors of the processes 10 and 20, an in-situ process is used to introduce impurities of a predetermined conductivity type. Type or N type impurities may be doped into the thin film. The P-type impurity may be phosphorus (P), nitrogen (N), or the like, and the N-type impurity may be gallium (Ga) or the like. On the other hand, when the impurities are heavily doped, the semiconductor thin film can be used as a conductive film of electronic devices such as memory devices and displays.

In addition, in the present embodiment, the organic metal chemical vapor deposition process is described as an example, but the semiconductor thin film may be formed through various chemical vapor deposition processes, for example, thermal CVD or plasma chemical vapor deposition (PECVD). have.

Hereinafter, a method of manufacturing optoelectronic devices to which a method of manufacturing a semiconductor thin film according to an exemplary embodiment of the present invention is applied will be described with reference to FIGS. 2A and 2B. 2A and 2B are cross-sectional views of optoelectronic devices according to another embodiment of the present invention, fabricated using the method according to the present embodiment. The photoelectric device referred to in the present invention may be a light emitting device such as a light emitting diode (LED), a laser diode (LD), and a light receiving device that detects a specific wavelength. In the present specification, the LED will be described as an example among various application devices in which semiconductor thin films are adopted.

Referring to FIG. 2A, a zinc oxide based semiconductor thin film is formed on the substrate 202a. The substrate 202a may be formed of a conductive substrate, and may be, for example, a substrate including silicon, zinc oxide, gallium nitride, gallium arsenide (GaAs), silicon carbide (SiC), or ITO. The zinc oxide semiconductor may be formed of a binary compound or a ternary compound further including an IIA group element or a IIB element. IIA and IIB elements are used to control energy band gap of the zinc oxide semiconductor thin film, and these elements may be cadmium or magnesium. Therefore, the zinc oxide semiconductor thin film may be formed to have a different composition ratio for each section. For example, the semiconductor layers may be formed in the same composition ratio so that the active layer interposed between the n-type and p-type semiconductor layers effectively traps the carrier therein, and the active layer is formed to have a different composition ratio from the semiconductor layers. Can be. The zinc oxide-based semiconductor thin film may be formed with a zinc oxide-based nanowire (not shown) and a zinc oxide-based semiconductor layer (not shown). Since the zinc oxide-based semiconductor thin film is formed by substantially the same method as that described in the embodiment of FIGS. 1A and 1B, a description thereof will be omitted.

Subsequently, an n-type impurity may be implanted into the zinc oxide thin conductor thin film to form an n-type semiconductor layer 204a in the semiconductor thin film adjacent to the substrate 202a. The implantation of the n-type impurity may be performed through an in situ process in the process of forming the zinc oxide-based semiconductor thin film. The n-type impurity may be gallium (Ga). Subsequently, in the process of forming the thin film, implantation of impurities may be stopped to form an undoped active layer 206. This is to avoid the formation of non-luminescent recombination centers. Next, the p-type semiconductor layer 208 may be formed on the active layer 206 by injecting p-type impurities in the process of forming the thin film. Injection of the p-type impurity may be performed through the in situ process. The p-type impurity may be phosphorus (P) or nitrogen (N). As a result, the semiconductor stack 210a including the n-type semiconductor layer 204a, the active layer 206, and the p-type semiconductor layer 208 sequentially stacked on the substrate 202a is completed.

Subsequently, p-type and n-type electrodes 212 and 214a may be formed on the p-type semiconductor layer 208 and the n-type semiconductor layer 204a, respectively. The electrodes 212 and 214a may be formed of a laminate of Ni / Al, Ni / Au, Ti / Al, or Ti / Au to form ohmic contact with the semiconductor stack 210a and the substrate 202a. have. In this embodiment, the n-type electrode 214a is formed below the substrate 202a. However, in another embodiment, the substrate 202a may be laser lifted off or chemical mechanical polishing (CMP). Can be removed. In addition, the zinc oxide nanowires that are part of the n-type semiconductor layer 204a can be removed. Thereafter, an n-type electrode may be formed under the n-type semiconductor layer 204a.

As a result, the LED 200 including the semiconductor stack 210a and the p-type and n-type electrodes 212 and 214a is completed. The LED manufactured according to the present embodiment has excellent light emission efficiency by providing a semiconductor laminate 210a having good surface flatness and single crystallinity.

Since the embodiment of FIG. 2B is substantially the same as the embodiment of FIG. 2A except for the material of the substrate 202b and the arrangement of the n-type electrode 214b, only the differences will be described. The substrate 202b may be a sapphire substrate as a nonconductive substrate. After the semiconductor stack 210b is formed on the substrate 202b, the semiconductor stack 210b may be etched to expose a portion of the n-type semiconductor layer 202b. Subsequently, the n-type electrode 214b may be formed on the exposed n-type semiconductor layer 204b, and the p-type electrode 212 may be formed on the p-type semiconductor layer 208.

Hereinafter, the present invention will be described in more detail with reference to experimental and comparative examples. However, the following experimental examples are for illustrating the present invention, it should be understood that the present invention is not limited by the following experimental examples.

Experimental Examples

3A and 3B are cross-sectional photographs and planar photographs of a thin film formed by setting a thin film growth time to a short time when performing the manufacturing method according to the present embodiment, and FIGS. 3C and 3D illustrate the manufacturing method according to the present embodiment. FIG. 3E is a planar photograph and a cross-sectional photograph of a thin film formed by setting the thin film growth time to a long time, and FIG. 3E is a cross-sectional photograph of the region shown in FIG. 3D. 3 are scanning electron microscope (SEM) images.

In the experimental examples, the semiconductor thin film of the present embodiment was manufactured as follows. The semiconductor thin film fabricated in the present experimental examples was formed using an organometallic chemical vapor deposition process as a binary compound semiconductor composed of zinc oxide. Specifically, ultrasonic cleaning was performed on the sapphire substrate (Al ₂ O ₃ ) in the order of acetone, methanol and pure water for 5 minutes, followed by drying for 10 minutes in an oven at a temperature of about 80 ° C. Subsequently, the substrate was placed in the chamber to maintain the temperature of the chamber at 400 ° C. required for nanowire growth using an induction coil, an indirect heating method, and the pressure in the chamber was maintained at 0.001 torr. Next, dimethylzinc [Zn (CH ₃ ) ₂ ], which is a zinc-containing gas, was supplied into the chamber for an initial 30 seconds, followed by an oxygen gas having a concentration of 6N. At the same time, 6N argon gas was used as the carrier gas in the chamber. That is, an organic metal chemical vapor deposition process was performed at a temperature of 400 ° C. to grow a buffer layer and zinc oxide nanowires sequentially stacked on the sapphire substrate. Thereafter, while continuously maintaining the supply of zinc-containing gas and oxygen gas, the temperature was continuously decreased to 300 ° C to form a zinc oxide semiconductor layer on the zinc oxide nanowire continuously.

3A and 3B illustrate examples in which a zinc oxide semiconductor layer is grown for 20 minutes after growth of zinc oxide nanowires, and FIGS. 3C to 3E illustrate examples in which a zinc oxide semiconductor layer is grown for 3 hours after growth of zinc oxide nanowires. admit. As can be seen in FIGS. 3A and 3B, the semiconductor layer grown on the zinc oxide nanowires is formed with a flat surface, and the hexagonal shape sheets of the single crystal urethane are formed on the surface. It can be observed to have. However, it is shown in Figure 3b that the slope of the hexagonal shape of the plane is different. This is due to the surface of the zinc oxide semiconductor thin film not reaching a perfect match. In FIGS. 3C and 3D, unlike the embodiment of FIG. 3A, hexagonal planes of several μm in size are clearly visible on the surface of the semiconductor layer, and the slopes thereof are exactly coincident. Although the semiconductor layer was grown at a low temperature of 400 ° C., it can be seen that the growth is almost matched with the growth for a long time. As shown in FIG. 3E, the region A is a section in which zinc oxide nanowires are grown, and the region B is a section in which grain size does not change while forming two-dimensional growth in one dimension. Finally, area C is a section in which grain size increases rapidly as two-dimensional growth occurs.

4A to 4D are region-specific transmission electron microscope (TEM) images and corresponding diffraction patterns shown in FIG. 3E, and FIGS. 4E to 4G are enlarged TEM images of the region shown in FIG. 4A, and FIG. 4H. Is an enlarged TEM photograph of the area shown in FIG. 4C.

As can be seen in the TEM photographs of FIGS. 4A to 4D, it can be seen that the growth direction is changed from vertical to horizontal. In addition, as shown in the diffraction patterns of FIGS. 4A to 4D, the grain size increases with the growth time. Meanwhile, in FIG. 4E, it can be seen that the boundary of the grown grain is divided into a horizontal boundary with respect to the (0001) plane and a boundary inclined at a predetermined angle. In this case, the horizontal boundary is the {0001} plane, and the inclined plane is the (0001) plane and the {10-12} plane that is inclined 42.5 degrees. In particular, FIG. 4F shows a boundary where two large grains merge into one grain. On the other hand, as can be seen in Figure 4h, in the semiconductor layer adjacent to the zinc oxide nanowires, the {10-11} plane with a large degree of inclination with respect to the (0001) plane is dominant, and as the grain increases, the {10- 12} there are many planes. It can be seen that the boundary is shifted in the direction of increasing the horizontal growth compared to the vertical growth.

Figure 5a is a graph showing the lattice constant and stress change of the thin film according to the growth temperature in the manufacturing method according to the present embodiment, Figure 5b is a graph showing the change of the lattice constant and stress according to the regions shown in Figure 3e. The horizontal axis of FIG. 5A is the growth temperature of the semiconductor layer, and the left and right vertical axes of FIG. 5A are a lattice constant and a stress, respectively. In addition, the left and right vertical axes of FIG. 5B are a lattice constant and a stress, respectively.

 As can be seen in FIG. 5A, the lattice constant of the zinc oxide semiconductor thin film according to the change of the growth temperature is almost constant, whereas the stress is subjected to tensile stress as the growth temperature is lowered and the growth temperature is increased. Therefore, it appears to be subjected to a weak compressive stress. This is because the nanostructure changes as the temperature increases. In FIG. 5B, the region A, which is a zinc oxide nanowire, is subjected to a weak compressive stress as shown in FIG. 5A, and the growth temperature decreases to change into tensile stress as it grows into a thin film. Also, it can be seen that the area C where the grain size increases is grown under relatively excessive tensile stress.

6 is a view for explaining the mechanism of thin film growth using the manufacturing method according to the present embodiment. FIG. 6 shows the growth stages of the zinc oxide thin film thinly divided into four regions and a lattice plane of the surface thereof. The four regions of FIG. 6 correspond to the regions shown in FIG. 3E, respectively.

In region A, it is grown with a lattice plane of {0110} and grows in a 90 degree azimuth with (0001) plane. The regions B and C are grown with {0111}, {0112}, and {0001} planes, respectively, and these planes are grown with (0001) planes with 61.61, 42.47, and 0 degrees, respectively. This shows that not only the lattice plane formed as the growth temperature decreases, but also the angle between the lattice plane and the (0001) plane decreases. Meanwhile, in FIG. 6, broken bonds exposed on the surface of each lattice are indicated by yellow circles. It can be seen that as the growth temperature decreases, the number of broken bonds changes in the order of 2, 3, 5, and 0 based on one period. Through this change in the number of broken bonds, the zinc oxide semiconductor layer grows with excellent preferential orientation of the nanowires, and at the same time, the grain is continuously increased as the growth time is formed by the boundary of {0112} which leads to horizontal growth at the top of the semiconductor layer. It can be seen that. In addition, the surface of the semiconductor layer has a hexagonal-shaped single crystal seen in the Urtzite structure, as well as the {0001} surface having the lowest surface energy.

7 is a graph showing the transmittance of the thin film produced according to the manufacturing method according to the present embodiment. The transmittance was tested using zinc oxide thin films prepared by the method described in the experimental example of FIGS. 3A to 3E. In this experiment, the transmittance was measured by irradiating light of predetermined wavelength to two specimens and the transmittance according to the change of wavelength. As a result, both specimens showed more than 85% transmittance at about 600nm wavelength. Moreover, the thin film grown for 3 hours showed high transmittance despite being thicker than the thin film grown for 20 minutes.

Although the present invention has been described in detail through the representative embodiments, those skilled in the art to which the present invention pertains can make various modifications without departing from the scope of the present invention. Will understand. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims below and equivalents thereof.

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor thin film according to an exemplary embodiment of the present invention.

1C and 1D are enlarged views of A and B of FIG. 1B, respectively.

2A and 2B are cross-sectional views of optoelectronic devices according to another embodiment of the present invention, fabricated using the method according to the present embodiment.

3A and 3B are cross-sectional photographs and planar photographs of a thin film formed by setting a thin film growth time to a short time when performing the manufacturing method according to the present embodiment, and FIGS. 3C and 3D illustrate the manufacturing method according to the present embodiment. FIG. 3E is a planar photograph and a cross-sectional photograph of a thin film formed by setting the thin film growth time to a long time, and FIG. 3E is a cross-sectional photograph of the region shown in FIG. 3D.

4A to 4D are region-specific transmission electron microscope (TEM) images and corresponding diffraction patterns shown in FIG. 3E, and FIGS. 4E to 4G are enlarged TEM images of the region shown in FIG. 4A, and FIG. 4H. Is an enlarged TEM photograph of the area shown in FIG. 4C.

Figure 5a is a graph showing the lattice constant and stress change of the thin film according to the growth temperature in the manufacturing method according to the present embodiment, Figure 5b is a graph showing the change of the lattice constant and stress according to the regions shown in Figure 3e.

6 is a view for explaining the mechanism of thin film growth using the manufacturing method according to the present embodiment.

7 is a graph showing the transmittance of the thin film produced according to the manufacturing method according to the present embodiment.

Claims (23)

Forming a semiconductor nanowire on a substrate by using chemical vapor deposition proceeding at a first temperature, A semiconductor layer is formed on the nanowires by using the chemical vapor deposition method which proceeds at a second temperature lower than the first temperature. And the semiconductor layer is formed to have lattice planes whose angle with the (0001) plane decreases toward the upper surface when viewed in cross section. The method of claim 1, The chemical vapor deposition process proceeds to the second temperature is a method of manufacturing a semiconductor thin film is carried out by continuously decreasing from the first temperature to the second temperature. delete The method of claim 1, The chemical vapor deposition methods are performed using any one of thermal chemical vapor deposition (thermal CVD), organometallic chemical vapor deposition (MOCVD) or plasma chemical vapor deposition (PECVD) method. The method of claim 1, The formation of the nanowires is performed at a pressure of less than 1 torr at a temperature of 400 to 1000 ° C. for a time of 30 to 60 minutes, and the formation of the semiconductor layer is at a pressure of less than 1 tor at a temperature of 200 to 300 ° C. or more for 10 minutes or more. Method for producing a semiconductor thin film that is in progress. The method of claim 1, And the substrate is formed to include any one selected from the group consisting of silicon, sapphire, gallium nitride, silicon oxide, silicon nitride, zinc oxide, and ITO. The method of claim 1, The semiconductor is a method of manufacturing a semiconductor thin film formed to include a zinc oxide semiconductor. The method of claim 7, wherein The zinc oxide based semiconductor is a method of manufacturing a semiconductor thin film formed to be undoped (undoped). The method of claim 7, wherein The zinc oxide-based semiconductor is formed to be doped, wherein the doped impurities include gallium, nitrogen or phosphorus (P). The method of claim 7, wherein The zinc oxide semiconductor is a semiconductor thin film is formed of a binary compound or a ternary compound further comprising a group IIA element or group IIB element of the semiconductor thin film manufacturing method. The method of claim 7, wherein Zinc-containing gas in the process of progress of the chemical vapor deposition is dimethyl zinc _{[Zn (CH 3) 2]} , diethylzinc _{[Zn (C 2 H 5)} 2], zinc acetate _{[Zn (OOCCH 3) 2 ·} H 2 O], zinc acetate anhydride [Zn (OOCCH ₃ ) ₂ ] and zinc acetylacetonate [Zn (C ₅ H ₇ O ₂ ) ₂ ] and any one selected from the group consisting of oxygen, gas containing oxygen, ozone , Nitrogen dioxide, water vapor, and a method for producing a semiconductor thin film comprising any one selected from the group consisting of carbon dioxide. A semiconductor laminate including a zinc oxide semiconductor and having an n-type semiconductor layer, an active layer and a p-type semiconductor layer sequentially stacked on a substrate is formed, The forming of the semiconductor laminate may include forming a zinc oxide-based nanowire on a substrate by using a chemical vapor deposition method at a first temperature on the substrate, and proceeding at a second temperature lower than the first temperature. Forming a zinc oxide based semiconductor layer on the nanowires by using a deposition method, And the zinc oxide semiconductor layer is formed to have lattice planes whose angle with the (0001) plane decreases toward the upper surface when viewed in cross section. 13. The method of claim 12, The chemical vapor deposition process proceeds to the second temperature is a method of manufacturing a photovoltaic device is carried out by continuously decreasing from the first temperature to the second temperature. delete 13. The method of claim 12, The chemical vapor deposition methods are performed using any one of thermal CVD, organometallic chemical vapor deposition (MOCVD) or plasma chemical vapor deposition (PECVD). 13. The method of claim 12, Zinc-containing gas in the process of progress of the chemical vapor deposition is dimethyl zinc _{[Zn (CH 3) 2]} , diethylzinc _{[Zn (C 2 H 5)} 2], zinc acetate _{[Zn (OOCCH 3) 2 ·} H 2 O], zinc acetate anhydride [Zn (OOCCH ₃ ) ₂ ] and zinc acetylacetonate [Zn (C ₅ H ₇ O ₂ ) ₂ ] and any one selected from the group consisting of oxygen, gas containing oxygen, ozone , Nitrogen dioxide, water vapor and carbon dioxide manufacturing method of a photonic device comprising any one selected from the group consisting of. 13. The method of claim 12, Formation of the zinc oxide nanowires is carried out at a pressure of less than 1 torr at a temperature of 400 to 1000 ℃ for a time of 30 to 60 minutes, Forming the zinc oxide-based semiconductor layer is a method of manufacturing a photoelectric device at a pressure of less than 1 torr at a temperature of 200 to 300 ℃ less than 10 minutes. 13. The method of claim 12, And the substrate is formed to include any one selected from the group consisting of silicon, sapphire, gallium nitride, silicon oxide, silicon nitride, zinc oxide, and ITO. 13. The method of claim 12, Wherein the n-type semiconductor layer is formed to be doped with gallium, the p-type semiconductor layer is formed to be doped with nitrogen or phosphorus (P), and the active layer is formed to be undoped. 13. The method of claim 12, The semiconductor stacking portion is formed of a binary compound or a method of manufacturing a photoelectric device formed of a ternary compound further comprising a group IIA element or group IIB element. 13. The method of claim 12, And forming n-type and p-type electrodes under the n-type semiconductor layer and the p-type semiconductor layer, respectively. The method of claim 21, Before forming the n-type electrode, Remove the substrate, And removing a portion of the n-type semiconductor layer. 13. The method of claim 12, Etching the semiconductor laminate to expose a portion of the n-type semiconductor layer, Forming an n-type electrode on the exposed n-type semiconductor layer, And forming a p-type electrode on the p-type semiconductor layer.

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