In the description of the embodiments, each layer, region, pattern, or structure is formed “on” or “under” of a substrate, each layer (film), region, pad, or pattern. In the case described as "on" and "under" includes both "directly" or "indirectly" formed. In addition, the criteria for the top or bottom of each layer will be described with reference to the drawings.
In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.
Hereinafter, a light emitting device and a method of manufacturing the same according to embodiments will be described with reference to the accompanying drawings.
<First Embodiment>
1 is a cross-sectional view of a light emitting device 100 according to a first embodiment.
Referring to FIG. 1, the light emitting device 100 includes a substrate 101 and a chip structure 103. The light emitting device 100 may have the same size as that of the substrate 101 and the chip structure 103, that is, the diameter of the substrate 101 and the diameter of the chip structure 103 are the same.
The substrate 101 may include an insulating substrate, a conductive substrate, or a flexible substrate. The substrate 101 may be a Si substrate, an AlN substrate, a metal core PCB (Metal Core PCB), a single layer or a multilayer low temperature co-fired ceramic (LTCC) substrate, a single layer or a multilayer high temperature co-fired ceramic (HTCC), General PCB can be used selectively.
The substrate 101 includes a body 110 and has a via structure including a plurality of via holes 113A. However, this is not limitative.
First insulating layers 111, 113, and 115 may be formed on the surface of the substrate 101 and the via hole 113A. An upper insulating layer 111 is formed on an upper surface of the first insulating layers 111, 113, and 115, a via insulating layer 113 is formed in a plurality of via holes 113A of the substrate 101, and a lower surface of the substrate is formed. In this case, the insulating layer 115 may be formed. The first insulating layers 111, 113, and 115 may not be formed when the body 110 of the substrate 101 is a non-conductive material.
First and second lead patterns 122 and 112 are formed on an upper surface of the substrate 101. The first and second lead patterns 122 and 112 are spaced apart from each other by the filling member 140 to be electrically insulated from each other. The first and second lead patterns 122 and 112 may be formed in various sizes and shapes according to a predetermined circuit design pattern, but are not limited thereto.
Upper surfaces of the first lead pattern 122 and the second lead patterns 122 and 112 may be formed on the same plane. Accordingly, the chip structure 103 may be bonded to the substrate 101 without being inclined.
FIG. 2 is a cross-sectional view taken along line AA ′ of the light emitting device 100 of FIG. 1.
Referring to FIG. 2, the filling member 140 is formed on at least one side of the first and second lead patterns 122 and 112 on the substrate 101, and the first and second lead patterns 122 and 112 are formed. Can be formed in all areas except.
The first and second lead patterns 122 and 112 are respectively illustrated in a rectangular shape, but are not limited thereto.
The filling member 140 may transfer heat generated from the chip structure 103 to the substrate 101 or discharge itself, thereby improving heat dissipation characteristics of the light emitting device 100.
In addition, the filling member 140 may prevent moisture or the like from penetrating into the light emitting device 100.
The filling member 140 may be formed of a material having heat transfer characteristics while functioning as an insulator, and for example, flux, a thermoplastic resin, an anisotropic conductive adhesive, and the like may be used.
The flux may be any one of chloride, fluoride, and resin, but is not limited thereto. The flux may insulate between the first and second lead patterns 122 and 112 and transmit heat generated from the chip structure 103 to the substrate 101. In addition, the flux may serve to dissolve and remove oxides on the metal surface, thereby preventing the first and second lead patterns 122 and 112 from being oxidized. The flux may be coated on the substrate 101 or coated in a spray form before the substrate 101 and the chip structure 103 are bonded to each other.
The thermoplastic resin may include, for example, polyethylene, nylon, polyacetyl resin, vinyl chloride resin, ABS resin, acrylic resin, and the like, but is not limited thereto. The thermoplastic resin may be prepared in a semi-cured or gel state and disposed on the substrate 101, and then may be cured after bonding the substrate 101 and the chip structure 103.
The anisotropic conductive adhesive is an adhesive having conductivity only in the z-axis direction and is a kind of thermoplastic adhesive. High resistance in the x- and y-axis directions prevents current from flowing. The anisotropic conductive adhesive may be prepared in the form of a film or a paste, and may be applied to insulate the first and second lead patterns 122 and 112 between the first and second lead patterns 122 and 112. In addition, the anisotropic conductive adhesive may be prepared in a semi-cured state or a paste state and may be cured after bonding the substrate 101 and the chip structure 103.
On the other hand, the filling member 140 is not limited to being formed of the flux, thermoplastic resin, anisotropic conductive adhesive, it can be formed in various modifications within the range that can be easily implemented by those skilled in the art.
The via insulation layer 113 is formed in the via hole 113A, and the via electrodes 114 and 124 are formed in the via insulation layer 113. The first via electrode 124 is branched from the first lead pattern 122, and the second via electrode 114 is formed to branch from the second lead pattern 112.
External electrodes 116 and 126 are formed on the bottom surface of the substrate 101, and the first external electrode 126 and the second external electrode 116 are spaced apart from each other by the open part 121B. The external electrodes 116 and 126 may be formed in various sizes and shapes according to the pattern of the preset circuit design, but are not limited thereto.
The first via electrode 124 connects the first lead pattern 122 and the first external electrode 126 to each other, and the second via electrode 114 is connected to the second lead pattern 112. The second external electrode 116 is connected to each other.
A dicing groove 150 may be formed on the outer lower periphery of the substrate 101, that is, in the process of separating the light emitting device 100 into chips by notch etching. The groove 150 may be formed by etching the lower surface insulating layer 115 and a part of the body 110.
In this case, when the substrate 101 is a conductive substrate, the external electrodes 116 and 126 may be spaced apart from the bottom edge of the substrate 101, that is, the chip boundary or / and the dicing groove 150 from 200 μm to 500 μm. It may be formed to have one distance (T). This is to ensure reliability in the Surface Mount Technology (SMT) process of mounting the light emitting device 100 to the light emitting module.
In detail, the light emitting device 100 emits light between the external electrodes 116 and 126 and the light emitting module by soldering using, for example, solder bumps, stud bumps, and solder bumps. Can be mounted to the module. When soldering is performed, solder may flow along the lower surface insulating layer 115 to the side surface of the substrate 101 to contact the body 110 of the substrate 101. Thus, the body 110 and the external electrodes 116 and 126 may be electrically shorted with each other to reduce the reliability of the light emitting device 100. Accordingly, the reliability of the light emitting device 100 may be secured by separating the external electrodes 116 and 126 from an outer lower circumference of the substrate 101, that is, 200 μm to 500 μm from the chip boundary or the dicing groove 150. have.
The chip structure 103 may include a plurality of compound semiconductor layers including group 2 to group 6 compound semiconductors. For example, the chip structure 103 may be implemented as an LED chip using a group 3 to group 5 compound semiconductor. The LED chip may be a colored LED chip that emits light such as blue, green, or red, or may be a UV LED chip. The semiconductor material of the LED chip and its emission light may be variously implemented within the technical scope of the embodiment.
The chip structure 103 includes a first conductive semiconductor layer 131, an active layer 132, a second conductive semiconductor layer 133, a first pad 135, and a second pad 136.
A buffer layer or an undoped semiconductor layer may be further disposed on the upper surface of the chip structure 103.
The first conductive semiconductor layer 131 is a compound semiconductor of a Group III-V group element doped with a first conductive dopant, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and the like can be selected.
When the first conductive semiconductor layer 131 is an N-type semiconductor layer, the first conductive dopant includes an N-type dopant such as Si, Ge, Sn, Se, Te, or the like. The first conductive semiconductor layer 131 may function as an electrode contact layer, and may be formed as a single layer or a multilayer, but is not limited thereto.
An active layer 132 is formed under the first conductive semiconductor layer 131, and the active layer 132 may have a single quantum well structure, a multi-quantum well structure, a quantum line structure, or a quantum dot structure. In the case of the quantum well structure, the active layer 132 may be formed by using a compound semiconductor material of Group III-Group 5 elements in a cycle of a well layer and a barrier layer, for example, a cycle of an InGaN well layer / GaN barrier layer. .
A roughness pattern may be formed on an upper surface of the first conductive semiconductor layer 131, and the roughness pattern may improve external quantum efficiency.
The active layer 132 may be selected as a material having a band gap energy according to the wavelength of light to emit light. The active layer 132 may include a material that emits colored light such as light of blue wavelength, light of red wavelength, and light of green wavelength, but is not limited thereto. A conductive cladding layer may be formed on or under the active layer 132, and the conductive cladding layer may be formed of an AlGaN layer.
A second conductive semiconductor layer 133 is formed under the active layer 132. The second conductive semiconductor layer 133 may be a compound semiconductor of a Group III-5 element doped with a second conductive dopant, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaAsP and the like can be selected. When the second conductive semiconductor layer 133 is a P-type semiconductor layer, the second conductive dopant includes a P-type dopant such as Mg and Zn. The second conductive semiconductor layer 133 may function as an electrode contact layer, and may be formed as a single layer or a multilayer, but is not limited thereto.
The first conductive semiconductor layer 131, the active layer 132, and the second conductive semiconductor layer 133 may be defined as light emitting structures. In addition, the first conductive semiconductor layer 131 may be a P-type semiconductor, and the second conductive semiconductor layer 133 may be formed of an N-type semiconductor. A third conductive semiconductor layer, for example, an N-type semiconductor layer or a P-type semiconductor layer may be formed under the second conductive semiconductor layer 133. Accordingly, the light emitting structure may include at least one of an N-P junction, a P-N junction, an N-P-N junction, and a P-N-P junction structure.
A first pad 135 may be formed under the first conductive semiconductor layer 131. The first pad 135 may be formed in a pattern such as a circle shape, a polygon shape, a ring shape, a branched or bent shape, a multi-window shape, and the like. The first pad 135 may be formed in single or plural in the chip structure 103, and the position, formation, and number of the first pad 135 may be changed within the technical scope of the embodiment. The pattern shape of the first pad 135 may be formed in consideration of the emission area of the active layer 132.
A second pad 136 is formed under the second conductive semiconductor layer 133. The second pad 136 may be formed on the entire bottom surface of the second conductive semiconductor layer 133.
That is, the first pad 135 may be formed on one side of the compound semiconductor layer, and the second pad 136 may be formed on the other side of the compound semiconductor layer.
The first pad 135 or / and the second pad 136 may be formed of at least one or a plurality of alloy materials among Ag, Rh, Ni, Au, Pd, Ir, Ti, Pt, W, Al, and the like. have.
An ohmic contact layer may be formed in a pattern or a layer shape between the second pad 136 and the second conductive semiconductor layer 133. The ohmic contact layer may be Ni, Pt, Ir, Rh, Ag, indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZO), or indium gallium zinc (IGZO). oxide), indium gallium tin oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IrOx, RuOx, RuOx / ITO, Ni / IrOx / Au, and Ni / IrOx It may include at least one of / Au / ITO.
A second insulating layer 137 may be formed around the outer circumference of the chip structure 103. The second insulating layer 137 may be formed on the entire surface of the chip structure 103 except for a portion of the second pad 136 and the first pad 135. That is, the second insulating layer 137 may be formed on the filling member 140.
The second insulating layer 137 is formed around the first pad 135 to prevent a short problem with other layers 132, 133, and 136. The second insulating layer 137 may be formed of an insulating material. For example, SiO 2 , SiO x , SiO x N y , Si 3 N 4 , Al 2 O 3 , TiO 2 And the like.
The first pad 135 and the second pad 136 may be formed on the same plane. The first pad 135 may be formed relatively thick so that the first pad 135 is coplanar with the second pad 136, or a thickened bonding material is formed on the bottom surface of the first pad 135 to form the second pad 136. ) Can eliminate the height difference.
The chip structure 103 is bonded onto the substrate 101. The first pad 135 of the chip structure 103 is bonded to the first lead pattern 122 of the substrate 101, and the second pad 136 is formed on the second lead pattern of the substrate 101. 112). Since the two pads 135 and 136 of the chip structure 103 are directly bonded to the lead patterns 122 and 112 on the substrate 101, heat dissipation characteristics of the light emitting device 100 may be improved.
In addition, since the filling member 140 has adhesiveness, the bonding of the substrate 101 and the chip structure 103 may be firmly performed, and heat generated from the chip structure 103 may be transferred to the substrate 101. The heat radiation characteristics of the light emitting device 100 may be improved by transmitting to or emitting itself.
3 to 6 are views illustrating a method of manufacturing the light emitting device 100 according to the first embodiment, and FIG. 7 is a flowchart illustrating a method of manufacturing the light emitting device 100.
3 and 4, a compound semiconductor layer of Groups 2 to 6 is formed on the growth substrate 130 (S101 of FIG. 7).
The growth substrate 130 may be selected from the group consisting of sapphire substrate (Al 2 O 3 ), GaN, SiC, ZnO, Si, GaP, InP, and GaAs, Ga 2 O 3 .
The compound semiconductor layer of Groups 2 to 6 is electron beam deposition (E-beam deposition), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal deposition (dual-type thermal) It may be formed by a method such as evaporation (sputtering), metal organic chemical vapor deposition (MOCVD), but is not limited thereto.
The group 2 to 6 compound semiconductor layer includes a first conductive semiconductor layer 131, an active layer 132, and a second conductive semiconductor layer 133, and is below the first conductive semiconductor layer 131. The buffer layer may further include a buffer layer (not shown) and / or a nonconductive semiconductor layer (not shown).
The first conductive semiconductor layer 131 is formed on the growth substrate 130, and the first conductive semiconductor layer 131 is a compound semiconductor of a Group 3-5 element doped with a first conductive dopant. , GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and the like.
When the first conductive semiconductor layer 131 is an N-type semiconductor layer, the first conductive dopant may include an N-type dopant such as Si, Ge, Sn, Se, Te, and the like, and may be formed as a single layer or a multilayer. have.
An active layer 132 is formed on the first conductive semiconductor layer 131, and the active layer 132 may have a single quantum well structure, a multi-quantum well structure, a quantum line structure, or a quantum dot structure. In the case of the quantum well structure, the active layer 132 may be formed by using a compound semiconductor material of Group III-Group 5 elements in a cycle of a well layer and a barrier layer, for example, a cycle of an InGaN well layer / GaN barrier layer. .
A conductive cladding layer may be formed on or under the active layer 132, and the conductive cladding layer may be formed of an AlGaN layer.
The second conductive semiconductor layer 133 is formed on the active layer 132. The second conductive semiconductor layer 133 is a compound semiconductor of a Group III-V group element doped with a second conductive dopant, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaAsP and the like can be selected. When the second conductive semiconductor layer 133 is a P-type semiconductor layer, the second conductive dopant includes a P-type dopant such as Mg and Zn.
Here, the first conductive semiconductor layer 131, the active layer 132, and the second conductive semiconductor layer 133 may be defined as a minimum light emitting structure. In addition, the first conductive semiconductor layer 131 may be a P-type semiconductor, and the second conductive semiconductor layer 133 may be formed of an N-type semiconductor. A third conductive semiconductor layer, for example, an N-type semiconductor layer or a P-type semiconductor layer may be formed under the second conductive semiconductor layer 133. Accordingly, the light emitting structure may include at least one of an N-P junction, a P-N junction, an N-P-N junction, and a P-N-P junction structure.
After growing the Group 2 to Group 6 compound semiconductor layer on the growth substrate 130, mesa etching is performed on the Group 2 to Group 6 compound semiconductor layer to form an etching groove 141 (S103 in FIG. 7). ).
The etching groove 141 may be formed in a shape corresponding to the first pad formation region, and the depth of the etching groove 141 may be formed to expose the first conductive semiconductor layer 131. The etching groove 141 may be formed by etching around individual chips for light emitting area or electrical reliability, but is not limited thereto.
After the mesa etching, an insulating layer forming step and an electrode forming step (S105 and S107 in FIG. 7) are performed.
The insulating layer forming process is performed to form a second insulating layer 137. The second insulating layer 137 may be formed in the etching groove 141 of FIG. 4, and may be formed to the thickness of the first pad 135. The second insulating layer 137 is formed around the first pad 135, and the first pad 135, the second conductive semiconductor layer 133, the active layer 132, and the first pad 135 are formed around the first pad 135. It blocks the electrical contact with the two pads (136).
After the second insulating layer 137 is formed, the pads 135 and 136 are formed through the electrode forming process. In the electrode forming process, a first pad 135 is formed on the first conductive semiconductor layer 131 through the etching groove 141, and a second pad (on the second conductive semiconductor layer 133) is formed. 136 is formed.
The first pad 135 may be changed according to the shape of the etching groove 141, and may be spaced apart from the active layer 132 and the second conductive semiconductor layer 133. The second pad 136 may be formed on the entire surface of the second conductive semiconductor layer 133 except for the etching groove 141 or may be formed on a portion of the surface thereof.
Meanwhile, since the pads 135 and 136 may be formed first and then the second insulating layer 137 may be formed, the relationship between the electrode forming process and the insulating layer forming process may be changed, but is not limited thereto.
In this way, the chip structure 103 can be provided.
5 and 6, the chip structure 103 may be inverted 180 degrees, corresponded to the substrate 101 prepared in advance, and then bonded as shown in FIG. 6.
The substrate 101 may include an insulating substrate, a flexible substrate, or a conductive substrate. The substrate 101 may be a Si substrate, an AlN substrate, a metal core PCB (MCPCB), a single layer or a multilayer low temperature co-fired ceramic (LTCC) substrate, a single layer or a multilayer high temperature co-fired ceramic (HTCC), or a general PCB. Etc. can be used selectively.
The substrate 101 forms the via hole 113A by forming the via hole 113A (S121), and forms a dicing groove 150 by etching a chip boundary region to distinguish individual chips. 7 (S123 of FIG. 7), the first insulating layers 111, 113, and 115 are formed (S124 of FIG. 7), and the via electrodes 114 and 124 are formed by filling a conductive material in the via hole 113A (FIG. 7). S125 and through the wiring process, the lead patterns 122 and 112 and the external electrodes 126 and 116 are formed (S127 of FIG. 7), and the filling member 140 is formed on the substrate 101 (FIG. 7). S128).
In detail, the first insulating layers 111, 113, and 115 are formed on the top, bottom, and via holes 113A of the substrate 101. The first insulating layers 111, 113, and 115 are formed of an upper insulating layer 111 formed on an upper surface of the substrate 101, a via insulating layer 113 formed in a via hole 113A of the substrate 101, and a lower surface of the substrate 101. It includes a lower insulating layer 115 formed on.
The first insulating layers 111, 113, and 115 may be formed of an insulating material. For example, SiO 2 , SiO x , SiO x N y , Si 3 N 4 , Al 2 O 3 , TiO 2 It may optionally be formed in the back, but is not limited thereto.
The first and second lead patterns 122 and 112 are formed on an upper surface of the substrate 101. The first and second lead patterns 122 and 112 are spaced apart from each other by the open part 121A. The first and second lead patterns 122 and 112 may be formed in various sizes and shapes according to a wiring pattern of a predetermined circuit design.
The via electrodes 114 and 124 are insulated from the via hole 113A of the substrate 101 by the via insulating layer 113.
First and second external electrodes 126 and 116 are formed on the bottom surface of the substrate 101 and spaced apart from each other by the open part 121B, and the first and second external electrodes 126 and 116 have a predetermined circuit design pattern. It can be formed in various ways.
The first via electrode 124 connects the first lead pattern 122 and the first external electrode 126 to each other, and the second via electrode 114 is connected to the second lead pattern 112. The second external electrode 116 is connected to each other.
A dicing groove 150 corresponding to an individual chip spacing D1 is formed below the substrate 101, and the dicing groove 150 is a chip boundary region, and a notch etch is performed on the substrate 101. by etching). The notch etching process may be performed before forming the insulating layer, but is not limited thereto.
The dicing groove 150 may proceed through wet etching or / and dry etching after mask patterning using a mask layer. The wet etching is performed using a KOH or HNA solution (fluoric acid, nitric acid, acetic acid mixture) for the region where the mask layer is not formed, and the dry etching is performed to perform etching using SF 6 or XeF 2- based reaction gas. do.
The external electrodes 116 and 126 may be formed to have a first distance T spaced apart from the chip boundary or the dicing groove 150 and 200 μm to 500 μm from the lower periphery of the substrate 101. Can be. This is to ensure reliability in the Surface Mount Technology (SMT) process of mounting the light emitting device 100 to the light emitting module.
In detail, the light emitting device 100 emits light between the external electrodes 116 and 126 and the light emitting module by soldering using, for example, solder bumps, stud bumps, and solder bumps. Can be mounted to the module. When soldering is performed, solder may flow along the lower surface insulating layer 115 to the side surface of the substrate 101 to contact the body 110 of the substrate 101. Thus, when the body 110 is conductive, the body 110 and the external electrodes 116 and 126 may be electrically shorted with each other to reduce the reliability of the light emitting device 100. Accordingly, the light emitting device is spaced apart from the outer electrode 116 and 126 at the outer circumference of the substrate 101, that is, at a first distance T from the chip boundary or the dicing groove 150, that is, 200 μm to 500 μm. The reliability of 100 can be secured.
The filling member 140 may be prepared and formed in a region including the open part 121A between at least the first and second lead patterns 122 and 112 on the substrate 101. After the substrate 101 and the chip structure 103 are bonded to each other, the filling member 140 remains in at least one side of the first and second lead patterns 122 and 112 or in an area except for the first and second lead patterns. can do.
Thus, the first and second lead patterns 122 and 112 are spaced apart from each other by the filling member 140 to be electrically insulated.
In addition, the filling member 140 may transfer heat generated from the chip structure 103 to the substrate 101 or release itself, thereby improving heat dissipation characteristics of the light emitting device 100. In addition, the filling member 140 may prevent moisture or the like from penetrating into the light emitting device 100. In addition, the filling member 140 may have an adhesive force so that the coupling between the chip structure 103 and the substrate 101 can be made firmly.
The filling member 140 may be formed of a material having heat transfer characteristics while functioning as an insulator, and for example, flux, a thermoplastic resin, an anisotropic conductive adhesive, and the like may be used.
The flux may be any one of chloride, fluoride, and resin, but is not limited thereto. The flux may insulate between the first and second lead patterns 122 and 112 and transmit heat generated from the chip structure 103 to the substrate 101. In addition, the flux may serve to dissolve and remove oxides on the metal surface, thereby preventing the first and second lead patterns 122 and 112 from being oxidized.
The flux may be coated on the substrate 101 or coated in a spray form before the substrate 101 and the chip structure 103 are bonded to each other. In this case, as shown in FIG. 5, the flux may be applied to an area including the open part 121A between at least the first and second lead patterns 122 and 112 of the substrate 101, and the substrate 101 may be applied. When the chip structure 103 is coupled to each other, the chip structures 103 remain on side surfaces of the first and second lead patterns 122 and 112. In addition, after the substrate 101 and the chip structure 103 are bonded, the flux may be cured.
The thermoplastic resin may include, for example, polyethylene, nylon, polyacetyl resin, vinyl chloride resin, ABS resin, acrylic resin, and the like, but is not limited thereto. The thermoplastic resin may be prepared in a semi-cured or gel state and disposed on the substrate 101, and then may be cured after bonding the substrate 101 and the chip structure 103.
The anisotropic conductive adhesive is an adhesive having conductivity only in the z-axis direction and is a kind of thermoplastic adhesive. High resistance in the x- and y-axis directions prevents current from flowing. The anisotropic conductive adhesive may be in the form of a film or a paste, and may be applied to insulate the first and second lead patterns 122 and 112 between the first and second lead patterns 122 and 112. In addition, the anisotropic conductive adhesive may be cured after being prepared in a semi-cured state or a paste state, after bonding the substrate 101 and the chip structure 103.
On the other hand, the filling member 140 is not limited to being formed of the flux, thermoplastic resin, anisotropic conductive adhesive, it can be formed in various modifications within the range that can be easily implemented by those skilled in the art.
After the filling member 140 is formed, the substrate 101 and the chip structure 103 are opposed to each other, and the substrate 101 and the chip structure 103 are joined in a bonding manner (S129 of FIG. 7). ), The growth substrate 130 is removed (S131 of FIG. 7).
In detail, the first pad 135 of the chip structure 103 is opposed to the first lead pattern 122 of the substrate 101, and the chip structure is formed on the second lead pattern 112. The second pad 136 of the 103 is opposed. The first pad 135 and the second pad 136 are bonded to the first lead pattern 122 and the second lead pattern 122. Here, the bonding may be selectively used using a conductive adhesive, or using a solder bump, a stud bump, or a solder bump.
When the substrate 101 and the chip structure 103 are bonded to each other, the bottom surface of the pad of the chip structure 103 may be adhered to the substrate 101 in close contact with each other, thereby improving thermal conduction efficiency. .
In addition, the filling member 140 has an adhesive force so that the substrate 101 and the chip structure 103 are firmly coupled, and transfers heat generated from the chip structure 103 to the substrate 103 or releases itself. Thus, heat dissipation characteristics of the light emitting device 100 may be improved.
After the substrate 101 and the chip structure 103 are bonded to each other, the growth substrate 130 on the chip structure 103 is removed. The growth substrate 130 may be removed by a laser lift off (LLO) process or may be removed by etching, but is not limited thereto.
Referring to FIG. 6, a dicing process for chip separation is performed (133 of FIG. 7). The dicing process may be performed through the lower portion of the substrate 101 or through the upper portion of the chip structure 103 to a blade, and the dicing process may cut the substrate 101 into individual chips. As a process for separating by cutting, it may be changed within the technical scope of the embodiment.
Through the dicing process, the light emitting device 100 may be provided as shown in FIG. 1.
As such, the method of manufacturing the light emitting device 100 does not bond the LED chip unit, but bonds the chip structure 103 at the wafer level to the substrate 101. Simple and efficient, there is an advantage that the wire bonding process can be omitted.
Second Embodiment
Hereinafter, the light emitting device 200 and the manufacturing method thereof according to the second embodiment will be described in detail. In the description of the second embodiment, the same parts as those of the first embodiment are referred to the first embodiment, and redundant description thereof will be omitted.
8 is a view showing a light emitting device 200 according to the second embodiment.
Referring to FIG. 8, the light emitting device 200 includes a substrate 101 and a chip structure 103.
External electrodes 116 and 126 are formed on the bottom surface of the substrate 101, and the first external electrode 126 and the second external electrode 116 are spaced apart from each other by the open part 121B.
A dicing groove 150 may be formed on the outer lower periphery of the substrate 101, that is, in the process of separating the light emitting device 200 into chips by notch etching. The groove 150 may be formed by etching the lower surface insulating layer 115 and a portion of the substrate 101.
In this case, a groove insulating layer 153 may be formed in the dicing groove 150. This is to ensure reliability in a surface mount technology (SMT) process for mounting the light emitting device 200 to a light emitting module.
In detail, the light emitting device 200 emits light between the external electrodes 116 and 126 and the light emitting module by soldering using, for example, solder bumps, stud bumps, solder bumps, and the like. Can be mounted to the module. When soldering is performed, solder may flow along the lower surface insulating layer 115 to the side surface of the substrate 101 to contact the body 110 of the substrate 101. When the body 110 is made of a conductive material, the body 110 and the external electrodes 116 and 126 may be electrically shorted with each other to reduce the reliability of the light emitting device 200. Accordingly, the groove insulating layer 153 is formed in the dicing groove 150 so that the body 110 and the external electrodes 116 and 126 are not shorted by the solder or the like, thereby improving reliability of the light emitting device 200. Can be improved.
Features, structures, effects, and the like described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in each embodiment may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.
In addition, the above description has been made with reference to the embodiment, which is merely an example, and is not intended to limit the present invention. Those skilled in the art to which the present invention pertains will be illustrated as above without departing from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.
