KR101047708B1

KR101047708B1 - Light emitting device and manufacturing method

Info

Publication number: KR101047708B1
Application number: KR1020090102807A
Authority: KR
Inventors: 조범철
Original assignee: 엘지이노텍 주식회사
Priority date: 2009-10-28
Filing date: 2009-10-28
Publication date: 2011-07-08
Also published as: KR20110046008A

Abstract

In one embodiment, a light emitting device includes: a substrate including a first lead pattern and a second lead pattern on an upper surface thereof; And a compound semiconductor layer including a first conductivity type semiconductor layer, an active layer under the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer under the active layer, and formed under the first conductivity type semiconductor layer. A first pad bonded to the one lead pattern, a second pad formed under the second conductive semiconductor layer and bonded to the second lead pattern, a current spreading layer on the compound semiconductor layer, and the first conductive And a chip structure including at least one conductive via electrically connecting the current spreading layer and the first pad to penetrate a semiconductor semiconductor layer.

Light emitting element

Description

Light emitting device and method for manufacturing thereof

The embodiment relates to a light emitting device and a method of manufacturing the same.

Light emitting diodes (LEDs) are semiconductor light emitting devices that convert current into light.

The wavelength of light emitted by the light emitting diode depends on the semiconductor material used to manufacture the light emitting diode. This is because the wavelength of the emitted light is determined in accordance with the band-gap of the semiconductor material, which represents the energy difference between valence band electrons and conduction band electrons.

Recently, the light emitting diode is gradually increasing in brightness, and is being used as a light source for a display, an automotive light source, and an illumination light source. A light emitting diode that emits white light having high efficiency by using a fluorescent material or by combining various color light emitting diodes. It is also possible to implement.

On the other hand, the brightness of the light emitting diode depends on various conditions such as the structure of the active layer, the light extraction structure that can effectively extract light to the outside, the size of the chip, the type of the molding member surrounding the light emitting diode.

The embodiment provides a light emitting device that operates stably by forming a current spreading layer to allow current to spread evenly over the compound semiconductor.

The embodiment provides a light emitting device having improved heat dissipation characteristics.

In the method of manufacturing a light emitting device according to the embodiment, a compound semiconductor layer is formed by sequentially growing a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer on a growth substrate, and forming a first semiconductor layer on the first conductive semiconductor layer. Forming a chip structure by forming a second pad on the pad and the second conductive semiconductor layer; Forming a substrate having a first lead pattern and a second lead pattern corresponding to the first pad and the second pad; Coupling the chip structure and the substrate such that the first pad and the second pad correspond to the first lead pattern and the second lead pattern; Removing the growth substrate; And forming a current spreading layer on the compound semiconductor layer.

The embodiment can provide a light emitting device that can stably operate by forming a current spreading layer to spread current evenly over the compound semiconductor.

The embodiment can provide a light emitting device having improved heat dissipation characteristics.

In the description of the embodiments, it is to be understood that each layer (film), region, pattern or structure is formed "on" or "under" a substrate, each layer The terms " on "and " under " encompass both being formed" directly "or" indirectly " In addition, the criteria for the top or bottom of each layer will be described with reference to the drawings.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

Hereinafter, a light emitting device and a method of manufacturing the same according to embodiments will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a light emitting device 100 according to an embodiment.

Referring to FIG. 1, the light emitting device 100 includes a substrate 101 and a chip structure 103. The light emitting device 100 may have the same diameter as the diameter of the substrate 101 and the chip structure 103.

The substrate 101 may include an insulating substrate, a conductive substrate, or a flexible substrate. The substrate 101 may be a Si substrate, an AlN substrate, a metal core PCB (MCPCB), a single layer or a multilayer low temperature co-fired ceramic (LTCC) substrate, a single layer or a multilayer high temperature co-fired ceramic (HTCC), or a general PCB. Etc. can be used selectively.

The substrate 101 includes a body 110 and has a via structure including a plurality of via holes 113A. However, this is not limitative.

First insulating layers 111, 113, and 115 are formed on the surface of the substrate 101 and the via hole 113A. An upper insulating layer 111 is formed on an upper surface of the first insulating layers 111, 113, and 115, a via insulating layer 113 is formed in a plurality of via holes 113A of the substrate 111, and a lower surface of the substrate is formed. In this case, the insulating layer 115 may be formed. The first insulating layers 111, 113, and 115 may not be formed when the body 110 of the substrate 101 is a non-conductive material.

First and second lead patterns 122 and 112 are formed on an upper surface of the substrate 101. The first and second lead patterns 122 and 112 may be electrically insulated from each other by the open part 121A. The first and second lead patterns 122 and 112 may be formed in various sizes and shapes according to a predetermined circuit design pattern, but are not limited thereto.

Upper surfaces of the first lead pattern 122 and the second lead patterns 122 and 112 may be formed on the same plane. Accordingly, the chip structure 103 may be bonded to the substrate 101 without being inclined.

The via insulation layer 113 is formed in the via hole 113A, and the via electrodes 114 and 124 are formed in the via insulation layer 113. The first via electrode 124 is branched from the first lead pattern 122, and the second via electrode 114 is formed to branch from the second lead pattern 112.

External electrodes 116 and 126 are formed on the bottom surface of the substrate 101, and the first external electrode 126 and the second external electrode 116 are spaced apart from each other by the open part 121B. The external electrodes 116 and 126 may be formed in various sizes and shapes according to the pattern of the preset circuit design, but are not limited thereto.

The first via electrode 124 connects the first lead pattern 122 and the first external electrode 126 to each other, and the second via electrode 114 is connected to the second lead pattern 112. The second external electrode 116 is connected to each other.

A dicing groove 170 may be formed on the outer lower periphery of the substrate 101, that is, in the process of separating the light emitting device 100 into chips by notch etching. The recessed groove 170 may be formed by etching a portion of the lower insulating layer 115 and the body 110.

The chip structure 103 may include a plurality of compound semiconductor layers including group 2 to group 6 compound semiconductors. For example, the chip structure 103 may be implemented as an LED chip using a group 3 to group 5 compound semiconductor. The LED chip may be a colored LED chip that emits light such as blue, green, or red, or may be a UV LED chip. The semiconductor material of the LED chip and its emission light may be variously implemented within the technical scope of the embodiment.

The chip structure 103 may include a first conductive semiconductor layer 131, an active layer 132 under the first conductive semiconductor layer 131, and a second conductive semiconductor layer 133 under the active layer 132. The first pad 135 is disposed under the first conductive semiconductor layer 131, and the second pad 136 is disposed under the second conductive semiconductor layer 133.

The first conductive semiconductor layer 131 is a compound semiconductor of a Group III-V group element doped with a first conductive dopant, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and the like can be selected. When the first conductive semiconductor layer 131 is an N-type semiconductor layer, the first conductive dopant includes an N-type dopant such as Si, Ge, Sn, Se, Te, or the like.

An active layer 132 is formed under the first conductive semiconductor layer 131, and the active layer 132 may have a single quantum well structure, a multi-quantum well structure, a quantum line structure, or a quantum dot structure. In the case of the quantum well structure, the active layer 132 may be formed by using a compound semiconductor material of Group III-Group 5 elements in a cycle of a well layer and a barrier layer, for example, a cycle of an InGaN well layer / GaN barrier layer. .

The active layer 132 may be selected as a material having a band gap energy according to the wavelength of light to emit light. The active layer 132 may include a material that emits colored light such as light of blue wavelength, light of red wavelength, and light of green wavelength, but is not limited thereto. A conductive cladding layer may be formed on or under the active layer 132, and the conductive cladding layer may be formed of an AlGaN layer.

A second conductive semiconductor layer 133 is formed under the active layer 132. The second conductive semiconductor layer 133 may be a compound semiconductor of a Group III-5 element doped with a second conductive dopant, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaAsP and the like can be selected. When the second conductive semiconductor layer 133 is a P-type semiconductor layer, the second conductive dopant includes a P-type dopant such as Mg or Ze.

Here, the first conductive semiconductor layer 131, the active layer 132, and the second conductive semiconductor layer 133 may be defined as a minimum light emitting structure. In addition, the first conductive semiconductor layer 131 may be a P-type semiconductor, and the second conductive semiconductor layer 133 may be formed of an N-type semiconductor. A third conductive semiconductor layer, for example, an N-type semiconductor layer or a P-type semiconductor layer may be formed under the second conductive semiconductor layer 133. Accordingly, the light emitting structure may include at least one of an N-P junction, a P-N junction, an N-P-N junction, and a P-N-P junction structure.

A first pad 135 may be formed under the first conductive semiconductor layer 131. The first pad 135 may be formed in a pattern such as a circle shape, a polygon shape, a ring shape, a branched or bent shape, a multi-window shape, and the like. The first pad 135 may be formed in single or plural in the chip structure 103, and the position, formation, and number of the first pad 135 may be changed within the technical scope of the embodiment. The pattern shape of the first pad 135 may be formed in consideration of the emission area of the active layer 132.

A second pad 136 is formed under the second conductive semiconductor layer 133. The second pad 136 may be formed on the whole or part of the bottom surface of the second conductive semiconductor layer 133.

The first pad 135 or / and the second pad 136 may be formed of at least one or a plurality of alloy materials among Ag, Rh, Ni, Au, Pd, Ir, Ti, Pt, W, Al, and the like. have.

An ohmic contact layer may be formed in a pattern or a layer shape between the second pad 136 and the second conductive semiconductor layer 133. The ohmic contact layer may be Ni, Pt, Ir, Rh, Ag, indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZO), or indium gallium zinc (IGZO). oxide), indium gallium tin oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IrOx, RuOx, RuOx / ITO, Ni / IrOx / Au, and Ni / IrOx It may include at least one of / Au / ITO.

A second insulating layer 137 may be formed around the outer circumference of the chip structure 103. The second insulating layer 137 may be formed in a region of the lower surface of the chip structure 103 except for the second pad 136 and the first pad 135.

The second insulating layer 137 is formed around the first pad 135 to prevent a short problem with other layers 132, 133, and 136. The second insulating layer 137 may be formed of an insulating material. For example, SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ And the like.

The first pad 135 and the second pad 136 may be formed on the same plane. The first pad 135 may be formed relatively thick so that the first pad 135 may be coplanar with the second pad 136, or the bonding pad may be thickened on the bottom surface of the first pad 135 to form the second pad 136. ) Can eliminate the height difference.

The current spreading layer 160 may be formed on the compound semiconductor layer, and a conductive via 150 may be formed to electrically connect the current spreading layer 160 and the first pad 135. The conductive via 150 may be formed through the compound semiconductor layer.

The current spreading layer 160 allows the current to spread smoothly through the compound semiconductor layer (Current Spreading), so that the light emitting device 100 can emit light stably, the heat radiation characteristics of the light emitting device 100 Can improve.

The current spreading layer 160 may be formed of a transparent material or an opaque material while having electrical conductivity. For example, the current spreading layer 160 may be formed of a metal, a metal oxide, or a compound semiconductor.

The current spreading layer 160 is made of transparent material such as ITO, IZO (In-ZnO), GZO (Ga-ZnO), AZO (Al-ZnO), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), It may include, but is not limited to, at least one of IrOx, RuOx, RuOx / ITO, Ni / IrOx / Au, and Ni / IrOx / Au / ITO.

The current spreading layer 160 of opaque material may include titanium (Ti), chromium (Cr), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), tungsten (W), and copper (Cu). ), Or may be a compound semiconductor containing at least one of molybdenum (Mo) or implanted with impurities, but is not limited thereto.

On the other hand, the current spreading layer 160 may be formed in a different shape depending on whether the material is transparent.

2 and 3 are views illustrating a case where the current spreading layer 160 is formed of an opaque material and a transparent material, respectively.

Referring to FIG. 2, when the current spreading layer 160 is formed of an opaque material, the current spreading layer 160 may have various patterns having openings through which light can be emitted. In particular, the various patterns are preferably formed to overlap the active layer 132 in a vertical direction, but is not limited thereto.

2 (a) is the various patterns of the current spreading layer 160 is formed in a trident-shaped pattern, Figure 2 (b) is the various patterns are formed in a pattern of X (x) shape, The various patterns may be formed to be evenly distributed on the compound semiconductor layer.

As such, the various patterns of the current spreading layer 160 formed of an opaque material may be formed in a shape capable of effectively spreading the current through the compound semiconductor layer while emitting light effectively, but are not limited thereto.

Referring to FIG. 3, when the current spreading layer 160 is formed of a transparent material, the current spreading layer 160 may be formed in all or most regions of the compound semiconductor layer.

Since the current spreading layer 160 is transparent, light generated in the active layer 132 passes through the current spreading layer 160 even though the current spreading layer 160 is formed in most regions of the compound semiconductor layer. Because it can be.

Meanwhile, although the current spreading layer 160 is formed of a transparent material, the current spreading layer 160 may be formed to have various patterns, but is not limited thereto.

In addition, an uneven pattern may be formed on the upper surface of the current spreading layer 160 to improve light extraction efficiency.

The current spreading layer 160 and the first pad 135 are electrically connected to each other by the conductive via 150, and the current spreading layer 160 receives the current provided from the first pad 135. It is effectively spread over the compound semiconductor layer.

The conductive via 150 is formed to penetrate the first conductive semiconductor layer 131, forms a second via hole in the first conductive semiconductor layer 131, and then performs a plating process on the second via hole. It can be formed by filling the conductive material by performing.

One end of the conductive via 150 contacts the first pad 135, and the other end contacts the via contact portion 161 of the current spreading layer 160.

Although one conductive via 150 is illustrated as being formed, a plurality of conductive vias 150 may be formed but are not limited thereto.

The plating process may include electroless plating and electric plating. First, an electroless plating is formed on an inner wall of the second via hole to form a seed layer, and then the seed layer is used. Electroplating can be performed.

Alternatively, after the seed layer is deposited before the plating process, plating may be performed using the seed layer, but is not limited thereto.

The conductive material used in the plating process may include, for example, at least one metal such as copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), tin (Sn), and the like. It is not limited.

The chip structure 103 and the substrate 101 are joined by bonding to each other. The first pad 135 of the chip structure 103 is bonded to the first lead pattern 122 of the substrate 101, and the second pad 136 is formed on the second lead pattern of the substrate 101. 112). Since the two pads 135 and 136 of the chip structure 103 are directly bonded to the lead patterns 122 and 112 on the substrate 101, heat dissipation characteristics of the light emitting device 100 may be improved.

4 to 9 are views illustrating a method of manufacturing the light emitting device 100 according to the embodiment, and FIG. 10 is a flowchart illustrating a method of manufacturing the light emitting device 100.

Referring to FIG. 4, a compound semiconductor layer of Groups 2 to 6 is formed on the growth substrate 130 (S101 of FIG. 10).

The growth substrate 130 may be selected from the group consisting of sapphire substrate (Al ₂ O ₃ ), GaN, SiC, ZnO, Si, GaP, InP, and GaAs, Ga ₂ O ₃ .

The compound semiconductor layer of Groups 2 to 6 is electron beam deposition (E-beam deposition), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal deposition (dual-type thermal) It may be formed by a method such as evaporation sputtering, metal organic chemical vapor deposition (MOCVD), but is not limited thereto.

The group 2 to 6 compound semiconductor layer includes a first conductive semiconductor layer 131, an active layer 132, and a second conductive semiconductor layer 133, and is below the first conductive semiconductor layer 131. A buffer layer (not shown) and / or a nonconductive semiconductor layer (not shown) may be further included.

The first conductive semiconductor layer 131 is formed on the growth substrate 130, and the first conductive semiconductor layer 131 is a compound semiconductor of a Group 3-5 element doped with a first conductive dopant. , GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and the like.

When the first conductive semiconductor layer 131 is an N-type semiconductor layer, the first conductive dopant may include an N-type dopant such as Si, Ge, Sn, Se, Te, and the like, and may be formed as a single layer or a multilayer. have.

An active layer 132 is formed on the first conductive semiconductor layer 131, and the active layer 132 may have a single quantum well structure, a multi-quantum well structure, a quantum line structure, or a quantum dot structure. In the case of the quantum well structure, the active layer 132 may be formed by using a compound semiconductor material of Group III-Group 5 elements in a cycle of a well layer and a barrier layer, for example, a cycle of an InGaN well layer / GaN barrier layer. .

A conductive cladding layer may be formed on or under the active layer 132, and the conductive cladding layer may be formed of an AlGaN layer.

The second conductive semiconductor layer 133 is formed on the active layer 132. The second conductive semiconductor layer 133 is a compound semiconductor of a Group III-V group element doped with a second conductive dopant, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaAsP and the like can be selected. When the second conductive semiconductor layer 133 is a P-type semiconductor layer, the second conductive dopant includes a P-type dopant such as Mg and Zn.

After the growth of the Group 2 to Group 6 compound semiconductor layer on the growth substrate 130, the etching groove 141 is formed by performing Mesa etching (Mesa Etching) on the Group 2 to Group 6 compound semiconductor layer ( S102 of FIG. 10).

The etching groove 141 may be formed in a shape corresponding to the first pad formation region, and the depth of the etching groove 141 may be formed to expose the first conductive semiconductor layer 131.

After the mesa etching, a second via hole is formed in the etching groove 141 to penetrate the compound semiconductor layer, that is, the first conductive semiconductor layer 131 (S103 of FIG. 10), and then into the second via hole. The conductive via 150 is formed by filling the conductive material by a plating process or the like (S104 of FIG. 10).

The second via hole may be formed using laser drilling, etching, or the like, but is not limited thereto. The second via hole is formed in the etching groove 141 to penetrate the compound semiconductor layer, that is, the first conductive semiconductor layer 131, thereby exposing the growth substrate 130 through the second via hole. Can be.

Referring to FIG. 5, the conductive via 150 is formed by filling a conductive material in the second via hole, for example, by a plating process.

The conductive material used in the plating process may include, for example, at least one metal such as copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), tin (Sn), titanium (Ti), or the like. But it is not limited thereto.

Meanwhile, although one conductive via 150 is illustrated as being formed, a plurality of conductive vias 150 may be formed, but the embodiment is not limited thereto.

After the conductive vias 150 are formed, an insulating layer forming step and an electrode forming step (S105 and S107 in FIG. 10) are performed.

5 and 6, the insulating layer forming process is performed to form a second insulating layer 137. The second insulating layer 137 may be formed in the etching groove 141, and may be formed to the thickness of the first pad 135. The second insulating layer 137 is formed around the first pad 135, and the first pad 135, the second conductive semiconductor layer 133, the active layer 132 and the second are formed around the first pad 135. Electrical contact with the pad 136 is blocked.

After the second insulating layer 137 is formed, the pads 135 and 136 are formed through the electrode forming process. The first pad 135 is formed on the first conductive semiconductor layer 131 by the electrode forming process, and the second pad 136 is formed on the second conductive semiconductor layer 133. do. The first pad 135 is formed to contact the conductive via 150.

The first pad 135 may be changed according to the shape of the etching groove 141, and may be spaced apart from the active layer 132 and the second conductive semiconductor layer 133. The second pad 136 may be formed on the entire surface of the second conductive semiconductor layer 133 except for the etching groove 141 or may be formed on a portion of the surface thereof.

Meanwhile, since the pads 135 and 136 may be formed first and then the second insulating layer 137 may be formed, the relationship between the electrode forming process and the insulating layer forming process may be changed, but is not limited thereto.

In this way, the chip structure 103 can be provided.

Referring to FIGS. 7 and 8, the chip structure 103 may be inverted by 180 degrees, face the pre-fabricated substrate 101, and may be bonded as shown in FIG. 8.

The substrate 101 may include an insulating substrate, a flexible substrate, or a conductive substrate. The substrate 101 may be a Si substrate, an AlN substrate, a metal core PCB (MCPCB), a single layer or a multilayer low temperature co-fired ceramic (LTCC) substrate, a single layer or a multilayer high temperature co-fired ceramic (HTCC), or a general PCB. Etc. can be used selectively.

The substrate 101 forms the via hole 113A through the via hole 113A process (S121 of FIG. 10), and etches the chip boundary region to distinguish individual chips, thereby dicing the grooves 170. 10) (S123 of FIG. 10), the first insulating layers 111, 113, and 115 are formed (S124 of FIG. 10), and the via electrodes 114 and 124 are formed by filling a conductive material in the via hole 113A ( 10, the lead patterns 122 and 112 and the external electrodes 126 and 116 are formed through a wiring process (S127 of FIG. 10).

In detail, the first insulating layers 111, 113, and 115 may be formed on the top, bottom, and via holes 113A of the substrate 101. The first insulating layers 111, 113, and 115 are formed of an upper insulating layer 111 formed on an upper surface of the substrate 101, a via insulating layer 113 formed in a via hole 113A of the substrate 101, and a lower surface of the substrate 101. It includes a lower insulating layer 115 formed on.

The first insulating layers 111, 113, and 115 may be formed of an insulating material. For example, SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ It may optionally be formed in the back, but is not limited thereto.

The first and second lead patterns 122 and 112 are formed on an upper surface of the substrate 101. The first and second lead patterns 122 and 112 are spaced apart from each other by the open part 121A. The first and second lead patterns 122 and 112 may be formed in various sizes and shapes according to a wiring pattern of a predetermined circuit design.

The via electrodes 114 and 124 are insulated from the via hole 113A of the substrate 101 by the via insulating layer 113.

First and second external electrodes 126 and 116 are formed on the bottom surface of the substrate 101 and spaced apart from each other by the open part 121B, and the first and second external electrodes 126 and 116 have a predetermined circuit design pattern. It can be formed in various ways.

A dicing groove 170 corresponding to an individual chip spacing D1 is formed below the substrate 101, and the dicing groove 170 is a chip boundary region, and a notch etching is performed on the substrate 101. by etching). The notch etching process may be performed before forming the insulating layer, but is not limited thereto.

The dicing groove 170 may proceed through wet etching or / and dry etching after mask patterning using a mask layer. The wet etching is performed using a KOH or HNA solution (fluoric acid, nitric acid, acetic acid mixture) for the region where the mask layer is not formed, and the dry etching is performed to perform etching using SF ₆ or XeF _2- based reaction gas. do.

After the substrate 101 and the chip structure 103 are formed, the substrate 101 and the chip structure 103 are opposed to each other and bonded to each other (S129 in FIG. 10) to remove the growth substrate 130. (S131 of FIG. 10).

Referring to FIGS. 7 and 8, the first pad 135 of the chip structure 103 is opposed to the first lead pattern 122 of the substrate 101, and the second lead pattern ( 112 faces the second pad 136 of the chip structure 103. The first pad 135 and the second pad 136 are bonded to the first lead pattern 122 and the second lead pattern 122. In this connection, the conductive adhesive may be used, or solder bumps, stud bumps, and solder bumps may be selectively used.

When the substrate 101 and the chip structure 103 are bonded to each other, the bottom surface of the pad of the chip structure 103 may be adhered to the substrate 101 in close contact with each other, thereby improving thermal conduction efficiency. .

After the substrate 101 and the chip structure 103 are bonded to each other, the growth substrate 130 on the chip structure 103 is removed. The growth substrate 130 may be removed by a laser lift off (LLO) process or may be removed by etching, but is not limited thereto.

After removing the growth substrate 130, the exposed surface of the compound semiconductor layer may be etched (S132 of FIG. 10).

In this case, the exposed compound semiconductor layer may be any one of the first conductive semiconductor layer 131, the buffer layer (not shown), and the non-conductive semiconductor layer (not shown).

The etching may be performed by a wet etching method using an etching solution such as KOH, but is not limited thereto. The etching may remove the buffer layer and / or the non-conductive semiconductor layer (not shown), and may partially remove the first conductive semiconductor layer 131.

In addition, a light extraction pattern may be formed on the surface of the compound semiconductor layer by the etching.

After the etching, the current spreading layer 160 may be formed on the compound semiconductor layer (S133 of FIG. 10).

Referring to FIG. 9, the current spreading layer 160 is illustrated as being formed on the first conductive semiconductor layer 131. For example, the current spreading layer 160 may be the buffer layer or the buffer layer. It may be formed on a non-conductive semiconductor layer (not shown), but is not limited thereto.

The current spreading layer 160 may have various patterns or shapes such that light may be emitted, depending on whether the material is transparent or not, but is not limited thereto.

In addition, an uneven pattern may be formed on the upper surface of the current spreading layer 160, thereby improving light extraction efficiency of the light emitting device 100.

9 and 1, a dicing process for chip separation is performed (135 of FIG. 10), whereby the light emitting device 100 according to the embodiment is provided. The dicing process may be performed through the lower portion of the substrate 101 or through the upper portion of the chip structure 103 to a blade, and the dicing process may cut the substrate 101 into individual chips. As a process for separating by cutting, it may be changed within the technical scope of the embodiment.

As such, the method of manufacturing the light emitting device 100 does not bond the LED chip unit, but bonds the chip structure 103 at the wafer level to the substrate 101. Simple and efficient, there is an advantage that the wire bonding process can be omitted.

In addition, since the current spreading layer 160 is formed on the compound semiconductor layer, the light emitting device 100 may smoothly spread a current in the compound semiconductor layer, and thus may operate stably. 100) reliability is improved. In addition, the heat dissipation characteristics of the light emitting device 100 may be improved by the current spreading layer 160.

Features, structures, effects, and the like described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

In addition, the above description has been made with reference to the embodiment, which is merely an example, and is not intended to limit the present invention. Those skilled in the art to which the present invention pertains will be illustrated as above without departing from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 to 10 are views illustrating a light emitting device and a method of manufacturing the same according to an embodiment.

Claims

A substrate including a first lead pattern and a second lead pattern on an upper surface thereof; And

A compound semiconductor layer including a first conductivity type semiconductor layer, an active layer under the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer under the active layer, and formed under the first conductivity type semiconductor layer A first pad bonded to the lead pattern, a second pad formed under the second conductive semiconductor layer and bonded to the second lead pattern, a current spreading layer on the first conductive semiconductor layer, 1. A light emitting device comprising a chip structure comprising at least one conductive via penetrating a conductive semiconductor layer to electrically connect the current spreading layer and the first pad.

The method of claim 1,

A first external electrode and a second external electrode on a lower surface of the substrate,

The first external electrode is electrically connected to the first lead pattern by a first via electrode penetrating the substrate, and the second external electrode is connected to the second lead pattern by a second via electrode penetrating the substrate. Light emitting device electrically connected with.

3. The method of claim 2,

When the substrate is formed of a conductive material,

And an insulating layer on a surface of the substrate, around the first via electrode and the second via electrode.

The method of claim 1,

The current spreading layer is formed of a transparent or opaque material, the light emitting device is formed of any one of a metal, a metal oxide or a compound semiconductor.

The method of claim 4, wherein

The current spreading layer is formed of a transparent material, ITO, IZO (In-ZnO), GZO (Ga-ZnO), AZO (Al-ZnO), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), A light emitting device comprising at least one of IrOx, RuOx, RuOx / ITO, Ni / IrOx / Au, and Ni / IrOx / Au / ITO.

The method of claim 4, wherein

The current spreading layer is formed of an opaque material, titanium (Ti), chromium (Cr), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), tungsten (W), copper (Cu ), A light emitting device comprising at least one of molybdenum (Mo), or a compound semiconductor implanted with impurities.

The method of claim 1,

The current spreading layer is a light emitting device formed in the form of a trident pattern or X (x) pattern that can emit light.

The method of claim 4, wherein

When the current spreading layer is formed of a transparent material, the current spreading layer is a light emitting device formed in all regions on the first conductive semiconductor layer.

The method of claim 1,

The upper surface of the current spreading layer has a light emitting device having an uneven pattern.

The method of claim 1,

The conductive via includes at least one metal of copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), tin (Sn), and titanium (Ti).

The method of claim 1,

And at least one of a nonconductive semiconductor layer and a buffer layer on the first conductive semiconductor layer, wherein the current spreading layer is formed on the nonconductive semiconductor layer or the buffer layer.

The first conductive semiconductor layer, the active layer and the second conductive semiconductor layer are sequentially grown on the growth substrate to form a compound semiconductor layer, and the first pad and the second conductive semiconductor layer are formed on the first conductive semiconductor layer. Forming a chip structure by forming a second pad on the top;

Forming a substrate having a first lead pattern and a second lead pattern corresponding to the first pad and the second pad;

Coupling the chip structure and the substrate such that the first pad and the second pad correspond to the first lead pattern and the second lead pattern;

Removing the growth substrate; And

Forming a current spreading layer on the first conductive semiconductor layer.

The method of claim 12,

Forming the substrate,

Forming a first external electrode electrically connected to the first lead pattern and a second external electrode electrically connected to the second lead pattern on a bottom surface of the substrate.

The method of claim 13,

The first lead pattern and the first external electrode are electrically connected by a first via electrode, and the second lead pattern and the second external electrode are electrically connected by a second via electrode.

And a dielectric layer formed around a surface of the substrate, the first via electrode, and the second via electrode.

The method of claim 12,

The chip structure may include forming at least one conductive via that electrically connects the current spreading layer and the first pad through the first conductive semiconductor layer after the compound semiconductor layer is grown. Manufacturing method.

The method of claim 15,

The conductive via is formed by forming a via hole penetrating through the first conductive semiconductor layer, and then plating the via hole.

The method of claim 12,

The current spreading layer is a light emitting device manufacturing method is formed in the form of a trident pattern or X (x) pattern that can emit light.

The method of claim 12,

And the current spreading layer is formed in all regions on the first conductivity type semiconductor layer.