KR101071996B1 - Shadow mask for manufacturing the micro thermoelectric energy conversion module, and manufacturing method for the shadow mask - Google Patents

Abstract

The present invention relates to a shadow mask for manufacturing a micro thermoelectric energy conversion module, and more particularly, to simplify the manufacturing process of the micro thermoelectric energy conversion module, and to improve the performance of the micro thermoelectric energy conversion module by forming a semiconductor pattern layer at a high temperature. The present invention relates to a shadow mask for manufacturing a micro thermoelectric energy conversion module, which can prevent adhesion of both sides of a semiconductor pattern layer to a shadow mask when the semiconductor pattern layer is formed.

The present invention also relates to a method of manufacturing a shadow mask for manufacturing the micro thermoelectric energy conversion module.

Micro thermoelectric module, cooling, power generation, p-type semiconductor, n-type semiconductor, shadow mask

Description

SHADOW MASK FOR MANUFACTURING THE MICRO THERMOELECTRIC ENERGY CONVERSION MODULE, AND MANUFACTURING METHOD FOR THE SHADOW MASK}

The present invention relates to a shadow mask for manufacturing a micro thermoelectric energy conversion module, and more particularly, to simplify the manufacturing process of the micro thermoelectric energy conversion module, and to improve the performance of the micro thermoelectric energy conversion module by forming a semiconductor pattern layer at a high temperature. The present invention relates to a shadow mask for manufacturing a micro thermoelectric energy conversion module, which can prevent adhesion of both sides of a semiconductor pattern layer to a shadow mask when the semiconductor pattern layer is formed.

The present invention also relates to a method of manufacturing a shadow mask for manufacturing the micro thermoelectric energy conversion module.

Physical phenomena in which heat flow and current affect each other, such as the Seebeck and Peltier effects, are collectively called "thermoelectric effects."

The thermoelectric effect is generated in a circuit in which dissimilar metals or dissimilar semiconductors having different thermoelectric properties are bonded.

When there is a temperature difference at the junction of such dissimilar metals or dissimilar semiconductors, a phenomenon in which a current is generated in this circuit is called a Seebeck effect.

This Seebeck effect is widely used in the field of temperature measurement sensors and the practical use of thermoelectric converters using waste heat.

When a direct current is applied to a dissimilar metal circuit or a circuit in which dissimilar semiconductors are bonded, a phenomenon occurs in which one side of the junction generates heat and the other endothermic, which is called a Peltier effect.

The Peltier effect is used to thermoelectrically cool various chips, devices, etc. including a central processing unit (CPU).

1 is a perspective view illustrating a thermoelectric conversion module using a general hetero semiconductor.

Referring to FIG. 1, the p-type semiconductor 1 and the n-type semiconductor 2 are alternately arranged in the thermoelectric conversion module.

The p-type semiconductor 1 and the n-type semiconductor 2 are connected to the electrode 3, respectively, and the externally connected electrode 4 is connected to the lower end surface of the p-type semiconductor 1 disposed at one end side. The electrode 5 to be externally connected is connected to the lower end surface of the N-type semiconductor 2 arranged on the other end side.

The P-type semiconductor 1 and the N-type semiconductor 2 are connected in series in a π type between the electrode 4 and the electrode 5.

A good thermally conductive substrate 6 is in contact with the electrode 3 connected to the upper end surfaces of the P-type semiconductor 1 and the N-type semiconductor 2.

The thermally conductive substrate 7 is in contact with the electrodes 3, 4, 5 connected to the lower end surfaces of the P-type semiconductor 1 and the N-type semiconductor 2.

When a direct current power source is connected between the electrode 4 and the electrode 5, the electrode 5 is placed on the positive side and the electrode 4 is placed on the negative side. In the junction between the p-type semiconductor 1 and the n-type semiconductor 2, the heat conductive substrate 6 absorbs and cools the heat, depending on the current direction, and heats the heat conductive substrate 7 by emitting heat. .

On the other hand, a load is connected between the electrode 4 and the electrode 5 to form a closed circuit, the thermally conductive substrate 6 is at the low temperature side, and the thermally conductive substrate 7 is at the high temperature side. When a temperature difference is provided between the thermally conductive substrates 7, electric current flows in the closed circuit to obtain power.

Therefore, the thermoelectric conversion module has almost the same basic configuration, and since the power is generated using the Seebeck effect and the temperature can be controlled using the Peltier effect, the thermoelectric conversion module can be used as a thermoelectric power element module and a thermoelectric cooling module.

2A to 2O are sequential process cross-sectional views showing a method of manufacturing a micro thermoelectric cooling module according to the prior art.

Referring to FIG. 2A, a silicon oxide film (SiO ₂ ; 12), a first LOR film 14, and a first photoresist 16 are sequentially formed on the silicon substrate 10.

Here, LOR (Lift off Resistor) is used because it is difficult to implement the T-shape of the pattern having a certain height of the pattern removal region when using a general photoresist in the lift-off process to be described later.

Referring to FIG. 2B, an exposure and development process of the first photoresist 16 is performed to form a first photoresist pattern 16 ′, and an etching process using the first photoresist pattern 16 ′ as an etching mask is performed. Proceeding to form the first LOR pattern 14 '.

Referring to FIG. 2C, titanium / platinum (Ti / Pt; 18), chromium (Cr; 20), and gold (Au; 22) are sequentially deposited through a sputtering process.

Referring to FIG. 2D, a part of the silicon oxide film 12 is exposed by removing the patterned first LOR pattern 14 ′ and the first photoresist pattern 16 ′ by performing a lift-off process. .

Referring to FIG. 2E, a second LOR film 24 is deposited, and a second photoresist 26 is deposited thereon.

Referring to FIG. 2F, a second photoresist pattern 26 ′ defining an n-type pattern region to be described later is formed by performing an exposure and development process, and a second LOR film is formed using the second photoresist pattern 26 ′. The etching process for (24) is performed to form a second LOR pattern 24 'to expose gold (Au) 22 in the n-type pattern region.

Referring to FIG. 2G, a sputtering process is performed to form an n-type semiconductor pattern Bi ₂ Te ₃ ; 28 on gold Au in the n-type pattern region.

Referring to FIG. 2H, the second photoresist pattern 26 ′ and the second LOR pattern 24 ′ are removed by performing a lift-off process.

Referring to FIG. 2I, a third LOR film 30 and a third photoresist 32 are deposited.

Referring to FIG. 2J, a third photoresist pattern 32 ′ defining a p-type pattern region is defined, and the third LOR layer 30 is etched using the third photoresist pattern 32 ′ to form a third LOR. By forming the pattern 30 ', gold (Au) 22 in the p-type pattern region is exposed.

Referring to FIG. 2K, a p-type semiconductor pattern Bi _0.5 Sb _1.5 Te ₃ ; 34 is formed on gold (Au) 22 of the p-type pattern region by sputtering.

Referring to FIG. 2L, a lift-off process is performed to remove the third photoresist pattern 32 ′ and the third LOR pattern 30 ′.

Referring to FIG. 2M, the fourth photoresist 36 is deposited on the entire structure, and the exposure and development processes are performed to expose the n-type semiconductor pattern 28 and the upper surfaces of the p-type semiconductor pattern 34.

Referring to FIG. 2N, titanium / copper / gold (Ti / Cu / Au), which is a cooling connector 38, is formed on the upper surface of the n-type semiconductor pattern 28 and the p-type semiconductor pattern 34 by electroplating.

Referring to FIG. 2O, the fourth photoresist 36 may be removed.

In the method of manufacturing a micro-thermoelectric cooling module according to the related art, an n-type semiconductor pattern is formed on a single substrate, and then a p-type semiconductor pattern is formed, thereby forming a LOR film, a photoresist deposition process, an exposure and development process, and an etching process. And since the LOR pattern and the photoresist removal process needs to be performed several times, process time increases, and process efficiency decreases. That is, the height of the semiconductor pattern is preferably 10 μm or more, the photoresist is not able to form a high height of the prior art requires the formation of a LOR pattern, the semiconductor pattern is usually the best at a temperature of 250 ~ 300 ℃ Since the thermoelectric performance, the co-sputtering process or co-evaporating process is carried out at a temperature of 250 ~ 300 ℃, the photoresist and LOR pattern is weak to high temperature, the above-described prior art is a semiconductor pattern under the temperature of 250 ~ 300 ℃ There is a disadvantage that is difficult to form.

In addition, when manufacturing a thermoelectric cooling module using a conventional shadow mask, the height of the shadow mask is difficult to form a semiconductor pattern of about 10 μm or more, and both sides of the semiconductor pattern are formed on the shadow mask when the semiconductor pattern is formed. There is a disadvantage of being bonded.

The present invention forms a semiconductor pattern layer at a temperature of 250 ~ 300 ℃ having the most thermoelectric performance of the semiconductor pattern layer using a shadow mask having a strong thermal resistance, thereby improving the performance of the micro thermoelectric energy conversion module micro thermoelectric energy A shadow mask for manufacturing a transform module is provided.

The efficiency of the micro thermoelectric energy conversion module is improved when the height of the semiconductor pattern layer is formed to be 10 μm or more, and the present invention provides a micro thermoelectric energy conversion module that can easily form the height of the semiconductor pattern layer to 10 μm or more. We want to provide a shadow mask.

An object of the present invention is to provide a shadow mask for manufacturing a micro thermoelectric energy conversion module in which both sides of the semiconductor pattern are prevented from adhering to the shadow mask when the semiconductor pattern is formed.

The present invention provides a shadow mask for manufacturing a micro thermoelectric energy conversion module in which a p-type semiconductor pattern connected in a π-type and an n-type semiconductor pattern are connected in series, wherein a lower opening 140'-1 penetrating up and down is formed. Membrane pattern layer 141 '; A membrane reinforcing layer 142 'stacked on the membrane pattern layer 141' and having an upper opening 140'-2 penetrating up and down to communicate with the lower opening 140'-1; It relates to a shadow mask for manufacturing a micro thermoelectric energy conversion module comprising a.

In the present invention, the membrane pattern layer 141 'includes an upper membrane pattern layer 141'-1 having a first lower opening 140'-1a forming an upper layer portion of the lower opening 140'-1. ); A lower membrane pattern layer 141'-2 having a second lower opening 140'-1b extending from a lower end of the first lower opening 140'-1a to form a lower layer of the lower opening 140'-1. ); The membrane reinforcing layer 142 'may include a silicon wafer pattern layer 142'-1; A single insulating pattern layer 142'-2 formed under the silicon wafer pattern layer 142'-1; An adhesive auxiliary pattern layer 142'-3 formed under the one side insulating pattern layer 142'-2; A plated electrode pattern layer 142'-4 having a bottom surface formed on the adhesion auxiliary pattern layer 142'-3, the bottom surface of which is in contact with an upper surface of the upper membrane pattern layer 141'-1; The other insulating pattern layer 142'-5 stacked on the silicon wafer pattern layer 142'-1; An etch protection pattern layer 142'-6 stacked on the other insulating pattern layer 142'-5; . ≪ / RTI >

On the other hand, the present invention is a method of manufacturing a shadow mask for manufacturing the micro thermoelectric energy conversion module, the one side insulating layer 142-2, the adhesion auxiliary layer 142-3 and the plating electrode layer (one side) on one side of the silicon wafer 142-1 ( Stacking 142-4) sequentially; Sequentially stacking the other insulating layer (142-5) and the etching protection layer (142-6) on the other side of the silicon wafer (142-1) opposite to one side; Stacking a first one side photoresist pattern layer (142'-7) having a first opening (142'-7h) on one side of the plating electrode layer (142-4); Stacking the upper membrane pattern layer (141'-1) on the first openings (142'-7h) of the first one side photoresist pattern layer (142'-7) by a plating process and a CMP process; A second opening capable of stacking the lower membrane pattern layer 141'-2 on one side of the first photoresist pattern layer 142'-7 and on one side of the upper membrane pattern layer 141'-1 Stacking a second one side photoresist pattern layer 142'-8 having 142'-8h; Stacking the lower membrane pattern layer (141'-2) on the second opening (142'-8h) of the second one side photoresist pattern layer (142'-8) by a plating process and a CMP process; Exposing the membrane pattern layer (141 ') by removing the first one side photoresist pattern layer (142'-7) and the second one side photoresist pattern layer (142'-8); The etching protective layer 142-6 and the other insulating layer 142-5 are sequentially etched, the silicon wafer 142-1 is etched, and the one insulating layer 142-2 and the adhesive auxiliary layer ( 142-3, sequentially etching the plating electrode layer 142-4 to form the upper opening 140'-2; It relates to a method of manufacturing a shadow mask for producing a micro thermoelectric energy conversion module comprising a.

In the present invention, the one insulating layer 142-2 is formed of silicon dioxide (SiO ₂ ), the adhesion auxiliary layer 142-3 is formed of silicon nitride (Si ₃ N ₄ ), the plating The electrode layer 142-4 is formed by sequentially stacking titanium (Ti) and copper (Cu) or sequentially stacking tantalum (Ta) and copper (Cu), and the other insulating layer 142-5 is formed of silicon dioxide. (SiO ₂ ), and the etch protection layer 142-6 may be formed of silicon nitride (Si ₃ N ₄ ).

In the shadow mask according to the present invention, an n-type semiconductor pattern layer and a p-type semiconductor pattern layer are separately formed on each substrate, and then the respective substrates on which the n-type semiconductor pattern layer and the p-type semiconductor pattern layer are formed are bonded. By shortening the process of depositing a plurality of insulating layers and photoresists, production efficiency can be improved by simplifying the manufacturing process of the micro thermoelectric energy conversion module.

In addition, the use of the shadow mask with a strong thermal resistance according to the present invention can form a semiconductor pattern layer at a high temperature having the highest thermoelectric performance of the semiconductor pattern layer, there is an advantage that the performance of the micro thermoelectric energy conversion module is improved. .

Meanwhile, the efficiency of the micro thermoelectric energy conversion module is improved by forming the height of the semiconductor pattern layer higher than 10 μm. When using the shadow mask according to the present invention, the height of the semiconductor pattern layer can be easily formed higher than 10 μm. There are advantages to it.

In addition, the shadow mask according to the present invention has an advantage in that both sides of the semiconductor pattern is prevented from adhering to the shadow mask when the semiconductor pattern is formed.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

Example 1

Embodiment 1 relates to a shadow mask for manufacturing a micro thermoelectric energy conversion module according to the present invention. It is about.

3 shows a schematic cross-sectional view of Embodiment 1. FIG.

Referring to FIG. 3, Embodiment 1 has a membrane pattern layer 141 'and a membrane reinforcement layer 142'.

Referring to FIG. 3, a lower opening 140 ′ -1 penetrating the upper and lower portions of the membrane pattern layer 141 ′ is formed in the membrane pattern layer 141 ′. The lower opening 140'-1 extends from the lower end of the first lower opening 140'-1a and the first lower opening 140'-1a forming the upper layer of the lower opening 140'-1. And a second lower opening 140'-1b forming a lower layer portion of the 140'-1. The membrane pattern layer 141 'may be formed by depositing Ni or the like by a plating process.

Accordingly, the membrane pattern layer 141 ′ may have a lower membrane pattern in which an upper membrane pattern layer 141 ′ -1 and a second lower opening 140 ′ -1 b are formed. Layer 141'-2. The upper membrane pattern layer 141'-1 and the lower membrane pattern layer 141'-2 are formed through a plating process, which will be described in the second embodiment.

Referring to FIG. 3, the membrane reinforcing layer 142 ′ is stacked on the membrane pattern layer 141 ′. The membrane reinforcing layer 142 'is formed with an upper opening 140'-2 penetrating the upper and lower portions of the membrane reinforcing layer 142', and the upper opening 140'-2 is in communication with the lower opening 140'-1. Is formed.

Referring to FIG. 3, the membrane reinforcing layer 142 ′ is formed of a silicon wafer pattern layer 142 ′ -1, one insulating pattern layer 142 ′ -2, an adhesion auxiliary pattern layer 142 ′ -3, and a plated electrode pattern layer ( 142'-4), the other insulating pattern layer 142'-5, and the etching protection pattern layer 142'-6.

Referring to FIG. 3, one side insulating pattern layer 142 ′-2 is stacked below the silicon wafer pattern layer 142 ′-1, and the adhesive auxiliary pattern layer 142 ′ -3 is one side insulating pattern layer 142 ′. -2) is laminated on the bottom.

Referring to FIG. 3, the plated electrode pattern layer 142 ′ -4 is laminated under the adhesion auxiliary pattern layer 142 ′ -3 so that the bottom surface contacts the top surface of the upper membrane pattern layer 141 ′ -1. The plating electrode pattern layer 142'-4 may have a structure in which the first plating electrode pattern layer 142'-4a and the second plating electrode pattern layer 142-4b are sequentially stacked. The first plating electrode pattern layer 142 ′ -4a may be formed of titanium (Ti) or tantalum (Ta), and the second plating electrode pattern layer 142-4b may be formed of copper (Cu).

Referring to FIG. 3, the other insulating pattern layer 142 ′ -5 is stacked on the silicon wafer pattern layer 142 ′ -1, and the etching protection pattern layer 142 ′ -6 is formed on the other insulating pattern layer 142 ′. -5) laminated on top.

Hereinafter, a method of manufacturing a micro thermoelectric energy conversion module using the above embodiment will be described.

4A to 4M are cross-sectional views sequentially illustrating a method of manufacturing a micro thermoelectric energy conversion module according to an embodiment 1, in which a p-type semiconductor pattern connected in a π-type and an n-type semiconductor pattern are connected in series; Process sectional drawing of the method of manufacturing this is shown.

Referring to FIG. 4A, a first insulating layer 110 and a first electrode layer 120 are sequentially formed on the first substrate 100.

In this case, the first substrate 100 is made of a silicon wafer, and the first insulating layer 110 uses a silicon oxide film (SiO ₂ ) formed through a thermal oxidation process.

Here, before the first insulating layer 110 is formed on the first substrate 100, a pattern defect may be prevented from occurring due to a foreign material remaining on the first substrate 100 so that the characteristics of the device may be reduced. The cleaning process can be further carried out to ensure that

The washing process is carried out in a boiling H ₂ SO ₄ : H ₂ O ₂ = 1: 1 solution for 8 to 12 minutes, preferably 10 minutes, and dipped in 50: 1 hydrofluoric acid solution for 6 to 8 minutes, preferably 7 minutes It can be carried out.

In addition, the electrode layer 120 preferably uses gold (Au) having excellent thermal conductivity and electrical conductivity, and may further form titanium (Ti) having excellent adhesive properties in order to improve adhesion between gold and the substrate.

That is, as shown in FIG. 4A, the first electrode layer 120 may have a structure in which titanium (Ti) 120a having a thickness of 20 nm and gold (Au) 120b having a thickness of 200 nm are stacked.

Referring to FIG. 4B, a first-first photoresist layer 131 is formed on the first electrode layer 120. In this case, the first-first photoresist layer 131 may be formed by a spin coating method and then prebaked.

Referring to FIG. 4C, a first-first photoresist pattern layer 131 ′ is formed through an exposure process and a development process of the first-first photoresist layer 131. The first-first opening 131'-1 is formed in the first-first photoresist pattern layer 131 '. By forming the first-first photoresist pattern layer 131 ′, a portion of the first electrode layer 120 disposed under the first-first opening 131 ′ -1 is exposed to the outside.

Referring to FIG. 4D, the first electrode layer 120 is etched using the first-first photoresist pattern layer 131 ′ as an etching mask to form the first electrode pattern layer 120 ′. The first electrode pattern layer 120 'has a structure in which the titanium pattern layer 120'a and the gold pattern layer 120'b are stacked up and down. As the first electrode pattern layer 120 ′ is formed, a portion of the first insulating layer 110 under the first-first opening 131 ′-1 (see FIG. 3C) is exposed to the outside.

Referring to FIG. 4E, the first-first photoresist pattern layer 131 ′ is removed to expose the first electrode pattern layer 120 ′ to the outside.

Referring to FIG. 4F, the shadow mask 140 ′ of the first embodiment is fixed on the first electrode pattern layer 120 ′ by the mask aligner. The shadow mask 140 ′ has a lower opening 140 ′ -1 and an upper opening 140 ′ -2 exposing predetermined portions of the surface of the first electrode pattern layer 120 ′. The shadow mask 140 ′ formed by a separate process is fixed on the first electrode pattern layer 120 ′ by the mask aligner to form a lower portion of the lower opening 140 ′ -1 of the first electrode pattern layer 120 ′. The part where it is located is exposed to the outside. A method of forming the shadow mask 140 'will be described in the second embodiment.

Referring to FIG. 4G, a first semiconductor pattern layer 160 having an n-type type is formed in a portion of the first electrode pattern layer 120 ′ under the lower opening 140 ′-1. The first semiconductor pattern layer 160 may be formed through a co-sputtering process or a co-evaporating process that can control the composition ratio of two materials by adjusting power. For example, pure Bi and Te targets can be used to form a Bi ₂ Te ₃ film, which is a Bi-Te thin film. On the other hand, since the semiconductor pattern layer usually has the best thermoelectric performance at a temperature of 250 ~ 300 ℃, co-sputtering process or co-evaporating process can be carried out under the temperature of 250 ~ 300 ℃. Meanwhile, the plasma cleaning process may be further performed after the first electrode layer 120 is formed in order to improve the adhesion property between the first semiconductor pattern layer 160 and the first electrode pattern layer 120 '.

Referring to FIG. 4H, a nickel layer (Ni) 170 may be formed on the first semiconductor pattern layer 160 to perform diffusion prevention.

Referring to FIG. 4I, the tin layer Sn, which is the first bonding layer 180, is formed on the nickel layer 170 by electroplating.

Referring to FIG. 4J, the shadow mask 140 ′ is removed to complete the first pattern P1.

A process similar to the process of FIGS. 4A to 4J described above is performed to form the second pattern P2 as shown in FIG. 4K. Hereinafter, the method for forming the second pattern P2 will be briefly described.

A second insulating layer 210 and a second electrode layer (not shown) are sequentially formed on the second substrate 200. The second electrode layer (not shown) may be formed in a structure in which titanium and gold are stacked.

A 2-1 photoresist layer (not shown) is formed on the second electrode layer (not shown). Then, the 2-1 photoresist having a 2-1 opening (not shown) corresponding to the 1-1 opening 131'-1 by patterning the 2-1 photoresist layer (not shown). A pattern layer (not shown) is formed.

 Thereafter, the second electrode pattern layer 220 ′ is formed by etching the second electrode layer (not shown) using the second-1 photoresist pattern layer (not shown) as an etching mask. The second electrode pattern layer 220 'is a structure in which the titanium pattern layer 220'a and the gold pattern layer 220'b are stacked up and down.

Thereafter, the 2-1 photoresist pattern layer (not shown) is removed to expose the second electrode pattern layer 220 'to the outside.

On the other hand, the shadow mask 140 'of the first embodiment is fixed by the mask aligner on the second electrode pattern layer 220' exposed to the outside. The shadow mask 140 ′ has a lower opening 140 ′ -1 and an upper opening 140 ′ -2 exposing predetermined portions of the surface of the second electrode pattern layer 220 ′.

Subsequently, a second semiconductor pattern layer 260 having a p-type type is formed in a portion of the second electrode pattern layer 220 ′ under the lower opening 140 ′-1. The second semiconductor pattern layer 260 may be formed through a co-sputtering process or a co-evaporating process that can control the composition ratio of two materials by adjusting power.

Thereafter, an electro-plating process is performed on the second semiconductor pattern layer 260 to form a nickel layer (Ni) 270 which serves to prevent diffusion, and a second bonding layer on the nickel layer 170. A tin layer Sn (280) is formed by an electroplating process, and the second-2 shadow mask (not shown) is removed to complete the second pattern P2.

Other matters which are not described follow the process of forming 1st pattern P1.

Referring to FIG. 4L, the second pattern P2 is inverted on the first pattern P1 so that the first pattern P1 and the second pattern P2 face each other.

Referring to FIG. 4M, the second electrode pattern layer 220 ′ of the second pattern P2 is connected to the first bonding layer 180 of the first pattern P1, and the first pattern P1 of the first pattern P1 is connected. The second thermoelectric energy conversion module is completed by bonding the second bonding layer 280 of the second pattern P2 to the electrode pattern layer 120 '.

The micro thermoelectric energy conversion module manufactured using the first embodiment uses the shadow mask 140 'having a high thermal resistance, so that the semiconductor pattern layer has the first semiconductor pattern at a high temperature (250 to 300 ° C.) having the most thermoelectric performance. The layer 160 and the second semiconductor pattern layer 260 may be formed.

On the other hand, the height of the first semiconductor pattern layer 160 and the second semiconductor pattern layer 260 is preferably 10 μm or more, but the photoresist cannot form a high height of the photoresist and is weak to heat. It is difficult to form highly efficient semiconductor pattern layers 160 and 260. However, in Example 1, the height of the membrane pattern layer 141 ′ may be increased by the plating process, so that the height of the first semiconductor pattern layer 160 and the second semiconductor pattern layer 260 is 10 μm or more. It can be formed high.

On the other hand, the conventional shadow mask has a problem that the height of the portion corresponding to the membrane pattern layer 140'-1 of Example 1 is about 200 ~ 500 ㎛ high difficult to form a semiconductor pattern of several tens of ㎛, Example 1 In the case of the shadow mask, the height of the membrane pattern layer 141 ′ may be formed within 100 μm through the plating process, so that the semiconductor pattern layers 160 and 260 may be easily formed to 10 μm or more.

In addition, the shadow mask 140 'of the first embodiment has a lower opening 140'-1 formed in the membrane pattern layer 141' and a first lower opening 140'-1a and a first lower opening 140'-. Since it is divided into the second lower openings 140 ′-1b extending from the lower end of 1a, referring to FIG. There is an advantage that the adhesion to ') is prevented.

Example 2

Example 2 relates to a method of manufacturing the shadow mask of Example 1.

5A to 5K show sequential process cross-sections of Example 2. FIG.

Referring to FIG. 5A, first, an insulating layer 142-2, an adhesive auxiliary layer 142-3, and a plating electrode layer 142-4 are sequentially stacked on one side of a silicon wafer 142-1.

The insulating layer 142-2 may be formed in a structure in which silicon dioxide (SiO ₂ ) is stacked, and the adhesion auxiliary layer 142-3 may be formed in a structure in which silicon nitride (Si ₃ N ₄ ) is stacked. All.

Meanwhile, the plating electrode layer 142-4 may have a structure in which the first plating electrode layer 142-4a and the second plating electrode layer 142-4b are sequentially stacked. The first plating electrode layer 142-4a may be formed of titanium (Ti) or tantalum (Ta), and the second plating electrode layer 142-4b may be formed of copper (Cu).

Referring to FIG. 5A, the other insulating layer 142-5 and the etch protection layer 142-6 are sequentially stacked on the other side of the silicon wafer 142-1 that faces one side thereof.

The other insulating layer 142-5 may have a structure in which silicon dioxide (SiO ₂ ) is stacked, and the etch protection layer 142-6 may have a structure in which silicon nitride (Si ₃ N ₄ ) is stacked. .

Referring to FIG. 5B, a first photoresist pattern layer 142 ′ -7 having a first opening 142 ′ − 7 h is formed in the plating electrode layer 142-4.

Referring to FIG. 5C, an upper membrane pattern layer 141 ′ -1 may be stacked on the first openings 142 ′ -7 h of the first photoresist pattern layer 142 ′ -7 by a plating process and a CMP process. .

Referring to FIG. 5D, one side of the first one side photoresist pattern layer 142 ′ -7 and one side of the upper membrane pattern layer 141 ′ -1 may have a lower membrane pattern layer 141 ′ -2 (see FIG. 3). The second one side photoresist pattern layer 142'-8 having the second openings 142'-8h that can be stacked is stacked. That is, when the second one side photoresist pattern layer 142 ′ -8 is stacked on one side of the first side photoresist pattern layer 142 ′ -7 and the upper membrane pattern layer 141 ′ -1, the second opening is formed. A portion of the upper membrane pattern layer 141'-1 is exposed to the outside through 142'-8h.

Referring to FIG. 5E, the lower membrane pattern layer 141'-2 is formed by laminating the second openings 142'-8h of the second one side photoresist pattern layer 142'-8 by the plating process and the CMP process. step;

Referring to FIG. 5F, the first side photoresist pattern layer 142 ′ -7 and the second side photoresist pattern layer 142 ′ -8 are removed to expose the membrane pattern layer 141 ′. The lower opening 140'-1 is formed in the exposed membrane pattern layer 141 'by removing the first one side photoresist pattern layer 142'-7 and the second one side photoresist pattern layer 142'-8. do.

Referring to FIG. 5G, another photoresist pattern layer 142 ′ -9 having a third opening 142 ′ − 9 h is formed under the etch protection layer 142-6.

Referring to FIG. 5H, the etching protection pattern layer 142 ′ -6 and the other insulating pattern layer 142 ′ -5 are sequentially formed using the other photoresist pattern layer 142 ′ -9 as an etching mask.

Referring to FIG. 5I, when the etching protection pattern layer 142 ′ -6 and the other insulating pattern layer 142 ′ -5 are formed, the other photoresist pattern layer 142 ′ -9 is removed.

Referring to FIG. 5J, the silicon wafer pattern layer 142 ′ -1 is formed using the etching protection pattern layer 142 ′ -6 and the other insulating pattern layer 142 ′ -5 as an etching mask. The silicon wafer pattern layer 142 ′ -1 may be formed by wet etching in a KOH solution (40% wt, 60 ° C.). In this case, the etching protection pattern layer 142 ′ -6 serves as a protection layer in the wet etching process.

Referring to FIG. 5K, when the silicon wafer pattern layer 142'-1 is formed, the one side insulating pattern layer 142'-2 and the adhesion assistant pattern are sequentially formed using the silicon wafer pattern layer 142'-1 as an etching mask. The layer 142'-3 and the plating electrode pattern layer 142'-4 are formed. The plated electrode pattern layer 142'-4 is formed of a first plated electrode pattern layer 142'-4a and a second plated electrode pattern layer 142-4b.

Referring to FIG. 5K, the etching protection pattern layer 142 ′ -6, the other insulating pattern layer 142 ′ -5, the silicon wafer pattern layer 142 ′ -1, the one side insulating pattern layer 142 ′ -2, and adhesion The upper opening 140'-2 is formed by forming the auxiliary pattern layer 142'-3 and the plating electrode pattern layer 142'-4.

1 is a perspective view showing a thermoelectric conversion module using a general heterogeneous semiconductor.

Figures 2a to 2o are sequential process cross-sectional view showing a method of manufacturing a micro thermoelectric cooling module according to the prior art.

3 is a schematic cross-sectional view of Embodiment 1;

4A to 4M are cross-sectional views sequentially illustrating a method of manufacturing a micro thermoelectric energy conversion module using Example 1;

Description of the Related Art [0002]

100: first substrate 110: first insulating layer

120: first electrode layer 120 ': first electrode pattern layer

131: First-first photoresist layer 131 ′: First-first photoresist pattern layer

140 ': shadow mask 140'-1: lower opening

140'-1a: first lower opening 140'-1b: second lower opening

140'-2: top opening

141 ': membrane pattern layer 141'-1: upper membrane pattern layer

141'-2: lower membrane pattern layer

142 ': membrane reinforcing layer

142-1: Silicon Wafer 142'-1: Silicon Wafer Pattern Layer

142-2: one side insulating layer 142'-2: one side insulating pattern layer

142-3: Adhesion Auxiliary Layer 142'-3: Adhesion Auxiliary Pattern Layer

142-4: plating electrode layer 142'-4: plating electrode pattern layer

142-5: Insulation layer on the other side 142'-5: Insulation layer on the other side

142-6: etch protective layer 142'-6: etch protective pattern layer

142'-7: first photoresist pattern layer

142'-7h: first opening

142'-8: Photoresist pattern layer on one side of the 21st

142'-8h: second opening

Claims (5)

In the process of manufacturing a micro thermoelectric energy conversion module in which a p-type semiconductor pattern connected in a π-type and an n-type semiconductor pattern are connected in series The first electrode pattern layer in which the titanium pattern layers 120'a and 220'a and the gold pattern layers 120'b and 220'b are stacked up and down to form an n-type first semiconductor pattern layer 160. In the shadow mask fixed by the mask aligner on the second electrode pattern layer 220 'on which the (120') or p-type type second semiconductor pattern layer 260 is formed, An upper membrane pattern layer 141'-1 having a first lower opening 140'-1a forming an upper layer portion of the lower opening 140'-1 penetrating up and down, and a first lower opening 140'-1a Membrane pattern layer 141 including a lower membrane pattern layer 141'-2, which extends from a lower end of the bottom end portion and forms a second lower opening 140'-1b forming a lower layer of the lower opening 140'-1. '); An upper opening 140 ′ -2 is formed on the membrane pattern layer 141 ′ and penetrates up and down to communicate with the lower opening 140 ′ -1. The silicon wafer pattern layer 142'-1, the one side insulating pattern layer 142'-2 formed under the silicon wafer pattern layer 142'-1, and the one side insulating pattern layer 142'-2. ) Adhesion auxiliary pattern layer 142'-3 is formed to be laminated on the bottom, and a lower surface of the adhesion auxiliary pattern layer 142'-3 is laminated to contact the upper surface of the upper membrane pattern layer 141'-1. The plated electrode pattern layer 142'-4, the other insulating pattern layer 142'-5 stacked on the silicon wafer pattern layer 142'-1, and the other insulating pattern layer 142'- 5) a membrane reinforcing layer 142 ' including an etch protection pattern layer 142'-6 stacked on top of the membrane; Shadow mask for manufacturing a micro thermoelectric energy conversion module comprising a. delete delete As a method of manufacturing a shadow mask for producing a micro thermoelectric energy conversion module of claim 1, Sequentially stacking one insulating layer 142-2, an adhesive auxiliary layer 142-3, and a plating electrode layer 142-4 on one side of the silicon wafer 142-1; Sequentially stacking the other insulating layer (142-5) and the etching protection layer (142-6) on the other side of the silicon wafer (142-1) opposite to one side; Stacking a first one side photoresist pattern layer (142'-7) having a first opening (142'-7h) on one side of the plating electrode layer (142-4); Stacking the upper membrane pattern layer (141'-1) on the first opening (142'-7h) of the first one side photoresist pattern layer (142'-7) by a plating process and a CMP process; A second opening capable of stacking the lower membrane pattern layer 141'-2 on one side of the first photoresist pattern layer 142'-7 and on one side of the upper membrane pattern layer 141'-1 Stacking a second one side photoresist pattern layer 142'-8 having 142'-8h; Stacking the lower membrane pattern layer (141'-2) on the second opening (142'-8h) of the second one side photoresist pattern layer (142'-8) by a plating process and a CMP process; Exposing the membrane pattern layer (141 ') by removing the first one side photoresist pattern layer (142'-7) and the second one side photoresist pattern layer (142'-8); The etching protective layer 142-6 and the other insulating layer 142-5 are sequentially etched, the silicon wafer 142-1 is etched, and the one insulating layer 142-2 and the adhesive auxiliary layer ( 142-3, sequentially etching the plating electrode layer 142-4 to form the upper opening 140'-2; Method of producing a shadow mask for manufacturing a micro thermoelectric energy conversion module comprising a. 5. The method of claim 4, The one side insulating layer 142-2 is formed of silicon dioxide (SiO ₂ ), The adhesion auxiliary layer 142-3 is formed of silicon nitride (Si ₃ N ₄ ), The plating electrode layer 142-4 is formed by sequentially stacking titanium (Ti) and copper (Cu) or tantalum (Ta) and copper (Cu) sequentially. The other insulating layer 142-5 is formed of silicon dioxide (SiO ₂ ), The etching protection layer (142-6) is formed of silicon nitride (Si ₃ N ₄ ) characterized in that the manufacturing method of the shadow mask for manufacturing a micro thermoelectric energy conversion module.

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