KR100989643B1 - Method for manufacturing the thin film thermoelectric module and multi-chip pachage using the same - Google Patents

Abstract

PURPOSE: A method for manufacturing a thin film type thermoelectric module and a laminated semiconductor chip package using the same are provided to prevent a semiconductor chip from being damaged by discharging heat from each semiconductor chip. CONSTITUTION: A photosensitive resin layer is formed on by coating a photoresist on the upper side(11) of a silicon substrate(10). A mask is formed on the photosensitive resin layer. An insulation layer(21) is formed on the substrate. A diffusion preventing layer(22) is formed on the photosensitive layer and the insulation layer. A seed layer(23) is formed on the diffusion preventing layer.

Description

Method for manufacturing thin film type thermoelectric module and laminated semiconductor chip package using the same {METHOD FOR MANUFACTURING THE THIN FILM THERMOELECTRIC MODULE AND MULTI-CHIP PACHAGE USING THE SAME}

The present invention relates to a method for manufacturing a thin film type thermoelectric module using a wafer for a semiconductor, and in particular, a method for manufacturing a thin film type thermoelectric module for solving heat dissipation problems of silicon-based semiconductor chips used in a multilayer semiconductor chip package. It is about.

Maximization of space utilization due to high density integrated arrangement of various semiconductor chips occupies an important position in the semiconductor related art. This high density integrated arrangement was initially driven in the art through the miniaturization of semiconductor chips mainly due to the development of nano processes.

Meanwhile, a technology for achieving high density integration within a limited area through stacking arrangements of semiconductor chips has emerged (multi-chip package), and a technology for forming holes between semiconductor chips stacked up and down so as to be connected to each other (Through Silicon Via, TSV). ) Was developed.

In such a stacking technique of semiconductor chips, a challenge is to solve the heat generated in each semiconductor chip. That is, the heat generation of the semiconductor chip has always been a problem due to factors such as low power consumption and an increase in the frequency of the operating signal despite efforts to reduce the resistance element.

In particular, since the heat generated from each of the semiconductor chips, which are formed in a plurality of layers and located close to each other, is accumulated between the stacked layers, the performance of the semiconductor chips is reduced or the problem of damage is caused.

As a technique for solving the heat generation problem, there is a cooling technique using a thermoelectric element.

Thermoelectric element (thermoelectric element) is originally defined as a generic name of a device using a variety of effects represented by the interaction of heat and electricity, the device using the Peltier effect which is a phenomenon that the absorption (or generation) of heat caused by the current in the present invention It means by limiting the phosphorus Peltier element.

In order to construct a thermoelectric device using the Peltier effect, a plurality of hetero semiconductors made of bismuth tellurium or the like having different electric conduction methods are alternately arranged vertically in an up and down direction, and the adjacent semiconductors are electrically connected in series. This is followed by supplying a direct current to obtain an endothermic and exothermic reaction.

The thermoelectric element is capable of switching the endothermic heat generation in accordance with the current direction, and the endothermic heat generation amount is adjusted in accordance with the amount of current, so that the thermoelectric element is applied to the manufacture of a precision refrigerator or a small temperature chamber near room temperature.

Therefore, the application of the thermoelectric device technology to the laminated semiconductor chip package can be considered and FIG. 1 shows a thin film type thermoelectric module manufactured through a semiconductor process according to the technology disclosed in Korean Patent Registration No. 10-0819852.

However, in this case, the thickness of the thermoelectric module is increased by adding the thickness of the insulating layer 1 and the N-type semiconductor (or P-type semiconductor) 2 to the silicon substrate 10, so that it is suitable for a multilayer semiconductor chip package requiring compactness. There is a problem that can not.

Therefore, the thin film type thermoelectric module which can prevent the performance degradation or damage of the semiconductor chip by discharging heat generated from each semiconductor chip in a compact configuration suitable for being interposed between the semiconductor chips stacked up and down in the stacked semiconductor chip package. There is a need for a method of preparation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a thin film type thermoelectric module that can prevent the performance degradation or damage of a semiconductor chip by discharging heat generated from each semiconductor chip in a compact configuration suitable for use in a laminated semiconductor chip package. do.

Another object of the present invention to provide a laminated semiconductor chip package using a thin film thermoelectric module manufactured by the above manufacturing method.

A method of manufacturing a thin film type thermoelectric module according to an aspect of the present invention is a method of manufacturing a thin film type thermoelectric module using a semiconductor process, the method comprising: (a) P-type semiconductor inside a silicon substrate at a predetermined interval through an upper surface of a silicon substrate; Mounting, (b) mounting an N-type semiconductor at regular intervals between the adjacent P-type semiconductors through a lower surface of the silicon substrate, and (c) the P and N-type semiconductors on the upper and lower surfaces of the silicon substrate. And forming an electrode for electrically connecting neighboring P and N-type semiconductors to each other.

In the manufacturing method of the thin film type thermoelectric module, the step of mounting the P-type semiconductor, (a-1) forming a photosensitive resin layer 15 by coating a photosensitive resin (Phtoresist) on the upper surface of the silicon substrate, ( a-2) arranging a perforated mask according to the position where the P-type semiconductor is to be mounted on the photosensitive resin layer, and irradiating ultraviolet rays to remove a portion of the photosensitive resin layer exposed to ultraviolet rays, (a -3) etching the silicon substrate exposed through the removed photosensitive resin layer to form a P-type semiconductor site, (a-4) forming an insulating layer on the P-type semiconductor site, (a-5) the After removing the photosensitive resin layer from the upper surface of the silicon substrate may include depositing a P-type semiconductor on the P-type semiconductor site.

In the manufacturing method of the thin-film thermoelectric module, the step of mounting the N-type semiconductor, (b-1) forming a photosensitive resin layer by coating a photosensitive resin on the lower surface of the silicon substrate, (b-2) the photosensitive Arranging a mask in which intermediate positions of neighboring P-type semiconductors are perforated on the resin layer, and irradiating ultraviolet rays to remove portions of the photosensitive resin layer exposed to ultraviolet rays, (b-3) through the removed photosensitive resin layer Etching the exposed silicon substrate to form an N-type semiconductor site, (b-4) forming an insulating layer on the N-type semiconductor site, (b-5) removing the photosensitive resin layer from the bottom surface of the silicon substrate And then depositing an N-type semiconductor on the N-type semiconductor site.

In the method of manufacturing the thin film type thermoelectric module, the forming of the P-type semiconductor site and the forming of the N-type semiconductor site may be performed through a deep reactive ion etching method.

In the method of manufacturing the thin film type thermoelectric module, the forming of the P-type semiconductor site and the forming of the N-type semiconductor site may be performed by wet etching.

The method of manufacturing the thin film type thermoelectric module may further include forming a seed layer before the forming of the P-type semiconductor site and the forming of the N-type semiconductor site.

In the method of manufacturing the thin film type thermoelectric module, the depositing of the P-type semiconductor and the depositing of the N-type semiconductor may be performed through electroplating.

In the method of manufacturing the thin film type thermoelectric module, depositing the P-type semiconductor and depositing the N-type semiconductor may be performed through a metal organic chemical vapor deposition (MOCVD) method.

In the method of manufacturing the thin film type thermoelectric module, the step of forming the electrode may include: (c-1) the silicon substrate such that the P-type semiconductor and the N-type semiconductor deposited inside the silicon substrate are exposed on the surface of the silicon substrate. Polishing the upper and lower surfaces, (c-2) exposing P-type semiconductors and N-type semiconductors to be paired on the upper surface of the silicon substrate by using a mask, and P-type semiconductors and N-type semiconductors on portions exposed from the mask; (C-3) exposing the P-type semiconductor and the N-type semiconductor in pairs with the upper surface on the lower surface of the silicon substrate using a mask, and forming a P-type semiconductor on the exposed portion of the mask. And forming an electrode connecting the N-type semiconductor to the P-type semiconductor and the N-type semiconductor as a whole.

In a multilayer semiconductor chip package according to an aspect of the present invention, a thin film type thermoelectric module manufactured using one of the above methods is inserted between semiconductor modules.

The stacked semiconductor chip package may further include a dummy module used as a heat discharge passage.

The multilayer semiconductor chip package may be connected between thermal modules using thermal interface materials.

According to the manufacturing method of the thin film type thermoelectric module of the present invention, the thin film type thermoelectric which can prevent the performance degradation or damage of the semiconductor chip by discharging the heat generated from each semiconductor chip in a compact configuration suitable for use in the laminated semiconductor chip package A module and a multilayer semiconductor chip package using the same can be manufactured.

The above-described features and effects of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, and thus, those skilled in the art to which the present invention pertains may easily implement the technical idea of the present invention. Could be. As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosure, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention relates to a method of manufacturing a thin film thermoelectric module in which a P-type semiconductor pattern and an N-type semiconductor pattern connected in a π-type are connected in series. FIGS. 2 to 4 are sequential process cross-sectional views showing an embodiment of the present invention.

First, the step of mounting the P-type semiconductor inside the silicon substrate through the upper surface of the silicon substrate will be described in detail with reference to FIGS. 2A to 2H.

First, as shown in FIG. 2A, a photoresist is coated on the top surface 11 of the silicon substrate 10 to form the photoresist layer 15. Here, the silicon substrate 10 uses, for example, a silicon wafer having a thickness of 550 µm.

In addition, the photosensitive resin layer 15 may be formed through a prebake process after depositing by spin coating.

Next, the photosensitive resin layer 15 exposed to the ultraviolet light 17 is arranged by arranging a mask 16 on which the P-type semiconductor is mounted on the photosensitive resin layer 15 and irradiating the ultraviolet light 17. Remove

Accordingly, the position where the P-type semiconductor is mounted in the silicon substrate 10 is removed, and the photosensitive resin layer 15 remains only in the remaining portion, thereby leaving the state of FIG. 2B.

Next, the exposed silicon substrate 10 is etched to form the P-type semiconductor site 20. As the etching method, for example, a deep reactive ion etching method capable of etching to a deep portion of the silicon substrate 10 is used.

Accordingly, the P-type semiconductor sites 20 are formed at regular intervals from the silicon upper surface 11 into the silicon to be in the state of FIG. 2C.

In this state, the insulating layer 21 is formed on the substrate. The insulating layer 21 may use a silicon oxide film (SiO ₂ ) formed through a low temperature process such as sputtering. As a result, the insulating layer 21 is formed on the photosensitive resin layer 15 and the P-type semiconductor seat 20 that remain without being removed, thereby bringing the state of FIG. 2D.

Next, a diffusion barrier layer 22 is formed on the insulating layer 21 to prevent diffusion between the P-type semiconductor and silicon. The diffusion barrier layer 22 may be formed of, for example, tinite (TiN) or tantalum (Ta) using a sputtering process.

As a result, a diffusion barrier layer 22 is formed on the photosensitive resin layer 15 and the insulating layer 21 which remain unremoved, thereby bringing the state of FIG.

The insulating layer 21 and the diffusion barrier layer 22 serve as a diffusion barrier to prevent the P-type semiconductor and the silicon substrate 10 deposited during the annealing process from being fused.

Next, a seed layer 23 is deposited. As the seed layer 23, copper (Cu) or gold (Au) is used, for example. As a result, the seed layer 23 is laminated on the diffusion barrier layer 22 to form the state of FIG. 2F.

The seed layer 23 serves to assist the P-type semiconductor to be smoothly and quickly deposited on the P-type semiconductor seat 20 in the process of depositing the P-type semiconductor to be described later.

Next, the photosensitive resin layer 15 is removed. In this case, when the photosensitive resin layer 15 is removed, the insulating layer 21, the diffusion barrier layer 22, and the seed layer 23 that are stacked on the photosensitive resin layer 15 are also removed to form the state of FIG. 2G. .

At this time, the aspect ratio of the width and depth of the P-type semiconductor site 20 should be 1:10 or less, preferably 1: 5 or less. This is for the P-type semiconductor to be stably formed to the deep portion of the P-type semiconductor site.

Next, the P-type semiconductor 25 is deposited on the P-type semiconductor site 20. The deposition method may use, for example, sputtering or evaporating, but it is preferable to use electroplating or metal organic chemical vapor deposition (MOCVD) that can stably deposit deeply. Do. In the case of using the MOCVD method, the above-described process of depositing the seed layer 23 can be omitted.

As a result, the P-type semiconductor 25 is stacked on the P-type semiconductor seat 20, and the stacked portion protrudes convexly to the upper surface 11 of the silicon substrate 10 to have a state of FIG. 2H.

Next, the convexly protruding portions of the deposited P-type semiconductor 25 are removed to be flat so as to substantially coincide with the top surface 11 of the silicon substrate 10. The planarization process is performed by, for example, chemical mechanical polishing (CMP), thereby bringing the state of FIG. 2I.

According to the above process, the step of mounting the P-type semiconductor 25 inside the silicon substrate 10 through the upper surface 11 of the silicon substrate 10 is completed.

Next, the step of mounting the N-type semiconductor inside the silicon substrate 10 through the lower surface 12 of the silicon substrate 10 will be described in detail with reference to FIGS. 3A to 3H. The overall process is the same as in the case of mounting the P-type semiconductor 25.

First, as shown in FIG. 3A, the top surface 11 of the silicon substrate 10 is placed downward and the bottom surface 12 of the silicon substrate 10 is positioned upward, and then the bottom surface 12 of the silicon substrate 10 is placed on the bottom surface 12 of the silicon substrate 10. A photoresist is coated to form the photoresist layer 15.

Similar to the upper surface 11, the photosensitive resin layer 15 may be formed through a prebake process after depositing by spin coating.

Next, the mask 16 having the perforated position at which the N-type semiconductor is mounted on the photosensitive resin layer 15 is arranged, irradiated with ultraviolet rays 17, and then the photosensitive resin layer 15 exposed to the ultraviolet rays 17 is disposed. Remove At this time, the position where the N-type semiconductor is mounted is a portion in which the P-type semiconductor 25 is mounted.

Accordingly, the photosensitive resin layer 15 is removed in the portion where the N-type semiconductor is to be mounted in the silicon substrate 10, and the photosensitive resin layer 15 remains only in the remaining portion, thereby leaving the state of FIG. 3B.

Next, the exposed silicon substrate 10 is etched to form an N-type semiconductor site 30. As the etching method, for example, a deep reactive ion etching technique capable of etching to a deep portion of the silicon substrate 10 is used.

Accordingly, the N-type semiconductor seat 30 is formed at regular intervals between the P-type semiconductor seat 20 from the lower surface 12 of the silicon substrate 10 to the inside of the silicon substrate 10 to be in the state of FIG. 3C.

In this state, the insulating layer 31 is formed on the substrate. The insulating layer 31 may use a silicon oxide film (SiO ₂ ) formed through a low temperature process such as sputtering. Accordingly, the insulating layer 31 is formed on the photosensitive resin layer 15 and the N-type semiconductor seat 30 that remain without being removed, thereby bringing the state of FIG. 3D.

Next, a diffusion barrier layer 32 is formed on the insulating layer 31 to prevent diffusion between the N-type semiconductor and silicon described later. The diffusion barrier layer 32 may be formed of, for example, tinite (TiN) or tantalum (Ta) using a sputtering process.

As a result, a diffusion barrier layer 32 is formed on the photosensitive resin layer 15 and the insulating layer 31 which remain unremoved, thereby bringing the state of FIG. 3E.

The insulating layer 31 and the diffusion barrier layer 32 serve as a diffusion barrier to prevent the N-type semiconductor and the silicon substrate 10 deposited during the annealing process from being fused.

Next, a seed layer 33 is deposited. As the seed layer 33, copper (Cu) or gold (Au) is used, for example. Accordingly, the seed layer 33 is laminated on the diffusion barrier layer 32 to form the state of FIG. 3F.

The seed layer 33 serves to assist the N-type semiconductor to be smoothly and quickly deposited on the N-type semiconductor site 30 in the process of depositing the N-type semiconductor to be described later.

Next, the photosensitive resin layer 15 is removed. In this case, when the photosensitive resin layer 15 is removed, the insulating layer 31, the diffusion barrier layer 32, and the seed layer 33 that are stacked on the photosensitive resin layer 15 are also removed to form the state of FIG. 3G. .

In this case, in order to stably form the N-type semiconductor, an aspect ratio of the width and depth of the N-type semiconductor site 30 is 1:10 or less and preferably 1: 5 or less.

Next, the N-type semiconductor 35 is deposited on the N-type semiconductor site 30. The deposition method may use sputtering or evaporating, but it is preferable to use electroplating or metal organic chemical vapor deposition (MOCVD), which can stably deposit deeply. In the case of using the MOCVD method, the above-described process of depositing the seed layer 33 can be omitted.

Accordingly, the N-type semiconductor 35 is stacked on the N-type semiconductor seat 30 and a part of the stacked portion of the N-type semiconductor 35 protrudes convexly to the lower surface 12 of the silicon substrate 10. It becomes a state.

Next, the convexly protruding portion of the deposited N-type semiconductor 35 is removed to be flat so as to substantially coincide with the bottom surface 12 of the silicon substrate 10. The planarization process is performed by, for example, chemical mechanical polishing (CMP), thus bringing the state of FIG. 3I. At this time, a part of the P-type semiconductor 25 is also polished.

According to the above process, the step of mounting the N-type semiconductor 35 inside the silicon substrate 10 through the lower surface 12 of the silicon substrate 10 is completed.

Next, a method of forming an electrode on the silicon substrate 10 on which the P-type semiconductor 25 and the N-type semiconductor 35 are mounted will be described in detail with reference to FIGS. 4A to 4E.

First, the upper surface 11 and the lower surface 12 of the silicon substrate 10 on which the P-type semiconductor 25 and the N-type semiconductor 35 are mounted are planarized to deposit P in the silicon substrate 10. The type semiconductor 25 and the N type semiconductor 35 are exposed on both surfaces of the silicon substrate 10.

The planarization process is performed by, for example, chemical mechanical polishing (CMP), whereby a portion of the thermal thin film of the P-type semiconductor 25 and the N-type semiconductor 35 is polished to a state of FIG. 4A.

Next, as shown in FIG. 4B, the P-type semiconductor 25 and the N-type semiconductor 35 are exposed in pairs on the upper surface 11 of the silicon substrate 10 using a hard mask 18. As shown in FIG. 4C, an electrode layer 40 connecting the P-type semiconductor 25 and the N-type semiconductor 35 is formed in the portion exposed from the hard mask 18.

At this time, the formation of the electrode layer 40 is performed by, for example, sputtering or evaporating, and the electrode layer 40 is formed of gold (Au), platinum (Pt), and copper having excellent thermal conductivity and electrical conductivity. It is preferable to use (Cu) and aluminum (Al).

Next, as shown in FIG. 4D, the P-type semiconductor 25 and the N-type semiconductor 35 are paired on the lower surface 12 of the silicon substrate 10 alternately with the upper surface 11 by using the hard mask 18. The P-type semiconductor 25 and the N-type semiconductor are formed by exposing the electrode layer 40 connecting the P-type semiconductor 25 and the N-type semiconductor 35 to the portion exposed from the hard mask 18 as shown in FIG. 4E. Let (35) be connected in series as a whole.

At this time, the formation of the electrode layer 40 is performed by, for example, sputtering or evaporating, and the electrode layer 40 is formed of gold (Au), platinum (Pt), and copper having excellent thermal conductivity and electrical conductivity. It is preferable to use (Cu) and aluminum (Al).

By performing the above process, a thin film type thermoelectric module according to an embodiment of the present invention is completed. 4E shows a completed thin film thermoelectric module.

In the above description, the N-type semiconductor 35 is deposited after the P-type semiconductor 25 is deposited. However, the present invention is not limited to the above-described procedure. ) May be deposited.

In addition, although the planarization process is performed after the deposition of the P-type semiconductor 25 and the deposition of the N-type semiconductor 35, this may be omitted.

In the above description, the depth ion ion etching method is used as an etching method for forming the P-type semiconductor site and the N-type semiconductor site, but the wet etching method may be used.

When the wet etching method is used, it is possible to form a P-type semiconductor site and an N-type semiconductor site in a trapezoidal shape, so that deposition of P-type semiconductors and N-type semiconductors can be more stably deposited to deep portions. 5 shows a thin film thermoelectric module using the wet etching method.

Next, an operation relationship of a multilayer semiconductor chip package using a thin film thermoelectric module manufactured according to an exemplary embodiment of the present invention will be described.

6 is a cross-sectional view illustrating a multilayer semiconductor chip package using a thermoelectric module according to an embodiment of the present invention.

Referring to FIG. 6, the multilayer semiconductor chip package 50 may include a first semiconductor module 51, a first thermoelectric module 52, a dummy module 53, a second thermoelectric module 54, and a second semiconductor from above. Modules 55 are stacked. The dummy module may be formed of a thin film of copper (Cu) or platinum (Pt), which has a good thermal conductivity.

When a voltage is applied to the stacked semiconductor chip package 50, current flows through the thermoelectric modules 52 and 54, and heat is generated on one side of the thermoelectric modules 52 and 54 by the Peltier effect, and endothermic heat is generated on the other side.

The first thermoelectric module 52 stacked on the upper portion of the stacked semiconductor chip package 50 connects the electrodes such that an upper side thereof has a heat absorbing portion and a lower side thereof generates a heat generating portion. Since the heat absorbing portion and the heat generating portion may vary depending on the connection of the electrodes, the electrodes are connected to match the electrode.

Since the movement of heat is the same as the direction of movement of electrons or holes, when the positive electrode is connected to the P-type semiconductor and the negative electrode is connected to the N-type semiconductor in the first thermoelectric module 52, the first thermoelectric module 52 is connected. The upper side becomes the heat absorbing portion and the lower side becomes the heat generating portion.

In the above configuration, the heat absorbing portion of the first thermoelectric module 52 absorbs heat generated from the chip 56 mounted on the first semiconductor module 51 through a post 57 made of copper, thereby generating heat. The heat transferred to the unit is transferred to the outside of the stacked semiconductor chip package 50 through the dummy module 53.

On the other hand, the second thermoelectric module 54 stacked on the lower side connects the electrodes such that the upper side is the heat generating portion and the lower side is the heat absorbing portion. The electrode to be connected is opposite to the first thermoelectric module 52 such that a negative electrode is connected to the P-type semiconductor and a positive electrode is connected to the N-type semiconductor.

In the heat absorbing part of the second thin film type thermoelectric module, heat generated from the chip 56 mounted on the second semiconductor module 55 is absorbed through the posts 57 made of copper and transferred to the heat generating part, and the transferred heat is a dummy module ( 53 is discharged to the outside of the stacked semiconductor chip package 50 through.

In addition, the connection between each module, that is, the connection between the semiconductor module and the thermoelectric module, the thermoelectric module and the dummy module may be connected using thermal interface materials having good thermal conductivity and bonding strength. As the thermal interface material, for example, a thermal pad or a thermal grease may be used.

As a result, the heat conduction between the modules is more smoothly, reducing the heat loss and making the solid bonding between the modules possible, thereby producing a multilayer semiconductor chip package having excellent performance.

In this way, it is possible to efficiently discharge the heat generated in each semiconductor chip 56 of the laminated semiconductor chip package 50 in a compact configuration.

In the above, as an example of the present invention, a stacked semiconductor chip package in which two semiconductor modules are stacked is exemplified, but the present invention may be used for efficient heat dissipation of a stacked semiconductor chip package in which more semiconductor modules are stacked according to the above description.

In addition, in the above-described example, the thin film type thermoelectric module manufactured according to an exemplary embodiment of the present invention has been described for use in a multilayer semiconductor chip package. However, the present invention is not limited thereto and may be used in a general semiconductor circuit board such as a small LED substrate. Will be self explanatory.

In the detailed description of the present invention described above with reference to the preferred embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary skill in the art will be described in the claims to be described later And it will be understood that various modifications and changes of the present invention can be made without departing from the scope of the art.

1 is a cross-sectional view of a typical thin-film thermoelectric module

2A to 2I are cross-sectional views illustrating a process of mounting a P-type semiconductor of a thin film thermoelectric module according to an exemplary embodiment of the present invention.

3A to 3I are cross-sectional views illustrating a process of mounting an N-type semiconductor of a thin film thermoelectric module according to an embodiment of the present invention.

4A to 4E are cross-sectional views illustrating a process of forming an electrode of a thin film thermoelectric module according to an exemplary embodiment of the present invention.

5A is a cross-sectional view showing a thin film thermoelectric module after the process of mounting the P-type semiconductor and the N-type semiconductor using the wet etching method, and FIG. 5B is a cross-sectional view showing a thin film thermoelectric module manufactured using the wet etching method.

6 is a cross-sectional view illustrating a multilayer semiconductor chip package using a thermoelectric module according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10: silicon substrate 21, 31: insulating layer

22, 32: diffusion barrier layer 23, 33: seeder

25: P-type semiconductor 35: N-type semiconductor

50: stacked semiconductor chip package

Claims (12)

As a method of manufacturing a thin film type thermoelectric module using a semiconductor process, (a) mounting a P-type semiconductor at regular intervals inside the silicon substrate through an upper surface of the silicon substrate; (b) mounting an N-type semiconductor at regular intervals between the adjacent P-type semiconductors through a lower surface of the silicon substrate; (c) exposing the P and N-type semiconductors on the upper and lower surfaces of the silicon substrate, and forming electrodes to electrically connect neighboring P and N-type semiconductors to each other. Method of manufacturing a thin-film thermoelectric module, characterized in that performed. The method of claim 1, Mounting the P-type semiconductor, (a-1) forming a photosensitive resin layer 15 by coating a photoresist on a top surface of the silicon substrate (a-2) arranging a perforated mask according to the position where the P-type semiconductor is to be mounted on the photosensitive resin layer, and irradiating ultraviolet rays to remove portions of the photosensitive resin layer exposed to ultraviolet rays (A-3) etching the exposed silicon substrate through the removed photosensitive resin layer to form a P-type semiconductor site (a-4) forming an insulating layer on the P-type semiconductor site (a-5) A method of manufacturing a thin film type thermoelectric module comprising removing a photosensitive resin layer from an upper surface of the silicon substrate and depositing a P-type semiconductor on the P-type semiconductor site. The method of claim 1, Mounting the N-type semiconductor, (b-1) forming a photosensitive resin layer by coating the photosensitive resin on the lower surface of the silicon substrate (b-2) arranging a mask having a perforated intermediate position of a neighboring P-type semiconductor on the photosensitive resin layer, and irradiating ultraviolet rays to remove a portion of the photosensitive resin layer exposed to ultraviolet rays (b-3) etching the silicon substrate exposed through the removed photosensitive resin layer to form an N-type semiconductor site (b-4) forming an insulating layer on the N-type semiconductor site (b-5) removing the photosensitive resin layer from the lower surface of the silicon substrate and then depositing an N-type semiconductor on the N-type semiconductor site. The method according to claim 2 or 3, The forming of the P-type semiconductor site and the forming of the N-type semiconductor site may be performed through a deep reactive ion etching method. The method according to claim 2 or 3, Forming the P-type semiconductor site and the step of forming the N-type semiconductor site is a method of manufacturing a thin film type thermoelectric module, characterized in that the wet etching (Wet Etching) method. The method according to claim 2 or 3, And forming a seed layer on the insulating layer before performing the forming of the P-type semiconductor site and the forming of the N-type semiconductor site. The method according to claim 2 or 3, And depositing the P-type semiconductor and depositing the N-type semiconductor through electroplating. The method according to claim 2 or 3, And depositing the P-type semiconductor and depositing the N-type semiconductor through a metal organic chemical vapor deposition (MOCVD) method. The method of claim 1, Forming the electrode (c-1) polishing the upper and lower surfaces of the silicon substrate so that the P-type semiconductor and the N-type semiconductor deposited inside the silicon substrate are exposed on the surface of the silicon substrate; (c-2) exposing the P-type semiconductor and the N-type semiconductor in pairs on the upper surface of the silicon substrate using a mask, and forming an electrode connecting the P-type semiconductor and the N-type semiconductor to the exposed portion from the mask; (c-3) An electrode for exposing the P-type semiconductor and the N-type semiconductor in pairs on the lower surface of the silicon substrate alternately with the upper surface by using a mask and connecting the P-type semiconductor and the N-type semiconductor to the exposed portion from the mask; Forming a P-type semiconductor and an N-type semiconductor as a whole in series; Method of manufacturing a thin film type thermoelectric module comprising a. The multilayer semiconductor chip package of claim 1, wherein the thin film type thermoelectric module manufactured by the method of claim 1 is inserted between the semiconductor modules. The method of claim 10, Laminated semiconductor chip package, characterized in that the dummy module used as a heat discharge passage is further inserted. The method of claim 11, A laminated semiconductor chip package, characterized in that each module is connected using thermal interface materials.

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