KR101066601B1 - Method for fabricating pseudomorphic high electron mobility transistor device and power amplifier having the phemt produced by the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an amorphous high electron mobility transistor, and a power amplifier including a device manufactured thereby, comprising: forming a source and a drain on an epitaxial substrate, and removing the epitaxial substrate from a dry process and a wet method. And forming a recess region by recess etching, and forming a gate in the recess region, thereby manufacturing an amorphous high electron mobility transistor device.

Compound Semiconductor Devices, PHEMTs, Power Amplifiers, Negative Feedback Circuits

Description

FIELD OF THE INVENTION AND METHOD FOR MANUFACTURING ANYTHING HIGH-QUALITY MODULAR DEVICE DEVICE AND A POWER AMPLIFIER

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method of manufacturing an amorphous high electron mobility transistor device and a power amplifier having a device manufactured thereby.

Pseudomorphic High Electron Mobility Transistor (PHEMT), a kind of compound semiconductor device, has many layers included in the device that are very different from the lattice constant of other materials in the device, and form a channel layer due to lattice mismatch. It is common to have the property that the structure of the material to be modified. It is difficult to grow the layers on the substrate during the manufacturing process due to the stress strain due to the lattice mismatch, but the power and noise characteristics are excellent because of the high charge density and electron mobility transferred to the channel layer. Therefore, since it can operate at high frequency and the electron speed is superior to a silicon element, it is widely applied to the element of a microwave or millimeter wave band.

Since the pinch-off voltage is a negative voltage, the PHEMT device is generally operated by connecting a negative voltage power source to a gate to which a high frequency (RF) signal is input. The necessity of a circuit for generating a negative voltage increases the production cost of the chip, which is pointed out as a disadvantage compared to a heterojunction transistor using only a positive voltage power supply. In order to drive the PHEMT device with a single voltage power supply, the pinch-off voltage must be increased to apply a positive voltage of 0 volts or more to the gate to which the high frequency signal is input. There is a problem that the chip reliability is lowered due to the instability of the device coming from the gain.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems in the prior art, and an object of the present invention is to provide a method for manufacturing an amorphous high electron mobility transistor device capable of operating with a single power supply voltage and having high productivity and stability, and a device manufactured thereby. In providing a power amplifier having a.

In order to achieve the above object, the method of manufacturing an amorphous high mobility transistor device according to the present invention is characterized in that the electrical properties are improved by performing the gate recess etching in parallel with the dry etching and the wet etching. The power amplifier according to the present invention includes a device fabricated by the gate recess etching, and satisfies broadband characteristics and unconditional stability conditions by connecting a negative feedback circuit connected in series with a resistor and a capacitor in parallel with a gate and a drain. do.

According to another aspect of the present invention, there is provided a method of manufacturing an amorphous high electron mobility transistor device, including: an epi substrate; Forming a source and a drain on the epi substrate; Gate recess etching the epitaxial substrate including a dry method and a wet method to form a recess region; And forming a gate in the recess region.

In the method of this embodiment, providing the epi substrate provides a semi-insulating substrate; Forming a buffer layer on the semi-insulating substrate; Forming an active layer on the buffer layer; And mesa etching the activation layer.

In the method of the present embodiment, providing the semi-insulating substrate may include forming gallium arsenide (GaAs).

In the method of this embodiment, providing the buffer layer comprises: forming a first buffer layer comprising undoped GaAs on the semi-insulating substrate; And forming a second buffer layer including aluminum gallium arsenide (AlGaAs) / gallium arsenide (GaAs) having a superlattice structure on the first buffer layer.

In the method of this embodiment, forming the activation layer comprises: forming an electron supply layer including undoped aluminum gallium arsenide (AlGaAs) having a first bandgap on the buffer layer; A lower silicon shaping layer having a first doping concentration, a lower spacer, an undoped indium gallium arsenide (InGaAs) having a second bandgap narrower than the first bandgap, an upper spacer and the first doping concentration on the electron supply layer Forming an electron traveling layer in which the upper silicon shaping layer having a second doping concentration smaller than the doping concentration is sequentially stacked; Forming a Schottky layer including doped aluminum gallium arsenide (AlGaAs) on the electron traveling layer; And forming a cap layer including undoped gallium arsenide (GaAs) on the Schottky layer.

In the method of this embodiment, forming the source and the drain comprises depositing a source / drain metal film including gold germanium (AuGe) / nickel (Ni) / gold (Au) on the cap layer; And performing rapid thermal treatment (RTA) on the source / drain metal layer to make ohmic contact with the cap layer.

In the method of this embodiment, forming the recessed region forms a protective film including a silicon nitride film defining a gate region by exposing a portion of the cap layer; Dry etching the cap layer exposed through the gate region to expose the schottky layer; And wet etching the exposed Schottky layer.

In the method of this embodiment, the dry etching of the cap layer is performed by reactive ion etching (RIE) capable of selectively etching the gallium arsenide (GaAs) with respect to the aluminum gallium arsenide (AlGaAs). May optionally include etching.

In the method of the present embodiment, the wet etching of the Schottky layer is performed by etching the aluminum gallium arsenide (AlGaAs) by wet etching using an etchant including phosphoric acid (H ₃ PO ₄ ) and hydrogen peroxide (H ₂ O ₂ ). The wet etching may be performed while measuring the saturation current until the saturation current value reaches the target value.

In the method of this embodiment, forming the gate comprises depositing a gate metal film including titanium (Ti) / platinum (Pt) / gold (Au) in the recess region; The gate metal layer may be lifted off to make the schottky contact with the schottky layer.

A power amplifier according to an embodiment of the present invention capable of realizing the above characteristics includes forming a recess region in the epitaxial substrate by a gate recess etching including a dry method and a wet method, and forming a gate in the recess region. A plurality of amorphous high electron mobility transistor elements manufactured by a fabrication method; A gate pad electrically connected to a plurality of gates of the plurality of amorphous high electron mobility transistor elements; A source pad electrically connected to a plurality of sources of the plurality of amorphous high electron mobility transistor elements; A drain pad electrically connected to a plurality of drains of the plurality of amorphous high electron mobility transistor elements; And a negative feedback circuit connected in parallel with the gate and drain pads and having a capacitor and a resistor connected in series.

In the power amplifier of the present embodiment, the capacitor may include a metal-insulator-metal (MIM) capacitor, and the resistor may include a nickel chromium (NiCr) thin film resistor.

In the power amplifier of this embodiment, the amorphous high electron mobility transistor device includes a gate contacted with a schottky contact in a recess region in which an epitaxial substrate is selectively removed, and a source / drain in ohmic contact with the epitaxial substrate. The substrate includes an aluminum gallium arsenide (AlGaAs) layer and a gallium arsenide (GaAs) layer, wherein the recess region is a dry type capable of selectively etching the gallium arsenide (GaAs) layer with respect to the aluminum gallium arsenide (AlGaAs) layer. Etching and the aluminum gallium arsenide (AlGaAs) may be formed by a gate recess etching including a wet etching.

According to the present invention, an amorphous high mobility device (PHEMT) capable of operating with a single power source and having improved characteristics can be manufactured. In addition, by applying the PHEMT device having such excellent characteristics, it is possible to implement a power amplifier that satisfies the broadband characteristics and unconditional stability conditions.

Hereinafter, a method of manufacturing an amorphous high electron mobility transistor device according to the present invention and a power amplifier having a device manufactured thereby will be described in detail with reference to the accompanying drawings.

Advantages over the present invention and prior art will become apparent through the description and claims with reference to the accompanying drawings. In particular, the present invention is well pointed out and claimed in the claims. However, the present invention may be best understood by reference to the following detailed description in conjunction with the accompanying drawings. Like reference numerals in the drawings denote like elements throughout the various drawings.

(Example)

1A to 1G are cross-sectional views illustrating a method of manufacturing an amorphous high electron mobility transistor device according to an exemplary embodiment of the present invention. The manufacturing method described below may include a process similar to that disclosed in Korean Patent No. 10-438895 proposed by the applicant, which is incorporated herein by reference.

Referring to FIG. 1A, an epitaxial substrate 101 may be prepared. The epitaxial substrate 101 may include an active layer 160 formed on a semi-insulating substrate 110. The activation layer 160 may be formed by sequentially stacking the electron supply layer 130, the first conductive layer 140, and the second conductive layer 150. The electron supply layer 130, the first conductive layer 140, and the second conductive layer 150 may be formed using, for example, an epitaxial growth method. The buffer layer 120 may be formed between the semi-insulating substrate 110 and the activation layer 160.

The semi-insulating substrate 110 may include, for example, gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium gallium phosphide (InGaP), or aluminum gallium arsenide (AlGaAs). According to the present embodiment, the semi-insulating substrate 110 may be a gallium arsenide (GaAs) substrate.

The buffer layer 120 may include a first buffer layer 122 composed of undoped GaAs, for example, to mitigate lattice mismatch between the semi-insulating substrate 110 and the activation layer 160. Can be. The buffer layer 120 may further include a second buffer layer 124 having a barrier energy large enough to prevent the movement of electrons through the channel. The second buffer layer 124 may include aluminum gallium arsenide (AlGaAs) / gallium arsenide (GaAs) having a superlattice structure.

The electron supply layer 130 may include undoped AlGaAs having a relatively wide band gap (approximately 1.42 eV to 2.16 eV) for supplying electrons. In the electron supply layer 130 composed of undoped AlGaAs, the content of aluminum (Al) may be set lower than that of gallium (Ga), for example, about 0.3 molar ratio or less. That is, _{X in} Al _X Ga _1-X As may be 0.3 or less.

The first conductive layer 140 may include a channel layer of a double shaping structure in which a carrier (eg, an electron) runs. For example, the first conductive layer 140 may include a lower silicon shaping layer 141, a lower spacer 143, an electron traveling layer 145, an upper spacer 147, and an upper silicon shaping layer 149. Can be.

For example, the lower silicon shaping layer 141 may be formed by delta doping silicon after forming the electron supply layer 130. The upper silicon shaping layer 149 may be formed by delta doping silicon after forming the upper spacers 147. The lower silicon shaping layer 141 may have a higher doping concentration than the upper silicon shaping layer 149. For example, the doping concentration of the lower silicon shaping layer 141 may be approximately 1.5 × 10 ¹² cm ⁻² to 2.5 × 10 ¹² cm ⁻² , and the doping concentration of the upper silicon shaping layer 149 is approximately 0.7 × 10 ^12. Cm ⁻² to 1.5 × 10 ¹² cm ⁻² . As described above, the double shaping structure including the upper and lower silicon shapings 141 and 149 may have a higher current density than the single silicon shaping structure. The lower spacer 143 may include, for example, undoped InGaAs. The same may be true of the upper spacer 147.

The electron running layer 145 may include, for example, undoped InGaAs having a narrow band gap (approximately 0.4 eV to 1.4 eV) of a lattice-matched or pseudomorphic structure. In the electron driving layer 145 including undoped InGaAs, the content of indium (In) is lower than that of gallium (Ga), for example, about 0.25 molar ratio or less to increase carrier confinement ability. Can be set. That is, _X may be 0.25 or less in In _X Ga _1-X As.

The second conductive layer 160 may include a schottky layer 152 and a cap layer 154. For example, the schottky layer 152 may include aluminum gallium arsenide (lowly doped AlGaAa) doped with a low concentration of impurities. The doping concentration of the Schottky layer 152 may be, for example, 1.0 × 10 ¹⁶ cm ⁻³ to 1.0 × 10 ¹⁷ cm ⁻³ . Since aluminum gallium arsenide (AlGaAs) constituting the schottky layer 152 has a large band gap as described above, electrons may be limited to the electron traveling layer 145. Cap layer 154 may include undoped GaAs.

Referring to FIG. 1B, the activation layer 160 is etched for device isolation. For example, the electron supply layer 130 may be partially removed from the cap layer 154 to be mesa-etched to have a structure having an inclined wall that is obliquely inclined. In this case, a portion of the second buffer layer 124 may be etched. Mesa etching may use an etchant containing sulfuric acid (H ₂ SO ₄ ) or phosphoric acid (H ₃ PO ₄ ), hydrogen peroxide (H ₂ O ₂ ), ultrapure water (H ₂ O).

Referring to FIG. 1C, a metal film is formed on the cap layer 154 and then heat-treated to form a source 172 and a drain 174 in ohmic contact with the cap layer 154. For example, gold germanium (AuGe) / nickel (Ni) / gold (Au) may be sequentially deposited on the cap layer 154, and heat treatment using rapid thermal treatment (RTA) may be adopted. Typically, in order to lower ohmic contact resistance, the cap layer 154 may be formed of gallium arsenide (GaAs) doped with a high concentration of impurities. However, according to the exemplary embodiment of the present invention, the undoped GaAs is epitaxially grown to form the cap layer 154, thereby maintaining a low ohmic contact resistance while reducing the knee voltage and reducing the breakdown voltage. It can be increased to improve the power characteristics.

Referring to FIG. 1D, a portion of the cap layer 154 is exposed to form a passivation layer 176 defining the gate region 178. For example, a silicon nitride film (eg, SiN, Si ₃ N ₄ ) is deposited on the cap layer 154, and a positive resist is applied on the silicon nitride film. Thereafter, a portion of the silicon nitride film may be removed by dry etching to form a protective film 176 having a pattern defining the gate region 178.

Referring to FIG. 1E, the cap layer 154 is recess etched to form a recess region 180 exposing the schottky layer 152. Such gate recess etching is known to be an important process that determines the characteristics of the device. In some embodiments, the gate recess etch may include dry etching and wet etching.

For example, a negative resist is applied on the passivation layer 176 and a portion of the cap layer 154 is removed by dry etching. The negative resist may include a pattern having a length greater than that of the gate described later, for example, a pattern having a length of about 0.4 to 1 μm greater than that of the gate. Dry etching at this time is reactive ion etching (RIE) capable of selectively etching gallium arsenide (GaAs) constituting the cap layer 154 and aluminum gallium arsenide (AlGaAs) constituting the cap layer 154 and the Schottky layer 152. Can be adopted. According to the dry etching (eg, RIE), the etching rate with respect to gallium arsenide (GaAs) is fast while the etching rate with respect to aluminum gallium arsenide (AlGaAs) is low, thereby enabling selective etching of the cap layer 154.

Subsequently, aluminum gallium arsenide (AlGaAs) constituting the schottky layer 152 may be wet etched. For example, a wet etching method using an etchant obtained by diluting a solution having a ratio of phosphoric acid (H ₃ PO ₄ ) and hydrogen peroxide (H ₂ O ₂ ) 6: 1 to 2: 1 in water (ultra pure water) may be adopted. . At this time, the wet etching may proceed until the saturation current value reaches the target value while measuring the saturation current. By the gate recess etching process in which the dry etching and the wet etching are performed in parallel, the electrical characteristics of the device may be improved as described below with reference to FIGS. 2A and 2B.

Referring to FIG. 1F, a metal film is deposited to form a gate 180 in schottky contact with the schottky layer 152. For example, the Schottky gate 180 may be formed by depositing a metal film including titanium (Ti) / platinum (Pt) / gold (Au) and then lifting it off. In order to enable fast operation of the device and to realize high gain and low noise, the gate 180 may have a T-shaped structure having a large head.

According to the present embodiment including the series of processes described above, AlGaAs having a wide bandgap and InGaAs having a narrow bandgap form a heterojunction structure and are trapped in a quantum well formed in InGaAs having a narrow bandgap. By using a high mobility of electrons, an amorphous high electron mobility transistor device (PHEMT) 100 capable of high speed operation may be implemented. In addition, as described with reference to FIG. 1E, the gate recess etching process may be performed by dry etching and wet etching at the same time, thereby improving electrical characteristics of the device. As an example for observing the improvement of the electrical characteristics, after fabricating a device having a gate length of about 0.8 μm, a unit gate width of about 150 μm, and a total gate area of about 300 μm, the uniformity of the device characteristics is examined. It may be as described below with reference to 2b.

Referring to FIG. 1G, a metal film 190 may be formed by selectively plating a metal on the source 172 and the drain 174. The metal film 190 may be formed by, for example, plating gold (Au). In particular, by forming the metal film 190 in the form of an air bridge having an arch shape, for example, a plurality of sources 172 and drains 174 between the plurality of PHEMT elements 100 as described below with reference to FIG. 3. ) Can be manufactured with a power amplifier (electrical) electrically connected.

2A and 2B are plan views illustrating pinch-off voltage, transfer conductance, and saturation current values of a PHEMT device manufactured by a method according to an embodiment of the present invention and a method different from the present embodiment, for each position where elements are formed on a substrate. to be.

Referring to FIG. 2A, the average and standard deviation of the pinch-off voltage in the device manufactured by the gate recess etching process in which dry etching and wet etching are performed in accordance with an embodiment of the present invention are -0.818 (V) and 0.0067, respectively. The mean and standard deviation of the transfer conductance are 269.2 (mS / mm) and 10.0, respectively, and the mean and standard deviation of the saturation current are 21.19 (mA) and 2.12, respectively. Here, the pinch-off voltage may be about -1 volt to drive the device with a positive voltage. The uniformity of pinch-off voltage, transfer conductance, and saturation current is -8.130, 3.7, and 9.98, respectively.

Referring to FIG. 2B, in the device fabricated by the gate recess etching process employing wet etching, unlike in the embodiment of the present invention, the average and standard deviation of the pinch-off voltage are -0.818 (V) and 0.238, respectively. The mean and standard deviation are 214.3 (mS / mm) and 35.2, respectively, and the mean and standard deviation of saturation current are 18.51 (mA) and 7.06, respectively. Here, too, the pinch-off voltage may be about -1 volt to drive the device with a positive voltage. The uniformity of the pinch-off voltage, transfer conductance, and saturation current is -27.026, 16.4, and 38.13, respectively.

Comparing FIG. 2A with 2B, the uniformity of the device fabricated in the gate recess etching process in which the dry method and the wet method are combined by the embodiment of the present invention is about compared to the uniformity of the device fabricated by the gate recess etching process by the wet method. It can be seen that the improvement is more than three times.

Referring to FIG. 1G, a metal film 190 may be formed by selectively plating a metal on the source 172 and the drain 174. The metal film 190 may be formed by, for example, plating gold (Au). In particular, by forming the metal layer 190 in the form of an air bridge having an arch shape, for example, as shown in FIG. 3, a plurality of sources 172 and a drain 174 between the plurality of PHEMT elements 100 may be formed. Electrically connected power amplifiers can be implemented.

3 is a plan view showing a power amplifier to which a PHEMT device manufactured by the method of the embodiment of the present invention is applied.

Referring to FIG. 3, the power amplifier 1000 according to the present embodiment is electrically connected to a gate pad 1100 electrically connected to a gate 180, a source pad 1200 electrically connected to a source 172, and a drain 174. The connected drain pad 1300 may be included. The power amplifier 1000 may further include a negative feedback circuit 1600 in which the capacitor 1400 and the resistor 1500 are connected in series. The capacitor 1400 may include, for example, a metal-insulator-metal (MIM) capacitor, and the resistor 1500 may include a nickel chromium (NiCr) thin film resistor. The negative feedback circuit 1600 may be connected in parallel to the gate 180 and the drain 174. The power amplifier 1000 including the negative feedback circuit 1600 may satisfy wideband characteristics and unconditionally stable conditions as shown in FIG. 4A. Therefore, the power amplifier 1000 of the present embodiment may not have an unstable characteristic in which oscillation occurs during operation.

4A is a graph showing the stability of the power amplifier after applying the negative feedback circuit, Figure 4B is a graph showing the stability of the power amplifier before applying the negative feedback circuit.

Comparing FIG. 4A with 4B, if the negative feedback circuit 1600 is applied to the power amplifier 1000 (FIG. 4A), the stability factor K in all frequency bands is 1 compared to otherwise (FIG. 4B). Larger and more stable measurement (stability measurement B) is less than 0 it can be seen that satisfactory unconditional stability conditions (K> 1, B <0).

The PHEMT device 100 of the present embodiment can be applied to Korean Patent No. 10-474567 proposed by the applicant, which is incorporated herein by reference.

The detailed description of the invention is not intended to limit the invention to the disclosed embodiments, but may be used in various other combinations, modifications, and environments without departing from the spirit of the invention. The appended claims should be construed to include other embodiments.

The high electron mobility transistor device which can be manufactured by the present invention can be applied to a wireless communication device of a high frequency band such as Bluetooth, WLAN, etc., and can be applied to a power amplifier.

1A to 1G are cross-sectional views illustrating a method of manufacturing an amorphous high electron mobility transistor device according to an exemplary embodiment of the present invention.

2A is a plan view showing the characteristics of an amorphous high electron mobility transistor device manufactured according to an embodiment of the present invention.

Figure 2b is a plan view showing the characteristics of the amorphous high electron mobility transistor device manufactured differently from the embodiment of the present invention.

Figure 3 is a block diagram showing a power amplifier using an amorphous high electron mobility transistor element that can be implemented by the manufacturing method according to an embodiment of the present invention.

4A is a graph showing the stability of a power amplifier after applying a negative feedback circuit.

4B is a graph showing the stability of the power amplifier before applying the negative feedback circuit.

Claims (10)

Providing an epi substrate; Forming a source and a drain on the epi substrate; Gate recess etching the epitaxial substrate including a dry method and a wet method to form a recess region; And Forming a gate in the recess region; A method of manufacturing an amorphous high electron mobility transistor device comprising. The method of claim 1, Providing the epi substrate is: Providing a semi-insulating gallium arsenide (GaAs) substrate; Forming a buffer layer on the semi-insulating substrate; Forming an activation layer on the buffer layer; And Mesa etching the activation layer; A method of manufacturing an amorphous high electron mobility transistor device comprising. The method of claim 2, Providing the buffer layer is: Forming a first buffer layer comprising undoped GaAs on the semi-insulating substrate; And Forming a second buffer layer including a superlattice aluminum gallium arsenide (AlGaAs) / gallium arsenide (GaAs) on the first buffer layer; A method of manufacturing an amorphous high electron mobility transistor device comprising. The method of claim 2, Forming the activation layer is: Forming an electron supply layer including undoped aluminum gallium arsenide (AlGaAs) having a first band gap on the buffer layer; A lower silicon shaping layer having a first doping concentration, a lower spacer, an undoped indium gallium arsenide (InGaAs) having a second bandgap narrower than the first bandgap, an upper spacer and the first doping concentration on the electron supply layer Forming an electron traveling layer in which the upper silicon shaping layer having a second doping concentration smaller than the doping concentration is sequentially stacked; Forming a Schottky layer including doped aluminum gallium arsenide (AlGaAs) on the electron traveling layer; And Forming a cap layer including undoped gallium arsenide (GaAs) on the Schottky layer; A method of manufacturing an amorphous high electron mobility transistor device comprising. 5. The method of claim 4, Forming the source and drain is: Depositing a source / drain metal film including gold germanium (AuGe) / nickel (Ni) / gold (Au) on the cap layer; And Rapid thermal treatment (RTA) of the source / drain metal film to ohmic contact with the cap layer: A method of manufacturing an amorphous high electron mobility transistor device comprising. 5. The method of claim 4, Forming the recessed region is: Exposing a portion of the cap layer to form a protective film including a silicon nitride film defining a gate region; Etching the cap layer exposed through the gate region by dry etching capable of selectively etching the gallium arsenide (GaAs) with respect to the aluminum gallium arsenide (AlGaAs) to expose the schottky layer; And Etching the exposed Schottky layer by wet etching; A method of manufacturing an amorphous high electron mobility transistor device comprising. The method of claim 6, Wet etching the Schottky layer is: The aluminum gallium arsenide (AlGaAs) formed on the electron transport layer is etched using an etchant containing phosphoric acid (H ₃ PO ₄ ) and hydrogen peroxide (H ₂ O ₂ ), but the saturation current value is measured while measuring the saturation current. Conducting the wet etch until a target value is reached; A method of manufacturing an amorphous high electron mobility transistor device comprising. 5. The method of claim 4, The gate is formed by: Depositing a gate metal film including titanium (Ti) / platinum (Pt) / gold (Au) in the recess region; And Lift-off the gate metal film to make Schottky contact with the Schottky layer: A method of manufacturing an amorphous high electron mobility transistor device comprising. A plurality of amorphous high electron mobility transistor elements manufactured by the method of claim 1; A gate pad electrically connected to a plurality of gates of the plurality of amorphous high electron mobility transistor elements; A source pad electrically connected to a plurality of sources of the plurality of amorphous high electron mobility transistor elements; A drain pad electrically connected to a plurality of drains of the plurality of amorphous high electron mobility transistor elements; And A negative feedback circuit connected in parallel with the gate and drain pads, the capacitor and a resistor connected in series; Power amplifier included. 10. The method of claim 9, The capacitor comprises a metal-insulator-metal (MIM) capacitor, and the resistor comprises a nickel chromium (NiCr) thin film resistor.

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