KR101056748B1 - Semiconductor package with electromagnetic shielding means - Google Patents

Semiconductor package with electromagnetic shielding means Download PDF

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KR101056748B1
KR101056748B1 KR1020090087255A KR20090087255A KR101056748B1 KR 101056748 B1 KR101056748 B1 KR 101056748B1 KR 1020090087255 A KR1020090087255 A KR 1020090087255A KR 20090087255 A KR20090087255 A KR 20090087255A KR 101056748 B1 KR101056748 B1 KR 101056748B1
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semiconductor chip
grounding
electromagnetic
semiconductor
substrate
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KR1020090087255A
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Korean (ko)
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KR20110029541A (en
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김병진
신민철
문한주
조성환
이태용
김재윤
이상웅
소광섭
김기정
현종해
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앰코 테크놀로지 코리아 주식회사
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Abstract

본 발명은 기판 상에 적층된 반도체 칩에 연결된 전자파 접지용 와이어를 이용하여 반도체 칩에서 내부적으로 발생된 전자파를 접지시킬 수 있는 전자파 차폐수단을 갖는 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package having electromagnetic shielding means capable of grounding electromagnetic waves generated internally in a semiconductor chip by using an electromagnetic grounding wire connected to a semiconductor chip stacked on a substrate.

본 발명은 기판상에 적층된 각각의 반도체 칩과 접지용 전도성 패턴에 전자파 접지용 와이어를 연결함으로써, 반도체 칩에서 내부적으로 발생된 전자파를 접지하여 반도체 패키지에 대한 전자파 차폐효과를 증대시킬 수 있다.The present invention can increase the electromagnetic shielding effect on the semiconductor package by grounding the electromagnetic wave generated internally in the semiconductor chip by connecting the electromagnetic grounding wire to each semiconductor chip and the grounding conductive pattern stacked on the substrate.

또한, 본 발명은 전자파 접지용 와이어와 접지용 전도성 패턴 사이에 연결된 히트스프레더가 반도체 칩에서 발생된 열을 전자파 접지용 와이어로부터 전달받아 방출함으로써, 각 반도체 칩의 열을 효과적으로 분산시킬 수 있다.In addition, the present invention can effectively dissipate heat of each semiconductor chip by the heat spreader connected between the electromagnetic grounding wire and the grounding conductive pattern receives the heat generated from the semiconductor chip from the electromagnetic grounding wire.

전자파, 차폐, 접지용 전도성 패턴, 반도체 칩, 전자파접지용 와이어, 히트스프레더 Electromagnetic wave, shielding, conductive pattern for grounding, semiconductor chip, electromagnetic grounding wire, heat spreader

Description

전자파 차폐수단을 갖는 반도체 패키지{Semiconductor package device for shielding electromagnetic waves}Semiconductor package having electromagnetic shielding means

본 발명은 전자파 차폐수단을 갖는 반도체 패키지에 관한 것으로서, 더욱 상세하게는 기판 상에 적층된 반도체 칩에 연결된 전자파 접지용 와이어를 이용하여 반도체 칩에서 내부적으로 발생된 전자파를 접지시킬 수 있는 전자파 차폐수단을 갖는 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package having electromagnetic shielding means, and more particularly, electromagnetic shielding means capable of grounding electromagnetic waves generated internally in a semiconductor chip by using an electromagnetic grounding wire connected to a semiconductor chip stacked on a substrate. It relates to a semiconductor package having a.

통상적으로, 스택 패키지(Stack Package)는 복수의 반도체 칩을 적층한 패키지로서, 단순화된 공정에 의해 패키지의 제조 단가를 낮출 수 있고, 대량 생산이 가능하다.In general, a stack package is a package in which a plurality of semiconductor chips are stacked, and thus the manufacturing cost of the package can be reduced by a simplified process, and mass production is possible.

상기 스택 패키지의 한 예로 관통 실리콘 비아(Through Silicon Via : TSV)를 이용한 구조가 제안된 바 있고, 상기 관통 실리콘 비아를 이용한 스택 패키지는 웨이퍼 단계에서 각각의 반도체 칩 내에 수직방향으로 관통 실리콘 비아를 형성한 후, 이 관통 실리콘 비아를 매개로 상부와 하부 반도체 칩들간의 물리적 및 전기적 연결이 이루어지도록 한 구조이다.As an example of the stack package, a structure using a through silicon via (TSV) has been proposed, and the stack package using the through silicon via forms a through silicon via in a vertical direction in each semiconductor chip at a wafer stage. Afterwards, the through-silicon vias enable physical and electrical connections between the upper and lower semiconductor chips.

한편, 각종 전자기기의 마더보드에는 다양한 구조로 제조된 다수개의 반도체 패키지 뿐만아니라, 각종 신호 교환용 전자기기들이 한꺼번에 설치되는 바, 이러한 반도체 패키지와 기기들은 전기적인 작동중에 전자파를 발산시키는 것으로 알려져 있다.On the other hand, as well as a plurality of semiconductor packages made of various structures, as well as a variety of signal exchange electronics are installed on the motherboard of various electronic devices, such semiconductor packages and devices are known to emit electromagnetic waves during electrical operation. .

이러한 전자파들은 인체에 유해한 것으로 밝혀지고 있고, 각종 전자기기의 마더보드에 좁은 간격으로 실장된 반도체 패키지와 기기들로부터 전자파가 발산되면, 그 주변에 실장된 반도체 패키지에까지 직간접으로 영향이 미치게 되어, 칩 회로에 손상을 입히는 것으로 밝혀지고 있다.These electromagnetic waves have been found to be harmful to the human body, and when electromagnetic waves are emitted from semiconductor packages and devices mounted at a narrow interval on the motherboard of various electronic devices, the semiconductor packages mounted on the surroundings are directly or indirectly affected. It has been found to damage circuits.

보다 상세하게는, 현재 PC대중화, 전자제품의 디지털화, 무선화, 전자제품의 소형화로 인하여 전자파 장해 문제가 대두되고 있는 바, 실제적으로 마더보드와 같은 기판상의 각 반도체 패키지 및 회로기기들은 전자파를 발생하게 되고, 이러한 전자파의 간섭으로 인하여 전자장치 자체에 회로기능 약화 및 동작 불량 등의 기능 장애 및 고장을 유발하게 된다.More specifically, the problem of electromagnetic interference due to PC popularization, digitization of electronic products, wireless, and miniaturization of electronic products has been raised. Actually, each semiconductor package and circuit devices on a substrate such as a motherboard generate electromagnetic waves. In addition, due to the interference of the electromagnetic waves, the electronic device itself may cause functional failures and failures, such as weak circuit function and poor operation.

도 3은 종래기술에 따른 전자파 차폐수단을 갖는 반도체 패키지로서, 기판(10) 상에 복수의 반도체 칩(12)이 적층되어 있고, 기판(10) 상에 접지용 전도성 패턴(11)이 형성되어 있다.3 is a semiconductor package having electromagnetic wave shielding means according to the prior art, in which a plurality of semiconductor chips 12 are stacked on a substrate 10, and a conductive pattern 11 for ground is formed on the substrate 10. have.

상기 반도체 칩(12)에는 복수의 관통 실리콘 비아(19)가 수직방향으로 동일한 배열로 각각 관통형성되어 있고, 이 관통 실리콘 비아(19)에는 범프(18)가 부착되어 상부 반도체 칩(13)과 하부 반도체 칩(14)을 물리적 및 전기적으로 연결시킨 다.A plurality of through silicon vias 19 are formed through the semiconductor chip 12 in the same arrangement in the vertical direction, and bumps 18 are attached to the through silicon vias 19 to form the upper semiconductor chip 13. The lower semiconductor chip 14 is physically and electrically connected.

상기 반도체 칩(12) 및 기판(10)의 상부에는 절연물질의 몰딩컴파운드 수지(30)가 감싸여져서 외부로부터 반도체 칩(12) 및 기판(10)을 보호하고 있고, 상기 몰딩수지(30)의 상단에 전자파 차폐층(33)이 형성되어 외부에서 발생된 전자파가 반도체 칩(12) 및 기판(10)에 침투되지 못하도록 반도체 칩(12) 및 기판(10)을 전자파로부터 차폐시킨다.An upper surface of the semiconductor chip 12 and the substrate 10 is surrounded by a molding compound resin 30 of an insulating material to protect the semiconductor chip 12 and the substrate 10 from the outside, and the molding resin 30 An electromagnetic wave shielding layer 33 is formed on the upper portion of the semiconductor shield 12 to shield the semiconductor chip 12 and the substrate 10 from electromagnetic waves so that externally generated electromagnetic waves do not penetrate the semiconductor chip 12 and the substrate 10.

이때, 상기 접지용 전도성 패턴(11)은 기판(10)에서 발생된 전자파를 제거해 주는 역할을 한다.In this case, the grounding conductive pattern 11 serves to remove electromagnetic waves generated from the substrate 10.

그러나, 상기 전자파 차폐층(33)은 외부에서 발생된 전자파가 반도체 칩(12) 및 기판(10) 내부로 침투하지 못하도록 하나, 상기 전자파는 반도체 칩(12) 자체에서 발생된 전자파를 제거하지 못함에 따라, 이 반도체 칩(12) 자체에서 발생된 전자파가 반도체 칩(12) 및 기판(10)의 회로기능 약화 및 동작 불량 등의 기능 장애 및 고장을 유발하게 된다.However, the electromagnetic shielding layer 33 prevents electromagnetic waves generated from the outside from penetrating into the semiconductor chip 12 and the substrate 10, but the electromagnetic waves cannot remove the electromagnetic waves generated from the semiconductor chip 12 itself. Accordingly, electromagnetic waves generated in the semiconductor chip 12 itself cause functional failures and failures such as weak circuit function and malfunction of the semiconductor chip 12 and the substrate 10.

본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 기판상에 적층된 각각의 반도체 칩과 기판상에 형성된 접지용 패턴을 와이어로 연결함으로써, 각 반도체 칩 자체에서 발생된 전자파를 제거할 수 있는 전자파 차폐수단을 갖는 반도체 패키지를 제공하는데 그 목적이 있다.The present invention has been made in view of the above, by connecting each semiconductor chip stacked on the substrate and the grounding pattern formed on the substrate with a wire, it is possible to remove the electromagnetic waves generated in each semiconductor chip itself It is an object of the present invention to provide a semiconductor package having an electromagnetic shielding means.

상기한 목적은 상면 테두리를 따라 접지용 전도성 패턴이 형성된 기판;The above object is a substrate formed with a conductive pattern for grounding along the upper edge;

상기 기판에 복수의 관통 실리콘 비아를 통해 통전가능하게 적층되는 다수의 반도체 칩; A plurality of semiconductor chips electrically stacked on the substrate through a plurality of through silicon vias;

상기 반도체 칩과 접지용 전도성 패턴을 연결하여 상기 반도체 칩에서 발생된 전자파를 접지시켜 제거하는 전자파 접지용 와이어; 및An electromagnetic wave grounding wire connecting the semiconductor chip and a conductive pattern for grounding to ground and remove the electromagnetic wave generated from the semiconductor chip; And

상기 반도체 칩 및 전자파 접지용 와이어를 외부로부터 절연 및 보호하기 위해 봉지되는 몰딩컴파운드 수지를 포함하는 전자파 차폐수단을 갖는 반도체 패키지에 의해 달성된다.It is achieved by a semiconductor package having electromagnetic shielding means including a molding compound resin sealed to insulate and protect the semiconductor chip and the electromagnetic wave grounding wire from the outside.

상기 과제해결수단에 의한 본 발명에 따른 전자파 차폐수단을 갖는 반도체 패키지의 장점 및 효과를 설명하면 다음과 같다.The advantages and effects of the semiconductor package having the electromagnetic shielding means according to the present invention by the above problem solving means are as follows.

1. 기판상에 적층된 각각의 반도체 칩과 접지용 전도성 패턴에 전자파 접지용 와이어를 연결함으로써, 반도체 칩에서 내부적으로 발생된 전자파를 접지하여 반도체 패키지에 대한 전자파 차폐효과를 증대시킬 수 있다.1. By connecting the electromagnetic grounding wire to each semiconductor chip and grounding conductive pattern stacked on the substrate, it is possible to increase the electromagnetic shielding effect on the semiconductor package by grounding the electromagnetic wave generated internally in the semiconductor chip.

2. 전자파 접지용 와이어와 접지용 전도성 패턴 사이에 연결된 히트스프레더가 반도체 칩에서 발생된 열을 전자파 접지용 와이어로부터 전달받아 방출함으로써, 각 반도체 칩의 열을 효과적으로 분산시킬 수 있다.2. The heat spreader connected between the electromagnetic grounding wire and the grounding conductive pattern receives and releases heat generated from the semiconductor grounding wire, thereby effectively dissipating the heat of each semiconductor chip.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도 1은 본 발명의 일실시예에 따른 전자파 차폐수단을 갖는 반도체 패키지를 나타내는 단면도이고, 도 2는 본 발명의 다른 실시예에 따른 전자파 차폐수단을 갖는 반도체 패키지를 나타내는 단면도이다.1 is a cross-sectional view showing a semiconductor package having an electromagnetic shielding means according to an embodiment of the present invention, Figure 2 is a cross-sectional view showing a semiconductor package having an electromagnetic shielding means according to another embodiment of the present invention.

본 발명은 관통 실리콘 비아(19)를 이용한 스택 패키지에서 외부의 전자파 뿐만 아니라 내부적으로 반도체 칩(12)에서 발생된 전자파를 제거할 수 있는 전자파 차폐수단을 갖는 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package having electromagnetic shielding means capable of removing not only external electromagnetic waves but also electromagnetic waves generated internally from the semiconductor chip 12 in the stack package using the through silicon vias 19.

본 발명의 일실시예에 따른 반도체 패키지는 기판(10), 반도체 칩(12), 접지용 전도성 패턴(11), 전자파 접지용 와이어(20) 등을 포함한다.The semiconductor package according to an embodiment of the present invention includes a substrate 10, a semiconductor chip 12, a conductive pattern 11 for grounding, a wire 20 for electromagnetic wave grounding, and the like.

상기 기판(10) 상에 상방향으로 제1 내지 제5반도체 칩(13~17)이 적층되어 있고, 상기 반도체 칩(12)에는 복수의 관통 실리콘 비아(19)가 수직방향으로 형성되어 있고, 상기 관통 실리콘 비아(19)에는 각각 범프(18)가 부착되어 있으며, 이 관통 실리콘 비아(19) 및 범프(18)를 통해 상부 반도체 칩과 하부 반도체 칩, 그리고 하부 반도체 칩과 기판(10)이 물리적 및 전기적으로 연결되어 있다.First to fifth semiconductor chips 13 to 17 are stacked on the substrate 10 in the upward direction, and a plurality of through silicon vias 19 are formed in the semiconductor chip 12 in the vertical direction. Bumps 18 are attached to the through silicon vias 19, respectively, and through the through silicon vias 19 and bumps 18, the upper semiconductor chip, the lower semiconductor chip, and the lower semiconductor chip and the substrate 10 are attached. It is physically and electrically connected.

상기 접지용 전도성 패턴(11)은 기판(10)상에 형성되고 반도체 패키지의 접지부와 연결되어, 기판(10)에서 발생된 전자파를 접지시킴으로써, 전자파의 간섭으로 인한 회로기능 약화 및 동작 불량 등의 기능 장애 등을 방지할 수 있다.The grounding conductive pattern 11 is formed on the substrate 10 and is connected to the ground portion of the semiconductor package to ground the electromagnetic waves generated from the substrate 10, thereby degrading circuit function due to the interference of the electromagnetic waves and poor operation. It can prevent the malfunction and the like.

상기 전자파 접지용 와이어(20)는 각 반도체 칩(12)에서 발생된 전자파를 접지용 전도성 패턴(11)과 연결하여 전자파를 접지시킴으로써, 각각의 반도체 칩(12)에서 발생된 전자파를 접지시킴으로써, 전자파의 간섭으로 인한 회로 기능 약화 및 동작 불량 등의 기능 장애 등을 방지할 수 있다.The electromagnetic wave grounding wire 20 connects the electromagnetic waves generated from each semiconductor chip 12 with the grounding conductive pattern 11 to ground the electromagnetic waves, thereby grounding the electromagnetic waves generated from each semiconductor chip 12. It is possible to prevent functional failures such as circuit malfunction and malfunction due to electromagnetic interference.

본 발명의 일실시예에 따른 전자파 접지용 와이어(20)는 적층된 복수의 반도체 칩(12) 중 일부만을 선택적으로 연결하여 전자파를 제거할 수 있다.The electromagnetic wave grounding wire 20 according to an embodiment of the present invention may selectively remove only a part of the plurality of stacked semiconductor chips 12 to remove electromagnetic waves.

예를 들어, 상기 전자파 접지용 와이어(20)는 제1 내지 제3와이어(21~23)를 포함한다.For example, the electromagnetic grounding wire 20 includes first to third wires 21 to 23.

즉, 제1와이어(21)는 제1반도체 칩(13)과 접지용 전도성 패턴(11)을 연결하는 와이어로서, 제1와이어(21)의 일단부는 제1반도체 칩(13)의 상면에 형성된 입출력단자(24)에 연결되어 있고, 제1와이어(21)의 타단부는 접지용 전도성 패턴(11)에 연결되어 있다. That is, the first wire 21 is a wire connecting the first semiconductor chip 13 and the conductive pattern 11 for grounding. One end of the first wire 21 is formed on the upper surface of the first semiconductor chip 13. It is connected to the input and output terminal 24, the other end of the first wire 21 is connected to the conductive pattern for ground (11).

그리고, 상기 제1반도체 칩(13)의 입출력단자(24)와 최외각측에 있는 범프(18)(제1 및 제2반도체 칩(14) 사이) 사이에는 전도성 연결라인(25)이 연결되어, 제1반도체 칩(13)에서 발생된 전자파가 전도성 연결라인(25) 및 입출력단자(24)를 거쳐 제1와이어(21)를 통해 접지됨으로써 제거된다.A conductive connection line 25 is connected between the input / output terminal 24 of the first semiconductor chip 13 and the bump 18 (between the first and second semiconductor chips 14) on the outermost side. The electromagnetic waves generated by the first semiconductor chip 13 are removed by being grounded through the first wire 21 via the conductive connection line 25 and the input / output terminal 24.

상기 제2와이어(22)는 제2반도체 칩(14)과 접지용 전도성 패턴(11)을 연결하는 와이어로서, 제2와이어(22)의 일단부는 제2반도체 칩(14)의 상면에 형성된 입출력단자(24)에 연결되어 있고, 제2와이어(22)의 타단부는 접지용 전도성 패턴(11)에 연결되어, 제2반도체 칩(14)에서 발생된 전자파가 제2와이어(22)를 통해 접지됨으로써 제거된다.The second wire 22 is a wire connecting the second semiconductor chip 14 and the conductive pattern 11 for grounding. One end of the second wire 22 is formed on the upper surface of the second semiconductor chip 14. It is connected to the terminal 24, the other end of the second wire 22 is connected to the grounding conductive pattern 11, the electromagnetic wave generated from the second semiconductor chip 14 through the second wire 22 It is removed by grounding.

상기 제3와이어(23)는 제3반도체 칩(15)과 접지용 전도성 패턴(11)을 연결하는 와이어로서, 제3와이어(23)의 일단부는 제3반도체 칩(15)의 상면에 형성된 입출력단자(24)에 연결되어 있고, 제3와이어(23)의 타단부는 접지용 전도성 패턴(11)에 연결되어 제3반도체 칩(15)에서 발생된 전자파가 제3와이어(23)를 통해 접지됨으로써 제거된다.The third wire 23 is a wire connecting the third semiconductor chip 15 and the conductive pattern 11 for ground, and one end of the third wire 23 is formed on the upper surface of the third semiconductor chip 15. It is connected to the terminal 24, the other end of the third wire 23 is connected to the conductive pattern 11 for grounding, the electromagnetic wave generated from the third semiconductor chip 15 is grounded through the third wire (23) By being removed.

이와 같이, 상기 와이어를 통해 각각의 반도체 칩(12)과 기판(10)의 접지용 전도성 패턴(11)을 연결함으로써, 각각의 반도체 칩(12)에서 발생된 전자파를 접지시켜 제거할 수 있다.As such, by connecting each of the semiconductor chips 12 and the conductive patterns 11 for grounding the substrate 10 through the wires, the electromagnetic waves generated in the respective semiconductor chips 12 may be grounded and removed.

본 발명의 다른 실시예에 따른 전자파 차폐수단을 갖는 반도체 패키지는 기판(10), 반도체 칩(12), 접지용 전도성 패턴(11), 전자파 접지용 와이어(20) 및 히트 스프레더를 포함한다.The semiconductor package having the electromagnetic shielding means according to another embodiment of the present invention includes a substrate 10, a semiconductor chip 12, a conductive pattern 11 for grounding, a wire 20 for electromagnetic grounding and a heat spreader.

상기 기판(10), 반도체 칩(12), 접지용 전도성 패턴(11) 및 전자파 접지용 와이어(20)의 구성 및 작용은 전술한 본 발명의 제1실시예와 동일하므로, 중복되는 설명을 생략하기로 한다.Since the structure and operation of the substrate 10, the semiconductor chip 12, the conductive conductive pattern 11 for grounding and the electromagnetic wave grounding wire 20 are the same as those of the first embodiment of the present invention, a redundant description will be omitted. Let's do it.

여기서, 상기 전자파 접지용 와이어(20)는 반도체 칩(12)과 히트 스프레더를 연결함으로써, 반도체 칩(12)에서 발생된 열을 히트 스프레더를 통해 열 방출할 뿐만 아니라 각각의 반도체 칩(12)에서 발생된 전자파를 접지용 전도성 패턴(11)에 전도시켜 접지한다.Here, the electromagnetic grounding wire 20 connects the semiconductor chip 12 and the heat spreader, thereby not only dissipating heat generated in the semiconductor chip 12 through the heat spreader, but also in each semiconductor chip 12. The generated electromagnetic waves are grounded by conducting the conductive pattern 11 for grounding.

이때, 상기 히트 스프레더는 TIM(thermal interface material)에 의해 접지용 전도성 패턴(11) 위에 부착되고, 상기 TIM은 열전도성 물질로서 스크린 인쇄 방식에 의해 테입에 도포된다.At this time, the heat spreader is attached on the conductive pattern 11 for grounding by a thermal interface material (TIM), and the TIM is applied to the tape by screen printing as a thermal conductive material.

상기 히트 스프레더(Heat spreader)는 구리 재질로 만들어진 얇은 판으로써, 열전도율이 매우 높다. The heat spreader is a thin plate made of copper and has a very high thermal conductivity.

그러나, 구리는 부식이 잘되므로, 보통 크롬 같은 내마모성과 내부식성이 강한 재질로 도금을 한다.However, copper is highly corrosive and is usually plated with materials that are resistant to wear and corrosion, such as chromium.

본 발명의 제1 및 제2실시예에서 기판(10), 접지용 전도성 패턴(11), 전자파 접지용 와이어(20), 반도체 칩(12)은 몰딩컴파운드 수지로 봉지되어 외부로부터 절연 및 보호된다.In the first and second embodiments of the present invention, the substrate 10, the grounding conductive pattern 11, the electromagnetic grounding wire 20, and the semiconductor chip 12 are sealed with a molding compound resin to be insulated and protected from the outside. .

상기 반도체 패키지에 대한 전자파 차폐를 위하여 상기 몰딩수지의 상단 표면에 전자파 차폐용 전도성 물질을 분사 도포하여 전자파 차폐층(33)을 형성한다.In order to shield the electromagnetic wave of the semiconductor package, the electromagnetic shielding layer 33 is formed by spray coating a conductive material for shielding the electromagnetic wave on the upper surface of the molding resin.

도 1은 본 발명의 일실시예에 따른 전자파 차폐수단을 갖는 반도체 패키지를 나타내는 단면도1 is a cross-sectional view showing a semiconductor package having an electromagnetic shielding means according to an embodiment of the present invention

도 2는 본 발명의 다른 실시예에 따른 전자파 차폐수단을 갖는 반도체 패키지를 나타내는 단면도2 is a cross-sectional view showing a semiconductor package having an electromagnetic shielding means according to another embodiment of the present invention

도 3은 종래기술에 따른 전자파 차폐수단을 갖는 반도체 패키지를 나타내는 단면도3 is a cross-sectional view showing a semiconductor package having an electromagnetic shielding means according to the prior art

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10 : 기판 11 : 접지용 전도성 패턴10 substrate 11 grounding conductive pattern

12 : 반도체 칩 13 : 제1반도체 칩12 semiconductor chip 13 first semiconductor chip

14 : 제2반도체 칩 15 : 제3반도체 칩14: second semiconductor chip 15: third semiconductor chip

16 : 제4반도체 칩 17 : 제5반도체 칩16: fourth semiconductor chip 17: fifth semiconductor chip

18 : 범프 19 : 관통 실리콘 비아(TSV)18 Bump 19 Through Silicon Via (TSV)

20 : 전자파 접지용 와이어 21 : 제1와이어20: electromagnetic wave ground wire 21: the first wire

22 : 제2와이어 23 : 제3와이어22: second wire 23: third wire

24 : 입출력단자 25 : 전도성 연결라인24: input / output terminal 25: conductive connection line

30 : 몰딩컴파운드 수지 31 : 히트 스프레더30: molding compound resin 31: heat spreader

32 : TIM 33 : 전자파 차폐층32: TIM 33: electromagnetic shielding layer

Claims (4)

상면 테두리를 따라 접지용 전도성 패턴(11)이 형성된 기판(10);A substrate 10 having a conductive pattern 11 for grounding formed along an upper edge thereof; 상기 기판(10)에 복수의 관통 실리콘 비아(19)를 통해 통전가능하게 적층되는 다수의 반도체 칩(12);A plurality of semiconductor chips 12 electrically stacked on the substrate 10 through a plurality of through silicon vias 19; 다수의 반도체 칩(12) 중 선택된 일부의 반도체 칩(12)의 입출력단자(24)와 기판(10)의 접지용 전도성 패턴(11)을 연결하여 상기 반도체 칩(12)에서 발생된 전자파를 접지시켜 제거하는 전자파 접지용 와이어(20); 및 The electromagnetic wave generated in the semiconductor chip 12 is grounded by connecting the input / output terminal 24 of the semiconductor chip 12 selected from the plurality of semiconductor chips 12 and the conductive pattern 11 for grounding the substrate 10. Electromagnetic wave grounding wire 20 to be removed; And 상기 반도체 칩(12) 및 전자파 접지용 와이어(20)를 외부로부터 절연 및 보호하기 위해 봉지되는 몰딩컴파운드 수지(30)를 포함하는 전자파 차폐수단을 갖는 반도체 패키지.A semiconductor package having electromagnetic shielding means including a molding compound resin (30) sealed to insulate and protect the semiconductor chip (12) and the electromagnetic wave grounding wire (20) from the outside. 삭제delete 청구항 1에 있어서, 상기 전자파 접지용 와이어(20)의 일단부와 연결되고, 상기 접지용 전도성 패턴(11)의 상면에 장착되어, 상기 반도체 칩(12)에서 발생된 열을 전자파 접지용 와이어(20)를 통해 전달받아 방출하는 히트 스프레더(31)를 더 포함하는 것을 특징으로 하는 전자파 차폐수단을 갖는 반도체 패키지.The electromagnetic wave grounding wire of claim 1, wherein the heat generated from the semiconductor chip 12 is connected to one end of the electromagnetic wave grounding wire 20 and mounted on an upper surface of the conductive pattern 11 for grounding. 20) A semiconductor package having electromagnetic shielding means, characterized in that it further comprises a heat spreader (31) for receiving and transmitting through. 청구항 1에 있어서, 상기 몰딩컴파운드 수지(30)의 전체표면 또는 측면에 걸쳐 형성된 전자파 차폐층(33)을 포함하는 것을 특징으로 하는 전자파 차폐수단을 갖는 반도체 패키지.The semiconductor package according to claim 1, further comprising an electromagnetic shielding layer (33) formed over the entire surface or side surfaces of the molding compound resin (30).
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WO2017171807A1 (en) * 2016-03-31 2017-10-05 Intel Corporation Semiconductor package with electromagnetic interference shielding using metal layers and vias
CN111342814B (en) * 2020-02-10 2021-09-21 诺思(天津)微系统有限责任公司 Bulk acoustic wave filter, multiplexer and electronic equipment

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