TW201316477A - Package module with EMI shielding - Google Patents
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- TW201316477A TW201316477A TW100136352A TW100136352A TW201316477A TW 201316477 A TW201316477 A TW 201316477A TW 100136352 A TW100136352 A TW 100136352A TW 100136352 A TW100136352 A TW 100136352A TW 201316477 A TW201316477 A TW 201316477A
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
本發明係有關於電子封裝模組，特定而言係有關於具有電磁干擾屏蔽功能及微型封裝特性之封裝模組。The invention relates to an electronic package module, in particular to a package module having an electromagnetic interference shielding function and a micro package characteristic.
由於半導體科技的快速發展，電子產品例如行動電話、電視、筆記型電腦等之複雜度及功能性大為增加。越來越多複雜且高速的半導體裝置被封裝於基板或印刷電路板內。高速半導體裝置會產生電磁波而干擾其他裝置，或受到其他高速裝置所發射之電磁波之干擾。電磁干擾(electromagnetic interference，EMI)將會負面影響電子系統之操作，而電磁干擾所造成之問題對電子儀器的製造者而言已屬常見。Due to the rapid development of semiconductor technology, the complexity and functionality of electronic products such as mobile phones, televisions, and notebook computers have increased greatly. More and more complex and high speed semiconductor devices are packaged in substrates or printed circuit boards. High-speed semiconductor devices generate electromagnetic waves that interfere with other devices or are interfered with by electromagnetic waves emitted by other high-speed devices. Electromagnetic interference (EMI) will negatively affect the operation of electronic systems, and the problems caused by electromagnetic interference are common to manufacturers of electronic instruments.
一種傳統減少電磁干擾之方法係提供分離的金屬殼於模製的半導體封裝上。金屬殼一般連接至接地平面或印刷電路板上之接墊上，以減少電磁干擾。然而，金屬殼卻會負面增加封裝的厚度，而此情況必定無法滿足微型封裝的趨勢。此外，金屬殼的形成需要額外的製程及附加的材料，而將顯著增加封裝成本。於另一方法中，導電泡沫塑料或橡膠被施於模製封裝上，以吸收電磁干擾。然而，導電泡沫塑料或橡膠必須以人工施加，且需要特別之材料及額外的製程，而將會顯著增加封裝成本。再者，導電泡沫塑料或橡膠亦會負面增加模製封裝之厚度。一種進階的習知方法為將屏蔽表面直接金屬化，並將其與接地金屬線接觸。然而，屏蔽範圍係涵蓋整個封裝，且若要改變屏蔽的形狀及範圍則具有較小的彈性。One conventional method of reducing electromagnetic interference is to provide a separate metal shell on a molded semiconductor package. Metal shells are typically connected to ground planes or pads on printed circuit boards to reduce electromagnetic interference. However, the metal shell will negatively increase the thickness of the package, and this situation must not meet the trend of micro-package. In addition, the formation of metal shells requires additional processing and additional materials, which will significantly increase packaging costs. In another method, a conductive foam or rubber is applied to the molded package to absorb electromagnetic interference. However, conductive foam or rubber must be applied manually and requires special materials and additional processes that will significantly increase packaging costs. Furthermore, conductive foam or rubber can also negatively increase the thickness of the molded package. An advanced conventional method is to directly metallize the shielded surface and contact it with a grounded metal line. However, the shielding range covers the entire package and has less flexibility to change the shape and extent of the shield.
本發明係揭露具電磁干擾屏蔽之例示封裝模組。藉由在針對性地在導線上形成介電層和屏蔽層，以節省材料成本。The present invention discloses an exemplary package module with electromagnetic interference shielding. Material costs are saved by forming a dielectric layer and a shielding layer on the wires in a targeted manner.
本發明之一態樣揭露一種具電磁干擾屏蔽之封裝模組，包含：一基板；一接地接墊，其裝設於該基板上；一第一晶粒，其裝設於該基板上且具有一第一接觸墊；一黏膠層，其塗佈在該第一晶粒的上表面；一第二晶粒，其裝設於該黏膠層上且具有一第二接觸墊；一導電柱，其位於穿透該基板之一通孔內，且具有一導電墊；一第一導線，其連接該第一晶粒的該第一接觸墊和該導電柱之該導電墊；一第二導線，其連接該第二晶粒的該第二接觸墊和該導電柱之該導電墊；一第一導線介電層，其針對性地形成在該第一導線上；以及一第一導線屏蔽層，其針對性地形成在該第一導線介電層上，且電性耦合至該接地接墊，一第二導線介電層，其針對性地形成在該第二導線上；以及一第二導線屏蔽層，其針對性地形成在該第二導線介電層上，且電性耦合至該接地接墊，其中該第一導線介電層和該第一導線屏蔽層之整體以及該第二導線介電層和該第二導線屏蔽層之整體係用以降低電磁干擾。A package module with electromagnetic interference shielding includes: a substrate; a ground pad mounted on the substrate; a first die mounted on the substrate and having a first contact pad; an adhesive layer coated on the upper surface of the first die; a second die mounted on the adhesive layer and having a second contact pad; a conductive post a conductive pad formed in the through hole of the substrate and having a conductive pad; a first wire connecting the first contact pad of the first die and the conductive pad of the conductive post; a second wire, The second contact pad of the second die and the conductive pad of the conductive pillar; a first conductive layer of dielectric, which is specifically formed on the first wire; and a first wire shielding layer, Specifically formed on the first conductor dielectric layer and electrically coupled to the ground pad, a second wire dielectric layer, which is formed on the second wire in a targeted manner; and a second wire a shielding layer, which is specifically formed on the second conductor dielectric layer and electrically coupled to the ground connection Wherein the entire first conductor layer and the dielectric layer of the first shield conductor and the second lead-based dielectric layer and the whole of the second conductor shield to reduce electromagnetic interference.
本發明之另一態樣揭露一種具電磁干擾屏蔽之封裝模組，包含：一基板；一接地接墊，其裝設於該基板上；一晶粒，其裝設於該基板上且具有一接觸墊；一導電柱，其位於穿透該基板之一通孔內，且其上端具有一上導電墊而其下端具有一下導電墊；一導電凸塊，其連接於該導電柱的該下導電墊的下方；一導線，其連接該晶粒的該接觸墊和該導電柱之該上導電墊；一導線介電層，其針對性地形成在該導線上；以及一導線屏蔽層，其針對性地形成在該導線介電層上，且電性耦合至該接地接墊，其中該導線介電層和該導線屏蔽層係之整體係用以降低電磁干擾。Another aspect of the invention provides a package module with electromagnetic interference shielding, comprising: a substrate; a ground pad mounted on the substrate; a die mounted on the substrate and having a a conductive pad, which is located in a through hole penetrating the substrate, and has an upper conductive pad at an upper end and a lower conductive pad at a lower end thereof; and a conductive bump connected to the lower conductive pad of the conductive post a wire that connects the contact pad of the die and the upper conductive pad of the conductive post; a wire dielectric layer that is specifically formed on the wire; and a wire shielding layer that is targeted The ground dielectric layer is electrically formed and electrically coupled to the ground pad, wherein the wire dielectric layer and the wire shielding layer are integrally used to reduce electromagnetic interference.
本發明之又一態樣揭露一種具電磁干擾屏蔽之封裝模組，包含：一第一基板，其具有一第一導電墊；一第二基板，其設置於該第一基板下方，且具有一第二導電墊和一接地接墊；一第一晶粒，其裝設於該第一基板上且具有一第一接觸墊和一第二接觸墊；一第一重分佈線，其連接該第一接觸墊和該第一導電墊；一導線，其連接該第一導電墊和該第二導電墊；一導線介電層，其針對性地形成在該導線上；以及一導線屏蔽層，其針對性地形成在該導線介電層上，且電性耦合至該接地接墊，其中該導線介電層和該導線屏蔽層係用以降低電磁干擾。In another aspect of the invention, a package module with electromagnetic interference shielding includes: a first substrate having a first conductive pad; a second substrate disposed under the first substrate and having a first substrate a second conductive pad and a ground pad; a first die mounted on the first substrate and having a first contact pad and a second contact pad; a first redistribution line connecting the first a contact pad and the first conductive pad; a wire connecting the first conductive pad and the second conductive pad; a wire dielectric layer specifically formed on the wire; and a wire shielding layer The conductive layer is electrically formed and electrically coupled to the ground pad, wherein the wire dielectric layer and the wire shielding layer are used to reduce electromagnetic interference.
以下將敘述若干用以形成各式層之例示的技術。於一實施例中，形成接地接墊之技術包含濺鍍、印刷、電鍍、物理氣相沈積(PVD)、化學氣相沈積(CVD)或任何其結合。形成介電層之技術包含濺鍍、化學氣相沈積(CVD)、印刷或任何其結合。形成屏蔽層之技術包含濺鍍、印刷、電鍍、物理氣相沈積(PVD)、化學氣相沈積(CVD)或任何其結合。形成接合層之技術包含濺鍍、印刷、化學氣相沈積(CVD)或任何其結合。形成介電層之技術包含射出、印刷、模造製程或任何其結合。Several techniques for forming various layers are described below. In one embodiment, the technique of forming a ground pad includes sputtering, printing, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. Techniques for forming a dielectric layer include sputtering, chemical vapor deposition (CVD), printing, or any combination thereof. Techniques for forming a shield layer include sputtering, printing, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. Techniques for forming the bonding layer include sputtering, printing, chemical vapor deposition (CVD), or any combination thereof. Techniques for forming a dielectric layer include injection, printing, molding processes, or any combination thereof.
本發明將以下述實施例加以敘述，應領會者為此類實施例的敘述及範例僅用以說明而非用以限制本發明之申請專利範圍。因此，除說明書中所述之實施例以外，本發明亦可實行於其他大體上等同之實施例中。The invention is described in the following examples, which are intended to be illustrative and not to limit the scope of the invention. Accordingly, the present invention may be embodied in other substantially equivalent embodiments in addition to the embodiments described in the specification.
以下將詳細敘述具電磁干擾屏蔽之封裝模組以及其製造方法，上述封裝模組具有薄型屏蔽層。本發明之封裝模組有效降低從高速電子裝置所發射之電磁波或來自於其他電子裝置之電磁波。電子裝置或系統之間之電磁干擾(electromagnetic interference，EMI)會影響電子產品之正常運作。The package module with electromagnetic interference shielding and the manufacturing method thereof will be described in detail below, and the package module has a thin shielding layer. The package module of the present invention effectively reduces electromagnetic waves emitted from high-speed electronic devices or electromagnetic waves from other electronic devices. Electromagnetic interference (EMI) between electronic devices or systems can affect the normal operation of electronic products.
本發明之封裝模組因薄型屏蔽層而不會體積龐大且可符合現行應用中微型封裝之需求。The package module of the present invention is not bulky due to the thin shielding layer and can meet the requirements of the micro package in the current application.
在一實施例中，第1圖繪示其上形成有介電層和屏蔽層之導線的剖圖圖。其中導線介電層104是針對性地形成在導線102上；而導線屏蔽層106是針對性地形成在該導線介電層104上。導線屏蔽層106電性耦合至接地接墊。如此，該導線介電層104和該導線屏蔽層106便能降低電磁對導線102的干擾。In one embodiment, FIG. 1 is a cross-sectional view showing a wire on which a dielectric layer and a shield layer are formed. The wire dielectric layer 104 is specifically formed on the wire 102; and the wire shielding layer 106 is formed on the wire dielectric layer 104 in a targeted manner. The wire shield 106 is electrically coupled to the ground pad. As such, the wire dielectric layer 104 and the wire shield 106 can reduce electromagnetic interference with the wires 102.
在另一實施例中，第2圖繪示其上形成有介電層和屏蔽層之導線的又一剖圖圖。其中導線介電層204和導線屏蔽層206係完全包覆導線202。In another embodiment, FIG. 2 is a further cross-sectional view showing a wire on which a dielectric layer and a shielding layer are formed. The wire dielectric layer 204 and the wire shielding layer 206 completely enclose the wire 202.
第3圖繪示本發明之一種具電磁干擾屏蔽之封裝模組300，包含：一基板302；一接地接墊(未圖示)，其裝設於該基板302上；一第一晶粒307，其裝設於該基板302上且具有一第一接觸墊308；一黏膠層310，其塗佈在該第一晶粒307的上表面；一第二晶粒311，其裝設於該黏膠層310上且具有一第二接觸墊312；一導電柱，其位於穿透該基板302之一通孔內，且其上端具有一上導電墊315而其下端具有一下導電墊318；一導電凸塊314，其連接於該導電柱的該下導電墊318的下方；一第一導線316，其連接該第一晶粒307的該第一接觸墊308和該導電柱之該導電墊315；一第二導線317，其連接該第二晶粒的該第二接觸墊312和該導電柱之該導電墊315。FIG. 3 illustrates a package module 300 with electromagnetic interference shielding according to the present invention, comprising: a substrate 302; a ground pad (not shown) mounted on the substrate 302; a first die 307 It is mounted on the substrate 302 and has a first contact pad 308; an adhesive layer 310 coated on the upper surface of the first die 307; and a second die 311 mounted on the substrate The adhesive layer 310 has a second contact pad 312; a conductive post which is located in a through hole of the substrate 302, and has an upper conductive pad 315 at its upper end and a lower conductive pad 318 at its lower end; a bump 314 connected to the lower conductive pad 318 of the conductive post; a first wire 316 connecting the first contact pad 308 of the first die 307 and the conductive pad 315 of the conductive post; A second wire 317 is connected to the second contact pad 312 of the second die and the conductive pad 315 of the conductive post.
其中，該導電凸塊314可以為一錫球，亦即本發明適用於一球狀引腳柵格陣列(BGA)之封裝。The conductive bump 314 can be a solder ball, that is, the present invention is applicable to a package of a ball-shaped lead grid array (BGA).
選擇性地，該第二晶粒311的一主動面上可形成有一介電層，該介電層上可形成有一屏蔽層，用以降低電磁干擾。Optionally, a dielectric layer may be formed on an active surface of the second die 311, and a shielding layer may be formed on the dielectric layer to reduce electromagnetic interference.
選擇性地，該導電凸塊上形成有一介電層，該介電層上形成有一屏蔽層，用以降低電磁干擾。Optionally, a dielectric layer is formed on the conductive bump, and a shielding layer is formed on the dielectric layer to reduce electromagnetic interference.
如同第1圖般，在第4圖所繪示的封裝結構之該第一導線316上可針對性地形成一第一導線介電層，並在該第一導線介電層上形成一第一導線屏蔽層，其中該第一導線屏蔽層可電性耦合至該接地接墊。同樣地，亦可針對性地在該第二導線上形成一第二導線介電層；以及針對性地在該第二導線介電層上形成一第二導線屏蔽層，其中該第二導線屏蔽層亦可電性耦合至該接地接墊，其中該第一導線介電層和該第一導線屏蔽層之整體以及該第二導線介電層和該第二導線屏蔽層之整體係用以降低電磁干擾。As shown in FIG. 1 , a first conductive dielectric layer can be formed on the first conductive line 316 of the package structure illustrated in FIG. 4 , and a first conductive layer is formed on the first conductive dielectric layer. a wire shielding layer, wherein the first wire shielding layer is electrically coupled to the ground pad. Similarly, a second wire dielectric layer may be formed on the second wire in a targeted manner; and a second wire shielding layer is formed on the second wire dielectric layer, wherein the second wire shielding layer is formed. The layer may be electrically coupled to the ground pad, wherein the entirety of the first wire dielectric layer and the first wire shielding layer and the second wire dielectric layer and the second wire shielding layer are integrally reduced Electromagnetic interference.
如同第2圖般，第3圖所繪示的封裝結構之該第一導線介電層和該第一導線屏蔽層之整體係完全包覆該第一導線316，以及該第二導線介電層和該第二導線屏蔽層之整體係完全包覆該第二導線317。As shown in FIG. 2, the first conductive dielectric layer and the first conductive shielding layer of the package structure shown in FIG. 3 completely cover the first conductive line 316, and the second conductive dielectric layer. The second wire 317 is completely covered by the entirety of the second wire shielding layer.
第4圖繪示繪示本發明之另一種具電磁干擾屏蔽之封裝模組400，包含：一第一基板401，其具有一第一導電墊411；一第二基板409，其設置於該第一基板401下方，且具有一第二導電墊431和一接地接墊(未圖示)；一第一晶粒420，其裝設於該第一基板401上且具有一第一接觸墊416和一第二接觸墊429；一第一重分佈線433，其連接該第一接觸墊416和該第一導電墊411；一導線412，其連接該第一導電墊411和該第二導電墊431FIG. 4 illustrates another EMI shielding package module 400 of the present invention, comprising: a first substrate 401 having a first conductive pad 411; and a second substrate 409 disposed on the first A substrate 401 has a second conductive pad 431 and a ground pad (not shown); a first die 420 is mounted on the first substrate 401 and has a first contact pad 416 and a second contact pad 429; a first redistribution line 433 connecting the first contact pad 416 and the first conductive pad 411; a wire 412 connecting the first conductive pad 411 and the second conductive pad 431
選擇性地，更包含；一第二晶粒422，其與該第一晶粒420並排裝設於該第一基板401上，且包含一第三接觸墊434；及一第二重分佈線426，其連接該第一晶粒420的該第二接觸墊429和該第二晶粒422的該第三接觸墊434。Optionally, a second die 422 is mounted on the first substrate 401 along the first die 420 and includes a third contact pad 434; and a second redistribution line 426. The second contact pad 429 of the first die 420 and the third contact pad 434 of the second die 422 are connected.
選擇性地，該第一重分佈線433和該第二重分佈線426上分別形成有一介電層，該介電層上形成有一屏蔽層，用以降低電磁干擾。Optionally, a dielectric layer is formed on the first redistribution line 433 and the second redistribution line 426, and a shielding layer is formed on the dielectric layer to reduce electromagnetic interference.
如同第1圖般，第4圖所繪示的封裝結構更包含：一導線介電層，其針對性地形成在該導線412上；以及一導線屏蔽層，其針對性地形成在該導線介電層上，且電性耦合至該接地接墊，其中該導線介電層和該導線屏蔽層係用以降低電磁干擾。As shown in FIG. 1 , the package structure illustrated in FIG. 4 further includes: a wire dielectric layer specifically formed on the wire 412; and a wire shielding layer that is specifically formed on the wire The electrical layer is electrically coupled to the ground pad, wherein the wire dielectric layer and the wire shielding layer are used to reduce electromagnetic interference.
如同第2圖般，第4圖所繪示的封裝結構之導線介電層和導線屏蔽層係完全包覆導線412。As in FIG. 2, the wire dielectric layer and the wire shielding layer of the package structure shown in FIG. 4 completely enclose the wire 412.
第5圖繪示本發明之又一種具電磁干擾屏蔽之封裝模組500，包含：一基板506；一接地接墊(未圖示)，其裝設於該基板506上；一晶粒504，其裝設於該基板506上且具有一接觸墊508；一導電柱516，其位於穿透該基板506之一通孔內，且具有一導電墊513；一導線511，其連接該晶粒504的該接觸墊508和該導電柱516之該導電墊513。FIG. 5 illustrates a package module 500 with electromagnetic interference shielding according to the present invention, comprising: a substrate 506; a ground pad (not shown) mounted on the substrate 506; a die 504, The device is mounted on the substrate 506 and has a contact pad 508. The conductive post 516 is located in a through hole of the substrate 506 and has a conductive pad 513. A wire 511 is connected to the die 504. The contact pad 508 and the conductive pad 513 of the conductive post 516.
其中，形成上述具電磁干擾屏蔽之封裝模組500之方法包含下列步驟：提供一基板506，其中該基板506具有一接地接墊(未圖示)和一通孔；設置一晶粒504於該基板506之上，其中該晶粒504具有一接觸墊508；形成一導電柱516於該基板506的該通孔內，其中該導電柱516具有一導電墊513；形成一導線511，以連接該晶粒504的該接觸墊508和該導電柱516之該導電墊513；形成一導線介電層於該導線上；以及形成一導線屏蔽層於該導線介電層上，且電性耦合至該接地接墊，以降低電磁干擾。The method for forming the EMI shielding package module 500 includes the following steps: providing a substrate 506, wherein the substrate 506 has a ground pad (not shown) and a through hole; and a die 504 is disposed on the substrate Above the 506, the die 504 has a contact pad 508; a conductive post 516 is formed in the through hole of the substrate 506, wherein the conductive post 516 has a conductive pad 513; a wire 511 is formed to connect the crystal The contact pad 508 of the particle 504 and the conductive pad 513 of the conductive post 516; forming a wire dielectric layer on the wire; and forming a wire shielding layer on the wire dielectric layer and electrically coupled to the ground Pads to reduce electromagnetic interference.
此外，在晶粒504的左側具有另一接觸墊509，藉由一導線512連接接觸墊509至導電柱514的導電墊。其中，導線512上亦可作與導線511相同的導線介電層和導線屏蔽層。In addition, another contact pad 509 is provided on the left side of the die 504, and the contact pad 509 is connected to the conductive pad of the conductive post 514 by a wire 512. Wherein, the wire 512 can also be used as the same wire dielectric layer and wire shielding layer as the wire 511.
由於第5圖之晶片封裝屬於多晶粒堆疊，在晶粒504上塗佈有一彈性黏膠層524，其上堆疊有另一晶粒522，晶粒522亦具有一接觸墊526，藉由一導線530連接接觸墊526至導電柱516的導電墊513。其中，導線530上亦可作與導線511相同的導線介電層和導線屏蔽層。Since the chip package of FIG. 5 belongs to a multi-die stack, an elastic adhesive layer 524 is coated on the die 504, and another die 522 is stacked thereon. The die 522 also has a contact pad 526. Wire 530 connects contact pad 526 to conductive pad 513 of conductive post 516. Wherein, the wire 530 can also be used as the same wire dielectric layer and wire shielding layer as the wire 511.
進一步地，在形成該導線介電層於該導線上的步驟中，及在形成該導線屏蔽層於該導線介電層上的步驟中，藉由翻轉該封裝模組，可使該導線介電層和該導線屏蔽層形成在該導線的不同部位，甚至可使該導線介電層和該導線屏蔽層完全包覆該導線。應注意者，不論部分包覆或完全包覆皆能夠達成屏蔽的效用，而以完全包覆的效果較佳。Further, in the step of forming the wire dielectric layer on the wire, and in the step of forming the wire shielding layer on the wire dielectric layer, the wire can be dielectrically turned by flipping the package module The layer and the wire shielding layer are formed at different portions of the wire, and even the wire dielectric layer and the wire shielding layer can completely cover the wire. It should be noted that the effect of shielding can be achieved regardless of whether the partial coating or the complete coating is achieved, and the effect of complete coating is better.
由於可以翻轉該封裝模組，屏蔽層可形成在與晶粒的一主動面相同的一面，也可形成在與晶粒的一主動面相反的另一面。Since the package module can be flipped, the shield layer can be formed on the same side as an active surface of the die, or on the other side opposite to an active face of the die.
因此，本發明之具電磁干擾屏蔽之封裝模組具有類似同軸電纜的效果，可有效降低電磁干擾及增加傳輸效率及速度。Therefore, the package module with electromagnetic interference shielding of the invention has the effect similar to the coaxial cable, and can effectively reduce electromagnetic interference and increase transmission efficiency and speed.
在工業上，本發明之導線介電層和導線屏蔽層可應用於下列，包括：射頻(RF)產品、多導線(wire)產品、球柵陣列(BGA)的晶粒堆疊產品、如第5圖所示之多晶粒堆疊的晶片封裝、其上有晶片及被動元件的印刷電路板(PCB)、等等。基本上，只要是放進處理爐進行製造的產品，皆可用本發明取代傳統鐵殼而達成屏蔽的效果。In the industry, the wire dielectric layer and the wire shielding layer of the present invention can be applied to the following, including: radio frequency (RF) products, multi-wire products, ball grid array (BGA) die stack products, such as the fifth The multi-die stacked wafer package shown, the printed circuit board (PCB) with the wafer and passive components thereon, and the like. Basically, as long as it is placed in a processing furnace for manufacturing, the conventional iron shell can be replaced by the present invention to achieve a shielding effect.
雖本發明之較佳實施例已敘述如上，但此領域之技藝者應得以領會本發明不應限於此處所述之較佳實施例。在不脫離下述申請專利範圍所定義之本發明的精神及範圍下可作若干之更動及潤飾。While the preferred embodiment of the invention has been described above, those skilled in the art should understand that the invention is not limited to the preferred embodiments described herein. A number of changes and modifications may be made without departing from the spirit and scope of the invention as defined by the following claims.
102．．．導線102. . . wire
104．．．導線介電層104. . . Wire dielectric layer
106．．．導線屏蔽層106. . . Wire shield
202．．．導線202. . . wire
204．．．導線介電層204. . . Wire dielectric layer
206．．．導線屏蔽層206. . . Wire shield
300．．．封裝模組300. . . Package module
302．．．基板302. . . Substrate
303．．．導電墊303. . . Conductive pad
304．．．導電墊304. . . Conductive pad
305．．．導線305. . . wire
306．．．導線306. . . wire
307．．．晶粒307. . . Grain
308．．．接觸墊308. . . Contact pad
309．．．黏膠層309. . . Adhesive layer
310．．．黏膠層310. . . Adhesive layer
311．．．晶粒311. . . Grain
312．．．接觸墊312. . . Contact pad
313．．．介電層313. . . Dielectric layer
314．．．導電凸塊314. . . Conductive bump
315．．．導電墊315. . . Conductive pad
316．．．導線316. . . wire
317．．．導線317. . . wire
318．．．導電墊318. . . Conductive pad
400．．．封裝結構400. . . Package structure
401．．．基板401. . . Substrate
402．．．黏膠層402. . . Adhesive layer
403．．．晶粒容納凹槽403. . . Grain receiving groove
404．．．晶粒404. . . Grain
405．．．接觸墊405. . . Contact pad
406．．．導電層406. . . Conductive layer
407．．．導電層407. . . Conductive layer
408．．．黏著層408. . . Adhesive layer
409．．．基板409. . . Substrate
410．．．導電墊410. . . Conductive pad
411．．．接觸墊411. . . Contact pad
412．．．導線412. . . wire
413．．．導線413. . . wire
414．．．導線414. . . wire
416．．．接觸墊416. . . Contact pad
418．．．接觸墊418. . . Contact pad
420．．．晶粒420. . . Grain
422．．．晶粒422. . . Grain
426．．．重佈線426. . . Redistribution
429．．．接觸墊429. . . Contact pad
430．．．介電層430. . . Dielectric layer
431．．．導電墊431. . . Conductive pad
432．．．介電層432. . . Dielectric layer
433．．．重分佈線433. . . Redistribution line
434．．．接觸墊434. . . Contact pad
438．．．黏著層438. . . Adhesive layer
440．．．黏膠層440. . . Adhesive layer
445．．．介電層445. . . Dielectric layer
450．．．導電凸塊450. . . Conductive bump
500．．．封裝模組500. . . Package module
504．．．晶粒504. . . Grain
505．．．晶粒容納凹槽505. . . Grain receiving groove
506．．．基板506. . . Substrate
507．．．黏著層507. . . Adhesive layer
508．．．接觸墊508. . . Contact pad
509．．．接觸墊509. . . Contact pad
510．．．接觸墊510. . . Contact pad
511．．．導線511. . . wire
512．．．導線512. . . wire
513．．．導電墊513. . . Conductive pad
514．．．導電柱514. . . Conductive column
515．．．導電墊515. . . Conductive pad
516．．．導電柱516. . . Conductive column
517．．．導電層517. . . Conductive layer
518．．．介電層518. . . Dielectric layer
520．．．導電凸塊520. . . Conductive bump
522．．．晶粒522. . . Grain
524．．．黏膠層524. . . Adhesive layer
526．．．接觸墊526. . . Contact pad
528．．．導線528. . . wire
530．．．導線530. . . wire
本發明之上述目的及其他特徵及優點可藉由說明書中之若干詳細敘述並結合後附圖式而得以瞭解，其中：The above and other features and advantages of the present invention will become apparent from
第1圖繪示其上形成有介電層和屏蔽層之導線的剖圖圖。Figure 1 is a cross-sectional view showing a wire on which a dielectric layer and a shield layer are formed.
第2圖繪示其上形成有介電層和屏蔽層之導線的又一剖圖圖。2 is a cross-sectional view showing a wire on which a dielectric layer and a shield layer are formed.
第3圖繪示本發明之一種具電磁干擾屏蔽之封裝模組。FIG. 3 illustrates a package module with electromagnetic interference shielding according to the present invention.
第4圖繪示本發明之另一種具電磁干擾屏蔽之封裝模組。FIG. 4 is a diagram showing another package module with electromagnetic interference shielding according to the present invention.
第5圖繪示本發明之又一種具電磁干擾屏蔽之封裝模組。FIG. 5 illustrates another package module with electromagnetic interference shielding according to the present invention.
500．．．封裝模組500. . . Package module
504．．．晶粒504. . . Grain
505．．．晶粒容納凹槽505. . . Grain receiving groove
506．．．基板506. . . Substrate
507．．．黏著層507. . . Adhesive layer
508．．．接觸墊508. . . Contact pad
509．．．接觸墊509. . . Contact pad
510．．．接觸墊510. . . Contact pad
511．．．導線511. . . wire
512．．．導線512. . . wire
513．．．導電墊513. . . Conductive pad
514．．．導電柱514. . . Conductive column
515．．．導電墊515. . . Conductive pad
516．．．導電柱516. . . Conductive column
517．．．導電層517. . . Conductive layer
518．．．介電層518. . . Dielectric layer
520．．．導電凸塊520. . . Conductive bump
522．．．晶粒522. . . Grain
524．．．黏膠層524. . . Adhesive layer
526．．．接觸墊526. . . Contact pad
528．．．導線528. . . wire
530．．．導線530. . . wire
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|---|---|---|---|
| TW100136352A TWI484616B (en) | 2011-10-06 | 2011-10-06 | Package module with emi shielding |
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|---|---|---|---|
| TW100136352A TWI484616B (en) | 2011-10-06 | 2011-10-06 | Package module with emi shielding |
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| TW201316477A true TW201316477A (en) | 2013-04-16 |
| TWI484616B TWI484616B (en) | 2015-05-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW100136352A TWI484616B (en) | 2011-10-06 | 2011-10-06 | Package module with emi shielding |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI484616B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015000594A1 (en) * | 2013-07-03 | 2015-01-08 | Rosenberger Hochfrequenztechnik Gmbh & Co. Kg | An interconnect system comprising an interconnect having a plurality of metal cores at least partially surrounded by a dielectric layer |
| WO2015000597A1 (en) * | 2013-07-03 | 2015-01-08 | Rosenberger Hochfrequenztechnik Gmbh & Co. Kg | Mixed impedance bond wire connections and method of making the same |
| WO2015000595A1 (en) * | 2013-07-03 | 2015-01-08 | Rosenberger Hochfrequenztechnik Gmbh & Co. Kg | Electronic device having a lead with selectively modified electrical properties |
| CN105474388A (en) * | 2013-07-03 | 2016-04-06 | 罗森伯格高频技术有限及两合公司 | Die package with low electromagnetic interference interconnection |
| TWI712130B (en) * | 2015-11-12 | 2020-12-01 | 美商艾馬克科技公司 | Semiconductor package and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI264103B (en) * | 2005-12-23 | 2006-10-11 | Kou-Ning Chiang | A 3D electronic packaging structure with enhanced grounding performance and embedded antenna |
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2011
- 2011-10-06 TW TW100136352A patent/TWI484616B/en active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015000594A1 (en) * | 2013-07-03 | 2015-01-08 | Rosenberger Hochfrequenztechnik Gmbh & Co. Kg | An interconnect system comprising an interconnect having a plurality of metal cores at least partially surrounded by a dielectric layer |
| WO2015000597A1 (en) * | 2013-07-03 | 2015-01-08 | Rosenberger Hochfrequenztechnik Gmbh & Co. Kg | Mixed impedance bond wire connections and method of making the same |
| WO2015000595A1 (en) * | 2013-07-03 | 2015-01-08 | Rosenberger Hochfrequenztechnik Gmbh & Co. Kg | Electronic device having a lead with selectively modified electrical properties |
| CN105378915A (en) * | 2013-07-03 | 2016-03-02 | 罗森伯格高频技术有限及两合公司 | Mixed impedance bond wire connections and method of making the same |
| CN105474388A (en) * | 2013-07-03 | 2016-04-06 | 罗森伯格高频技术有限及两合公司 | Die package with low electromagnetic interference interconnection |
| US9673137B2 (en) | 2013-07-03 | 2017-06-06 | Rosenberger Hochfrequenztechnik Gmbh & Co. Kg | Electronic device having a lead with selectively modified electrical properties |
| US9812420B2 (en) | 2013-07-03 | 2017-11-07 | Rosenberger Hochfrequenztechnik Gmbh & Co. Kg | Die packaging with fully or partially fused dielectric leads |
| CN105474388B (en) * | 2013-07-03 | 2018-06-19 | 罗森伯格高频技术有限及两合公司 | Electromagnetic interference interconnects low bare die packaging body |
| CN105378915B (en) * | 2013-07-03 | 2018-09-11 | 罗森伯格高频技术有限及两合公司 | Mix the bonding wire connection and attaching method thereof of impedance |
| US10340209B2 (en) | 2013-07-03 | 2019-07-02 | Rosenberger Hochfrequenztechnik Gmbh & Co. Kg | Mixed impedance leads for die packages and method of making the same |
| TWI712130B (en) * | 2015-11-12 | 2020-12-01 | 美商艾馬克科技公司 | Semiconductor package and manufacturing method thereof |
| TWI774106B (en) * | 2015-11-12 | 2022-08-11 | 美商艾馬克科技公司 | Semiconductor package and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| TWI484616B (en) | 2015-05-11 |
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