TWI264103B - A 3D electronic packaging structure with enhanced grounding performance and embedded antenna - Google Patents

A 3D electronic packaging structure with enhanced grounding performance and embedded antenna Download PDF

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Publication number
TWI264103B
TWI264103B TW94146062A TW94146062A TWI264103B TW I264103 B TWI264103 B TW I264103B TW 94146062 A TW94146062 A TW 94146062A TW 94146062 A TW94146062 A TW 94146062A TW I264103 B TWI264103 B TW I264103B
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electronic
package structure
electronic component
telecommunications
layer
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TW94146062A
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Chinese (zh)
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TW200725846A (en
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Ming-Chih Yew
Chien-Chia Chiu
Kou-Ning Chiang
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Kou-Ning Chiang
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
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    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6661High-frequency adaptations for passive devices
    • H01L2223/6677High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

This invention provides one kind of the 3D electronic packaging structure with enhanced grounding performance and embedded antenna. The packaging structure can be stacked thought the contact pads at the top and bottom surfaces. The grounding layers were fabricated at the bottom surface of the silicon wafer and facilitated the grounding for integrated circuit. Moreover, the packaging units could be fabricated as the wafer-level-packaging and reduce the fabrication cost. The signals from the packaged integrated circuits could also be carried by the patterned grounding layers. By using the through hole surrounding the integrated circuits, the electronic signals at the top and the bottom surfaces of the packaging can communicate. Therefore, the applications of the electronic packaging structure are improved. Besides, the interconnects formed in the grounding layers could have circular shape. By this method, the antenna can be embedded inside our electronic packaging structure with enhanced grounding performance.

Description

1264103 九、發明說明: 【發明所屬之技術領域】 本發明係有關一種電子封裝結構,特別是一種強化接地 、 特性與内埋天線型之立體堆疊封裝單元,此封裝單元中,於電 . 子元件基材背面具有單或複數層接地層,同時可藉由封裝單元 兩侧之電訊接點達到多晶片堆疊之目的。 現今電子產品多以符合小型化、高性能、高精度、高信 賴度、及南反應度等為目標,使電路元件之分佈密度過高、電1264103 IX. Description of the Invention: [Technical Field] The present invention relates to an electronic package structure, and more particularly to a three-dimensional stacked package unit with enhanced grounding, characteristics and embedded antenna type, in which the sub-element is The back side of the substrate has a single or multiple layers of ground layers, and the multi-wafer stacking can be achieved by the telecommunication contacts on both sides of the package unit. Today's electronic products are aimed at miniaturization, high performance, high precision, high reliability, and south reactivity, so that the distribution density of circuit components is too high.

• 路之體積大幅縮小,然而電子產品之電路愈精巧,則將有愈多 元件形成於微小空間中,故使彼此間電訊干擾機會上升,影響 電子產品訊號之穩定;其中又以電磁干擾(Electr〇magne^曰C lnt=rf叶ence,EMI)及雜訊為最常出現之問題。EMI之抑制主 ,刀為幸田射性(Radiated)與傳導性(Conducted)電磁干擾,幸畐 生EMI |直接經由開放空間傳遞,不須要經由任何傳輸介 ί 般僅能以遮蔽(Shieldin§)、接地(Grounding)等方式 =決,本發明所提出之強化接地躲之 有單或複數層接地層用以加ίΐί疊 • 纟之^兀之'氣特性’降低電磁干擾對高密度電子元件可靠 【先前技術】 6, 387〜2匕ί:露型!,晶”裝如美國專利第 之頂面設有一第一社$圖,该封裝1〇〇係於一基板102 片103上進行打線“電路晶—片103 ’並於該第一積體電路晶 積體電路晶片⑽旻數,並電性連接該第- 片103頂面塗佈反102 ’接者,於該第一積體電路晶 黏附於其頂面,同心^ Q5,可將—第二積體電路晶片106 门樣利用打線作業與複數焊、線107連接該第 5 1264103 m與該基板102之後,再利用-封裝膠108 邊基板m上且將各組件全部包覆其中,即完成一堆疊 ’積體電路晶片之封餘序。堆疊顏體電路賴將二個或二 ^隹&在一起並共用一基板,在增加晶片個數之同 、:空間;然而因晶片内部訊號之傳遞須透過焊線 梦姓二土 1 #了進行,易產生訊號延遲現象,同時由於此種封 I、、口構电轉遞路徑過長,若應用於高頻電子元件則易產生雜 吼,影響電子元件之電訊可靠度。 ’、 曰國in虎6,236,115中,揭露一種高密度積體電路 Γ ΐ、封:Γ構二;該封裝結構仍採用晶片堆疊方式 為I降低如前述利用焊線作為傳遞晶片間訊號時所可 月匕產生之讯號延遲現象,第一積體電路晶 用複數個導通孔裏形成於晶片中,同 古r屬化線路204,並配合具導電特性之固著結構 it獅可縮短晶片間傳遞路徑,然而因積體電 弁曰曰_ &佈讀上升,不囉類晶#彼賴電訊干擾機合上 升,將衫響電子產品訊號之穩定。 曰上 ^ 於具系統整合之多微電子元件堆疊電子 t、向頻通訊或致動感測器等電子結構模組 =封裝之技術成本,與達成封裝體積微小2二= ίϋ出—種高密度、高結構與電性可靠度,同時設計、紐壯• The volume of the road is greatly reduced. However, the more compact the circuit of the electronic product, the more components will be formed in the tiny space, so the opportunity for telecommunication interference increases, affecting the stability of the electronic product signal; among them, electromagnetic interference (Electr) 〇magne^曰C lnt=rf leaves ence, EMI) and noise are the most common problems. The main cause of EMI suppression is that the knife is Radiant and Conducted electromagnetic interference. Fortunately, EMI is transmitted directly through the open space. It does not need to be shielded by any transmission. Grounding (Grounding) and other methods = decision, the enhanced grounding proposed by the present invention has a single or multiple layers of grounding layer to increase the 'gas characteristics' of the • 叠 降低 降低 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 电磁 降低 降低 降低 降低 降低 降低 降低 降低 降低 降低 降低 降低Prior Art] 6, 387~2匕ί: exposed type, the crystal is mounted on the top surface of the U.S. Patent No.1, and the package is attached to a substrate 102 on the substrate 103 for wiring. The wafer 103' is formed on the first integrated circuit crystallized circuit chip (10), and electrically connected to the top surface of the first chip 103 to be coated with a reverse 102' connector, and the first integrated circuit is crystal-bonded. On the top surface, concentric ^ Q5, the second integrated circuit wafer 106 can be connected to the substrate 102 by a wire bonding operation and a plurality of soldering wires 107, and then the package substrate is used. On the m and all the components are covered, that is, complete a stack 'integration I order road closure wafer. Stacking the body circuit depends on two or two together and sharing a substrate, increasing the number of wafers, the space: however, because the internal signal transmission of the chip must be passed through the welding line dream surname 2 soil 1 It is easy to generate signal delay phenomenon. At the same time, due to the long path of the I and port structure, the application of high frequency electronic components is prone to noise and affect the telecommunications reliability of the electronic components. ', 曰国 in Tiger 6,236,115, reveals a high-density integrated circuit Γ ΐ, Γ: Γ 2; the package structure is still using the wafer stacking method to reduce I as the above using the wire as the signal between the transfer of the wafer The signal delay caused by the 积, the first integrated circuit crystal is formed in the wafer by a plurality of via holes, and the sturdy structure of the stalk can be shortened. However, due to the increase in the integrated electrical output _ & amps, the 干扰 晶 晶 # # 彼 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电曰上^ In the system integration of multi-microelectronic components stacked electronic t, to the frequency communication or actuating sensors and other electronic structure modules = the technical cost of the package, and to achieve a small package volume of 2 2 = high density, High structure and electrical reliability, simultaneous design, New Zhuang

I依=巧求功能作適當彈性調整之多微電子轉封K 構,貝為當前急需解決的問題。 了衣、、、口 1264103 【發明内容】 鑑; 電子封及衫統整合之乡微電子树堆疊 組之趨勢,以;=細^ 種具 電路 多會種電子封I结構,其目的在於提供一 Η素St件之晶圓級封裳單元體,其上下表面且連接· 疊封裝触率=赠遞路鶴時咖提升此堆 明之另—目的在於提供—種電 之另—目的在贿供—種電子縣結構,爷封狀 y氣特性,故啊低電磁干擾對高密度電子元件 為達成前述目的,本發明所提出之電子 I ; "ί^ίϊΓ^^ 佈於前述電子元件之四周。單或複數層接地屛,^ ^域分 ,件基材之背面。單或複數個導通孔’ 域,且於該導通孔内或孔壁填充具導電特性之材料,衝& 衝區域之上表面與前述接地層間具有電訊連通之特性吏=緩 數個電訊通道,形成於前述電子封裝結構之單側或早$ 複數個電訊接點,形成於前述電訊通道之末端,且1或 電子封裝結構之單侧或雙侧。 77布於前述 1264103 本發明之前述盥苴I rely on the multi-microelectronics reversal K structure, which is the function of the flexible adjustment, which is an urgent problem to be solved. The clothing, the mouth, the mouth 1264103 [Invention content] Jian; electronic seal and shirt integration township microelectronic tree stacking group trend; to = ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The wafer-level sealing unit of the St素St-piece, its upper and lower surfaces and the connection and stacking of the package rate = the gift of the road cranes to enhance this pile of the other - the purpose is to provide - another kind of electricity - the purpose of bribery - The electronic county structure, the y-characteristic characteristics of the yoke, so low electromagnetic interference for the high-density electronic components to achieve the above purpose, the present invention proposed by the electronic I; " ί ^ ϊΓ ^ ^ ^ cloth around the aforementioned electronic components. Single or multiple layers of grounding 屛, ^ ^ domain points, the back side of the substrate. a single or a plurality of via holes' domains, and a material having a conductive property is filled in the via holes or in the hole walls, and the surface between the upper surface of the punching region and the ground layer has a telecommunication connection characteristic = a plurality of telecommunication channels, Formed on one side of the electronic package structure or a plurality of telecommunication contacts, formed at the end of the telecommunications channel, and 1 or one side or both sides of the electronic package structure. 77 is laid out in the foregoing 1264103.

^ t ® ^ T 【實施方式】 種強構。詳^,树籠出一 之電訊接點達到多晶片心此封裝=兀可藉由兩側 如下,唯所述之較佳實施例ρ口 1、σ亥發明之貫施例詳細說明 一 仏貝轭例^、做一說明,並非用以限定本發明。 三β圖1^封裝單元體3〇0之截面圖,亦為 素可d錫截r r電子元件基材318其材料組成元 之組合,_ =具轉體特性元素 形成於電子元_===2;^^牛層313 被動雷早分丛A , 工々包千凡件可為主動電子元件、 ;13電=為-緩衝區域(W中未特念; 於其中,故於本歸利用 為 310可^用1顧面形成電連通路;第二導通孔 方式形i^射鑽孔、乾遂式韻刻或其他適合之 ^合鎳、姥、鎢或以上金屬材料合金或他種具導電性之材丄 觸墊313上方佈有第—接觸墊期與第二接 一電子元件4層’位於第 他適合之方m、/ ❻、騎训7以滅鍍、電鍍或其 路訊穿重新^成:亚將位於第一、二接觸塾(309、306)之電 …斤刀佈,弟-覆蓋層304與第二覆蓋層3〇5可合而為 8 1264103 程除3高封裝單元表面之平坦性,並可於其間進 ]口系化衣私,形成弟二内導線 化前述之電路訊號重佈,增加第」一 ^孔308 ’強 時之應用性。 ㈢弟封衣早兀體300於進行堆疊 電子元件接地層311形成於第一 屬材銅,鐵、=金= 子元件之接地#因士:陡之材料的組合’該金屬層除作為電 幫助g守為一熱之良導體,具有導熱之特性,可 ===層313所產生之齡該電子元件: 合之方式形錢鑽孔或其他適 成於第一封Ξ單元體與第二電路保護層批形 “接點315、弟四電訊接點316之位 二=一 上利用網版印刷、模板印刷 亚=讀電訊接點 術或其他適合之方式形成“塗佈、微影技 明)。具電訊傳遞之難㈣°Qnf』保4層(圖三中未特別標 層上’用以連接第—封裝=體3〇JU前述之電訊接點保護 訊號。 才衣早兀體300與其他電子設備間之電路 其傳可如内之電路訊號, 第二導通孔以件第:内導線層勝 一封裝單元體3〇〇之下夺面)·二、μ弟—甩讯接點315 (第 導線層317—第—電訊接點’ ^ —接觸塾第二内 (第一雜單元體電訊傳遞之固著結構301 之電訊可如前^傳電子元件層加中 邪堆疊切叙妨;麵讀佳於 9 1264103 並非用以限定本發明。 /圖二B為對應於圖三A,本發明第一實施例之可 ^爲便 =說明,此圖中忽略圖三A中之第二電路保護層312。 地層311經圖案化製程後,形成第-電訊通道 327」圖三B中無法顯示第—封裝單元體3〇〇上表面1第一 子j層313,故利用虛線部份表示。第一電子元件層313内 3==可經由第三導通孔322傳遞至電子元 早兀體300之周圍,可利用第三電訊通道犯6與第二電7占 314相連接,達到配置電訊接點位置之目的。電子元地声 =1經圖案化製程後亦可形成如第五電訊接點323之測試專^ 並i封裝結構内部電子元件之測試域相連通,形t 一ίίίί结構;另,該瞧化製程可形成無線訊 ,接收天線324 ’儀此具有環麵繞型態之電賴道 單元/ 具村齡卜界骑鱗tfl賴遞之特 。然刖奴較佳實施_構只做—綱,並_以限定本發 八A為本發狀帛—實施嫩奸元件紐上之可能 =i=。ϊ上視圖中,晶圓4〇°上佈有複數個= 之強化接地特性立體堆疊封裝單元,放大 ”弟四a子讀層480,電子元件層間之猶 如機械鑽孔、雷射鑽孔、乾座式峨其他LSI : 第二導侧2 ;第—電子元二方= 循第;内導線層4〇4至第二導_ 士匕該之方式’進行封裝單元下表面電訊接點』己用置= 守,弟一笔子兀件層460内部之電訊可由第二接觸塾,= 1264103 用如圖三A第-實施例中之敘述方式 電訊接點配置。前述之封裝單元體皆於 完成,故可降低單-封料元體之製本, =割晶圓侧,完成本發明之強化接地特性立®體刀堆= μ圖ΠΛ對顧四A之放A_,本發日㈣—實施例於 電子兀件基材上之可能截面圖。電子有雷 :;:1^ 壯早兀即利用此緩衝區域中,扣除第二導通孔搬位= 部份^丁晶圓切割’如圖中之晶圓切割道棚所示;前述之 佳實施例結構只做-說明,並非用以限定本發明。 x 圖五A為晶圓堆疊示意圖,第一晶圓5〇1盥 上皆佈有複數個本發明之接地難立断疊封^元 晶圓之分割亦可於晶關完成堆疊程序後進行;如圖五b g Ϊ二Ϊ:為ϊίΐ A:,堆疊後進行切割程序之侧視圖; Ϊ 層ΙΓ弟二電子疋件層560位於第二晶圓502 501上,一電子元件層55〇與第三電子元件層57〇間之g 訊號可猎由第-具電訊傳遞之固著結構5G5做傳遞, 電子兀件層_與第四電子元件層5_之電路訊號 ^ -具電訊傳遞之m著結構506進行傳遞,晶圓切割道5()7曰用以 i!!i圓並形成本發明之強化接地特性立體堆疊封裝結構,如 圖六中所不。 圖六為本發明之第二實施例,為利用本發明之封 形式堆疊封裝之截面示意圖。第一封裝單元體J中 八有弟一電子兀件層605 ’第二封裝單元體62〇中具有第二電 1264103 子兀件層606,位於兩電子元件層中之電路訊 電訊傳遞之固著結構604進行傳 ^ =點 6〇2,利用第-具電訊傳遞之固著結構I ^使 封裝單元體62G與基板6(31形成電訊導通衣進 進行第圖^^^^^^實齡彳’為彻本發日狀封裝單元 710'^ t ® ^ T [Embodiment] A strong structure. Detailed ^, the tree cage out of a telecommunications contact to reach the multi-chip heart this package = 兀 can be as follows by the two sides, only the preferred embodiment ρ mouth 1, σ hai invention example to explain a mussel The conjugate example is not intended to limit the invention. The cross-sectional view of the package body 3〇0 of the ββ11 is also a combination of the material composition elements of the base material 318 of the primed tin tin rr electronic component, _=the element with the rotating body is formed in the electronic element _=== 2; ^^ cattle layer 313 passive lightning early cluster A, workmanship can be active electronic components, 13 electricity = for - buffer area (W is not special; in it, it is used in this 310 can be used to form an electrical communication path with a face; the second conductive hole is shaped by a hole, a dry-type rhyme or other suitable alloy of nickel, tantalum, tungsten or the like or a conductive material thereof The material is placed on the top of the contact pad 313 with the first contact pad and the second layer of the electronic component. The layer 4 is located on the side where it is suitable for the m, / ❻, and the riding 7 to extinguish the plating, electroplating or re-transfer. ^成: Asia will be located in the first and second contact 塾 (309, 306) electric ... knives cloth, the brother - cover layer 304 and the second cover layer 3 〇 5 can be combined to 8 1264103 process 3 high package unit surface The flatness can be used to enter the mouth of the system, and the circuit signal of the second wire is formed in the second wire to increase the applicability of the first hole 308 'strong. The clothing body 300 is formed on the stacked electronic component ground layer 311 formed in the first genus copper, iron, = gold = sub-component grounding #因士: the combination of the steep material 'the metal layer except the electric help g A good conductor of heat, with the characteristics of heat conduction, can be === the age of the layer 313. The electronic component: the way of drilling or other suitable for the first sealed unit body and the second circuit protective layer batch Shape "contact 315, brother four telecommunications contacts 316 bit two = one using screen printing, stencil printing sub = reading telecommunications joints or other suitable way to form "coating, lithography technology." Difficult to telecommunications (4) °Qnf』protect 4 layers (not shown on the special layer in Figure 3) to connect the first package = body 3〇JU aforementioned telecommunications contact protection signal. 才衣早兀体300 and other electronics The circuit between the devices can be transmitted as the circuit signal inside, the second via hole is the piece: the inner wire layer wins over the package unit body 3〇〇, and the second wire is connected to the surface of the package unit. Layer 317—the first telecommunications contact' ^—contacts the second inner part (the telecommunication of the fixed structure 301 of the first miscellaneous unit telecommunication transmission can be as before the electronic component layer plus the middle evil stacking and cutting; 9 1264103 is not intended to limit the present invention. / Figure 2B corresponds to Figure 3A. The first embodiment of the present invention can be described as a description. In this figure, the second circuit protection layer 312 in Figure 3A is omitted. After the formation 311 is patterned, a first-telecom channel 327 is formed. The first sub-j layer 313 of the upper surface 1 of the first package unit body 3 cannot be displayed in FIG. 3B, and thus is indicated by a broken line portion. 3== in the element layer 313 can be transmitted to the periphery of the electronic cell early body 300 via the third via hole 322, and can be utilized The third telecommunications channel commits 6 and the second electrical 7 314 are connected to achieve the purpose of configuring the location of the telecommunications contact. The electronic component ground sound=1 can also form a test of the fifth telecommunications contact 323 after the patterning process. The test domain of the internal electronic components of the i package structure is connected to each other, and the structure is formed by a t-shaped process; in addition, the deuteration process can form a wireless communication, and the receiving antenna 324' has a toroidal winding type electric channel unit/village age Bu 骑 骑 t t t t t t t t t 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳In the upper view, the wafer 4〇 is covered with a plurality of reinforced grounding characteristics three-dimensional stacked package unit, and the “fourth sub-reading layer 480” is enlarged, and the electronic component layers are like mechanical drilling, laser drilling, and dry seat.峨 other LSI: second guide side 2; first - electronic element two side = cycle; inner wire layer 4 〇 4 to second guide _ 士 之 匕 匕 ' 进行 进行 进行 进行 进行 进行 进行 进行 进行 进行 ' ' = Shou, the telecommunications inside the inner layer 460 can be used by the second contact 塾, = 1264103 as shown in Figure 3A In the example, the telecommunications contact configuration is described. The above-mentioned package unit body is completed, so that the cost of the single-sealing element body can be reduced, = the wafer side is cut, and the enhanced grounding characteristic of the present invention is completed. ΠΛ图ΠΛ对顾四A的放 A_,本发日(四)—The possible cross-section of the embodiment on the electronic component substrate. The electron has a thunder:;:1^ Strong early, use this buffer field, deduct the first The two-via hole relocation = partial wafer cutting is shown in the wafer dicing shed in the figure; the preferred embodiment structure described above is only for the purpose of illustration and is not intended to limit the invention. x Figure 5A is crystal The circular stacking diagram, the first wafer 5〇1盥 is provided with a plurality of grounding difficult vertical stacking of the present invention, and the division of the wafer can also be performed after the completion of the stacking process by the crystal; as shown in FIG. 5bgΪ二Ϊ: ϊίΐ A: a side view of the cutting process after stacking; Ϊ layer two electronic device layer 560 is located on the second wafer 502 501, an electronic component layer 55〇 and the third electronic component layer 57 The g signal can be transmitted by the fixed structure 5G5 of the first telecommunications transmission, the electronic component layer _ and the fourth electric The circuit signal of the component layer 5_ is transmitted with the structure 506 of the telecommunication transmission, and the wafer scriber 5 () 7 曰 is used for the i!!i circle and forms the three-dimensional stacked package structure of the enhanced grounding feature of the present invention, such as Not in Figure 6. Figure 6 is a schematic cross-sectional view showing a second embodiment of the present invention for stacking packages in the form of a package of the present invention. The first package unit body J has an electronic component layer 605. The second package unit body 62 has a second electrical 1264103 sub-layer 606, and the circuit telecommunications transmission is fixed in the two electronic component layers. The structure 604 transmits ^=6〇2, and the package unit body 62G and the substrate 6 are formed by the fixing structure I ^ of the first telecommunications transmission (31) forms a telecommunications guide into the figure. ^^^^^^^ 'For the hairpin package unit 710'

位置皆具有電訊接點,其中第兩側相對應 元體720間之電路訊號可藉^^體=與弟二封裝單 行傳遞,另第二封褒單元體7曰沖、电5孔傳遞之固著結構進 路訊號,可以具封裝單元體73〇間之電 強化接地特性之立體堆^封二撕7G6進行傳遞。本發明之 可進行圖案化之金屬層^層 =3=、结構下表面具有The locations all have telecommunication contacts, wherein the circuit signals between the two sides corresponding to the body 720 can be transmitted by the ^^ body = the second package of the second package, and the second package unit 7 is rushed and the 5 holes are transmitted. The structure access signal can be transmitted by the three-dimensional stacking and sealing 7G6 of the electrical strengthening grounding property of the package unit body 73. The patterned metal layer of the present invention = 3 =, the lower surface of the structure has

遞之與第,U 7〇2 ,利用第一具電基板™,有_妾點 之固著結構704,可使第二封裝703與=二具電訊傳遞 H第三封裝單元體㈣態f =電單元體 2豐封裝之目的’同時爲提高封裝。’進而達 =705可施加於具電訊傳遞之:^ I罪度,接合 第之=以; 第一封裝封裝‘體= ”弟一批早讀820間利用具電訊傳遞 12 1264103 :ίί♦斗805進行訊號傳遞,同時第一封裝單元體810與第 間利用第二具電訊傳遞之固著結制4進行 遞之上具有電訊接點觀’ _第—具電訊傳 可使第一封裝單元體810,第二封裝單元 達成堆疊元體830與基板8〇1形成電訊導通,進而 脫離;ifr較 1 圭實施例說明如上,而熟悉此領域技藝,在不And the U 7〇2, using the first electrically-on substrate TM, having a _ 妾 fixed structure 704, can make the second package 703 and = two telecommunications transfer H third package unit body (four) state f = The purpose of the electric unit body 2 is to improve the package. ' Further up to = 705 can be applied to the telecommunications transmission: ^ I sin, the joint of the = =; the first package package 'body = 》 a group of early reading 820 use telecom transfer 12 1264103 : ίί 斗 805 Signal transmission is performed, and the first package unit body 810 and the second fixed transmission system 4 with the second telecommunications transmission have a telecommunication contact point _ the first telecom transmission enables the first package unit body 810 The second package unit reaches the stacking body 830 and the substrate 8〇1 to form a telecommunications conduction, and then detached; ifr is the same as the first embodiment, and is familiar with the art, not

範圍更二$精神範當可做些許更動潤飾,其專利保護 耗圍更备視伽之申料利範圍及其等同領域而定。 【圖式簡單說明】 之祕實_將於下述說明中輔以下删形做更詳細 圖-為習知堆4型積體電路晶片職結構之示意圖。 圖一為習知以晶圓鑽 結構之不意圖。 孔方式形成之高密度積體電路晶片封裝The scope is even more. The spirit of the spirit can be used to make some changes, and the patent protection is more dependent on the scope of the application and the equivalent fields. [Simple description of the schema] The secrets of the following figure will be more detailed in the following description. Figure 1 is a schematic view of a conventional wafer-drilling structure. High-density integrated circuit chip package formed by hole mode

圖三B為對應於圖三A’本發明第—實施例之可能底視圖。 本發明H關於電子元錄壯之可能分佈 施例於電子元 圖四B為對應圖四八之放大區域,本發一杏 件基材上之可能戴面圖。 貝 圖五A為晶圓堆疊示意圖。 圖五B為對應圖五a 晶圓堆疊後進行切割程序之側視圖。 13 1264103 元進行第 元進行第 圖七為本發明之第三實施例,為利用本發明之封 二形式堆疊封裝之截面示意圖。 又 ®八為本發明之第四實施例,為利用本發明之 的 三形式堆疊封裝之截面示意圖。 衣早 【主要元件符號說明】 100堆疊型積體電路晶片封裝 102基板 103 第一積體電路晶片 104焊線 105 黏著層 106第二積體電路晶片 107焊線 封裝膠 201 第一積體電路晶片 202第二積體電路晶片 203 第三積體電路晶片 204金屬化線路 205固著結構 206 導通孔 300第一封裝單元體 3〇1具電訊傳遞之固著結構 302第一電訊接點 303 第一電路保護層 304第一覆蓋層 305 弟二覆蓋層 1264103Figure 3B is a possible bottom view of the first embodiment of the present invention corresponding to Figure 3A'. The present invention relates to the possible distribution of electronic components. Example 4B is an enlarged area corresponding to the image of Fig. 48, and a possible wearing surface of the substrate of the present invention. Figure 5A is a schematic diagram of wafer stacking. Figure 5B is a side view of the cutting process performed after stacking the wafers corresponding to Figure 5a. 13 1264103 is carried out for the first embodiment. FIG. 7 is a cross-sectional view showing a third embodiment of the present invention, which is a package package using the sealed form of the present invention. Further, the eighth embodiment is a fourth embodiment of the present invention, which is a schematic cross-sectional view of a three-piece stacked package using the present invention.衣早【Main component symbol description】100 stacked integrated circuit chip package 102 substrate 103 first integrated circuit wafer 104 bonding wire 105 adhesive layer 106 second integrated circuit wafer 107 wire bonding adhesive 201 first integrated circuit chip 202 second integrated circuit chip 203 third integrated circuit chip 204 metallization line 205 fixed structure 206 via 300 first package unit body 3 电 1 with telecommunication transmission structure 302 first telecommunication contact 303 first Circuit protection layer 304 first cover layer 305 second cover layer 1264103

306 第二接觸墊 307 第一内導線層 308 第一導通孔 309 第一接觸墊 310 第二導通孔 311 電子元件接地層 312 第二電路保護層 313 第一電子元件層 314 第二電訊接點 315 第三電訊接點 316 第四電訊接點 317 第二内導線層 318 電子元件基材 321 第一電訊通道 322 第三導通孔 323 第五電訊接點(測試接點) 324 無線訊號接收天線 325 第二電訊通道 326 第三電訊通道 327 第四電訊通道 400 晶圓 401 第一接觸墊 402 第二導通孔 403 晶圓切割道 404 第一内導線層 405 具電訊傳遞之固著結構 406 第一電訊接點 407 電子元件基材 408 緩衝區域 15 1264103306 second contact pad 307 first inner conductor layer 308 first via hole 309 first contact pad 310 second via hole 311 electronic component ground layer 312 second circuit protection layer 313 first electronic component layer 314 second telecommunications contact 315 Third telecommunications contact 316 fourth telecommunications contact 317 second inner conductor layer 318 electronic component substrate 321 first telecommunications channel 322 third via hole 323 fifth telecommunications contact (test contact) 324 wireless signal receiving antenna 325 Second telecommunication channel 326 third telecommunication channel 327 fourth telecommunication channel 400 wafer 401 first contact pad 402 second via hole 403 wafer dicing street 404 first inner wire layer 405 fixed structure 406 with telecommunication transmission first telecommunication interface Point 407 electronic component substrate 408 buffer area 15 1264103

409 第二接觸墊 430 放大區域 450 第一電子元件層 460 第二電子元件層 470 第三電子元件層 480 第四電子元件層 501 第一晶圓 502 弟二晶圓 505 第一具電訊傳遞之固著結構 506 第二具電訊傳遞之固著結構 507 晶圓切割道 550 第一電子元件層 560 第二電子元件層 570 第三電子元件層 580 第四電子元件層 601 基板 602 電訊接點 603 第一具電訊傳遞之固著結構 604 第二具電訊傳遞之固著結構 605 第一電子元件層 606 第二電子元件層 610 第一封裝單元體 620 第二封裝單元體 701 基板 702 電訊接點 703 第一具電訊傳遞之固著結構 704 第二具電訊傳遞之固著結構 705 接合材料 706 具電訊傳遞之接合材料 16 1264103 707 第三具電訊傳遞之固著結構 708 第四具電訊傳遞之固著結構 709 第一電訊通道 710 第一封裝單元體 720 第二封裝單元體 730 第三封裝單元體 801 基板 802 電訊接點 803 第一具電訊傳遞之固著結構 804 第二具電訊傳遞之固著結構 805 具電訊傳遞之接合材料 810 第一封裝單元體 820 第二封裝單元體 830 第三封裝單元體409 second contact pad 430 enlarged area 450 first electronic component layer 460 second electronic component layer 470 third electronic component layer 480 fourth electronic component layer 501 first wafer 502 second wafer 505 first telecommunications transmission solid Structure 506 second telecommunication transmission fixing structure 507 wafer cutting lane 550 first electronic component layer 560 second electronic component layer 570 third electronic component layer 580 fourth electronic component layer 601 substrate 602 telecommunications junction 603 first Fixing structure with telecommunication transmission 604 second fixing structure of telecommunication transmission 605 first electronic component layer 606 second electronic component layer 610 first package unit body 620 second package unit body 701 substrate 702 telecommunication contact 703 first Fixing structure with telecommunication transmission 704 second fixing structure of telecommunication transmission 705 bonding material 706 bonding material with telecommunication transmission 16 1264103 707 third fixing structure of telecommunication transmission 708 fixing structure of fourth telecommunication transmission 709 First telecommunications channel 710 first package unit body 720 second package unit body 730 third package unit body 801 substrate 802 telecommunications Contact 803 First telecommunication transmission fixing structure 804 Second telecommunication transmission fixing structure 805 Telecommunications transmission bonding material 810 First package unit body 820 Second package unit body 830 Third package unit body

1717

Claims (1)

1264103 十、申請專利範圍: 1. 一種電子封裝結構,至少包含: 單或複數層用以形成電子元件之基材; 單或複數個電子元件,形成於前述電子 元件之總表面積小於或等於前述電子元件美^^才=該電子 單或複數個接觸墊,佈於前述電子元件之表面;表面知, 單或複數個緩衝區域,該緩衝區域分佈於前、述電 :或?數層接_ ’軸於前述t子元件基材 牛之四周’ 單或複數辦通孔,形成於前猶衝 ’ 孔壁填充具導電特性之材料,使前述 ===或 接地層間具有電訊連通之特性; 釘次之上表面與前述 ίίΐΓΐ訊通道’形成於前述電子封裝結構之單側或雔側; 單或稷數個黾訊接點,形成於前述電訊通道 —又, 前述電子封裝結構之單側或雙側uκ通道之料,且分佈於 2. 如申請翻翻第1項之電子封裝結構, 封裝結構兩侧之電訊通道,可利用前述之導通隹匕於電子 遞,使位於該電子封裝結構_之钱通道形成通路^電訊傳 it申ϊ專=範圍第1項之電付裝結構,其中所述用以μ -电子^件之基材,其材料組成元素可為石夕、錄、錫、二1 上元素之混合或與他種具半導體特性元素之組合。人 ^如申請專種_〗項之電子縣結構,射所 ^材料與前述電子元件基材相同,且機衝區域内子衝^ 基材不用以形成㈣翻翻第1射所述之電子元件。70件 5.如申請專利範|5第〗項之電子龍結構,射 件可為主前子元件、被動電子元件、❹!元件、測試 18 1264103 微機電晶片或以上電子元件之組合。 6·如申凊專利範圍第1項之雷子 可為銅m idftH中所述之接地層, 導電性之材料的組合。 5上i屬材料合金或他種具 7·如申睛專利範圍第1項電 亦為-熱之㈣體,具有導^構,其情述之接地層 第i項之電子封裝結構,其中所述之接地層, 將電訊通道^於爛、#射鑽孔或其他適合之方式, 道’其中所述之電訊通 外界進行無線訊號傳遞^=、、丄%下’電訊通道具有可與 ^如^專纖圍第1項之電子難結n巾所述之導通 方式;成機械·、f _孔、乾溼式_或其他適合之 2·,如項之電子封裝結構,其中所述之導通 轉、鍺、鶴或以上金屬材料合金或他種具導電;之::的組:。 丨項之電子封裝結構,其中所述之電訊接 微影技術料他:高人:!、模板印刷、滾筒式塗佈、喷墨塗佈、 次/、他適合之方式形成電訊接點保護層。 19 1264103 如申^利範圍第丨項之電子封裝結構,其中所述之電 與前述封裝結_部電子元件之峨喊相 妒 一具測試功能之電子封裝結構。 &成 至少包 含 =..一種減_單讀之立齡疊電子封裝結構, 複數層用以形成電子元件之基材; 稷,個電子元件,形成於前述電子元件 =表面積小於於前述電子元件紐之/面積且^子疋件 禝數個接觸墊,佈於前述電子元件之表面· 、 ,數個緩衝區域’該緩衝區域分佈於前述電子 稷數層接地層,形成於前述電子元件紐 °, 複數個導通孔,形成於前述緩衝區域,且 填充具導電特性之材料,使前述緩衝區域之或孔壁 層間具有電訊連通之特性; — 表面與則述接地 複數個電成通道,形成於前述電子封梦纟 複數個賴無,職於_魏^、^早=·, 電子封裝結構之單側或雙側; 禾鳊且刀佈於前述 複數個固著結構,形成於前述之電訊接點。 15. 如申請專利範圍第14項 電子封裝結構,其巾所述位^ 體之立體堆疊 可利用前述之導通孔進行電‘η:構兩側之電訊通道, 通路。 $轉遞’使_側之電訊通道形成 16. 如申料纖_ 14項 電子封裝結構,其中輯 、赠之立體堆疊 固著結構以及導通孔,於進兩側之電訊通道、 封裝單元體内部電訊傳遞:媒隹η可曰做為單— ’、 亦可提供複數個封 20 1264103 裳單元體間,内部電子元侔 电于讀之電崎行賴時之路經。 錫、碳,或以上:3ίί:與 成元素可為>5夕、鍺 導體特性元素之組合 17.如申請專利範圍第 f子封裝結構,射所_ 封之立體堆疊 成元去可炎π ^ ^ 乂攻电子兀件之基好,甘 18.如申請專利範園第ι4 f=封裝結構,其t所述之緩衝之立體堆疊 相同’且該緩衝區域内之電=難—電子元件基材 圍第1項帽叙電子元件子70件麵不用·成申請專利範 之組合。 2♦感測元件、測試元件、微機ί;片動以子= 元體之立體堆疊 金 I呂、钻 、或以上金屬材料合金或他種具導電 21·如申請專利範圍第14項之且 結構,其中所述之接地層亦為—Hg之立體堆叠 熱之特性。 …、之良導體,具有導 範圍第14項之具複數個封事單-电子封裝結構,其中所述之接地声,J衣早7C體之立體堆疊 式綱、雷射鑽孔或其他適合之;用如機械加工、乾座 地層。 X ’ f㉝通道形成於該接 1264103 23.如申晴專利範圍第Μ項之 壯 通道可具有環型圍繞之型態,該圍繞=1,’,中所述之電訊 與外界進行無線喊傳叙雜。〜,賴通道具有可 電子元狀立體堆疊 鑽孔、乾洚或益办丨# * Λ, A」 了和用如機械鑽孔、 乾溼式蝕刻或其他適合之方式形成 雷射 電子封裝具複數個封料元體之立體堆疊 模板印刷、滾^2^電訊接點’其上可姻網版印刷、 式形成電訊接點保護層。贺墨塗佈、微影技術或其他適合之方 ;7·如申請專利範圍第w 接點’可與前勒樣結翻結構’其中所述之電… 成一具峨舰之好件之測試滅相連通,形 訊1264103 X. Patent application scope: 1. An electronic package structure comprising at least: a single or multiple layers for forming a substrate of electronic components; a single or a plurality of electronic components, the total surface area formed on the electronic components being less than or equal to the aforementioned electrons The component is ^^^== The electronic single or a plurality of contact pads are disposed on the surface of the electronic component; the surface is known, single or plural buffer regions, and the buffer region is distributed in the front, and the electricity is: or? The number of layers connected to the 't-axis of the t-element substrate around the cow' single or multiple through-holes, formed in the front of the 冲 ' ' hole wall filling with conductive properties of the material, so that the above === or grounding layer with telecommunications The top surface of the nail and the aforementioned ίίΐΓΐ channel are formed on one side or the side of the electronic package structure; a single or a plurality of contact points are formed in the telecommunication channel—and the electronic package structure Single-sided or double-sided uκ channel material, and distributed in 2. If you apply to turn over the electronic package structure of item 1, the telecommunication channel on both sides of the package structure can use the above-mentioned conduction to be electronically transferred to make the electron The package structure _ the money channel formation path ^ telecommunications transmission ϊ ϊ = = = range of the first item of the electrical assembly structure, wherein the substrate for the μ - electronic components, the material composition of which can be Shi Xi, recorded A combination of elements on tin, tin, or a combination of elements of semiconductor properties. If the application is for the electronic county structure of the special type _〗, the material is the same as the substrate of the electronic component, and the substrate is not used to form (4) flipping the electronic component described in the first shot. 70 pieces 5. If the electronic dragon structure of the patent application model 5 is used, the projectile can be a combination of the front sub-component, the passive electronic component, the ❹! component, the test 18 1264103 MEMS wafer or the above electronic components. 6. The thunder of claim 1 of the patent scope can be a combination of a grounding layer and a conductive material as described in copper m idftH. 5 i is a material alloy or his species 7 · If the scope of the patent scope of the first item is also - the heat (four) body, with a guide structure, the grounding layer of the i-th electronic package structure, which The grounding layer, the telecommunications channel is in the rotten, #射钻钻 or other suitable way, the road described in the telecommunications outside the wireless signal transmission ^ =, 丄% under the 'telecom channel has ^Special fiber around the first item of the electronic difficult knot n-way described; the mechanical, f _ hole, dry and wet _ or other suitable 2, such as the electronic package structure, wherein the conduction Turn, smash, crane or above metal alloy or his species with electrical conductivity; The electronic package structure of the item, in which the telecom connection lithography technology is expected to be: Gao Ren:! , stencil printing, roller coating, inkjet coating, secondary /, he is suitable to form a telecommunication contact protection layer. 19 1264103 The electronic package structure of the third item of claim 2, wherein the electrical power is combined with the scream of the electronic component of the package to form a test package electronic package structure. & at least comprising =.. a reduced-single-reading stacked electronic package structure, a plurality of layers for forming a substrate of the electronic component; 稷, an electronic component formed on the electronic component = surface area smaller than the aforementioned electronic component a plurality of contact pads, which are disposed on the surface of the electronic component, and a plurality of buffer regions. The buffer region is distributed on the ground layer of the electronic layer, and is formed in the electronic component. a plurality of via holes formed in the buffer region and filled with a material having a conductive property to have a communication connection between the buffer region or the hole wall layer; - a surface and a grounding plurality of electrical channels formed in the foregoing The electronic seal of the nightmare is based on one or both sides of the electronic package structure; the cymbal and the knife are placed on the aforementioned plurality of fixed structures, formed in the aforementioned telecommunication contacts . 15. For the electronic package structure of the 14th item of the patent application, the three-dimensional stack of the body of the towel can use the above-mentioned through holes to electrically connect the telecommunication channels on both sides of the structure. $Transfer's the _ side of the telecommunications channel formation 16. For example, the material fiber _ 14 electronic package structure, which is a series of three-dimensional stacking fixed structure and via holes, on both sides of the telecommunication channel, inside the package unit Telecommunications: The media 隹 can be used as a single--, and can also provide a plurality of seals 20 1264103 between the body of the body, the internal electronic 侔 侔 于 读 电 电 电 。 。 。 。 。. Tin, carbon, or above: 3 ίί: combination with the element can be >5 锗, 锗 conductor characteristic element 17. As claimed in the patent scope f sub-package structure, the _ seal of the three-dimensional stacking into the element can be inflammatory π ^ ^ The basis of the electronic component is good, Gan 18. If you apply for the patent model, the ι4 f= package structure, the buffered three-dimensional stack is the same 'and the electric energy in the buffer area is difficult - electronic component base The first item of the material enclosure is 70 pieces of electronic components. 2 ♦ sensing element, test element, microcomputer ί; slice moving with sub-body three-dimensional stacking gold I Lu, drill, or above metal alloy or his kind of conductive 21 · as claimed in the scope of the 14th and structure The ground layer is also characterized by a three-dimensional stack heat of -Hg. ..., a good conductor, with a range of 14th item, a plurality of sealed orders - electronic package structure, wherein the grounding sound, J clothing early 7C body three-dimensional stacking class, laser drilling or other suitable Use such as machining, dry grounding. The X ' f33 channel is formed in the connection 1264103. 23. The strong channel of the third paragraph of the Shen Qing patent scope may have a ring-shaped surrounding type, and the surrounding telecommunication, the telecommunications described above, and the outside world wirelessly shout miscellaneous. ~, Lai channel has an electron-elements three-dimensional stacking of drilling, cognac or 丨 丨 # * Λ, A" and using a mechanical drilling, dry-wet etching or other suitable way to form a laser electronic package The three-dimensional stacking stencil printing of the sealing material body, the rolling ^2^ telecommunications contact' can be printed on the screen, forming a telecommunication contact protection layer. Hemo coating, lithography technology or other suitable side; 7·If the patent application scope w contact 'can be combined with the former sample-like structure', the electricity described therein... The test of a good piece of the ship Connected
TW94146062A 2005-12-23 2005-12-23 A 3D electronic packaging structure with enhanced grounding performance and embedded antenna TWI264103B (en)

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TWI484616B (en) * 2011-10-06 2015-05-11 Adl Engineering Inc Package module with emi shielding
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