TWI453873B - Stacked semiconductor package structure - Google Patents

Description

Stacked semiconductor package structure

The present invention relates to a package structure, and more particularly to a stacked semiconductor package structure.

As electronic products become shorter and lighter, the boards within them become smaller and smaller, so that the area available for component placement on the board is also reduced. In the past, a plurality of wafers can be directly bonded to a circuit board in a side-by-side manner, which is gradually impossible to achieve in advanced miniaturized electronic products. Therefore, it has been developed to vertically stack a plurality of wafers, which is called a package-on-package device (POP). Here, a surface mount technology (SMT) process is used to integrate different wafer stacks on the same substrate to meet the requirements of small joint area and high density component placement.

Moreover, with the rapid increase in demand for electronic product functions and applications, many advanced packaging technologies have been developed, such as flip chip, chip scale package (CSP), wafer level package, and three-dimensional package (3D). Package) technology, etc.

The three-dimensional packaging technology integrates wafers and passive components into a single package and can be a solution for System In Package (SIP). The three-dimensional packaging technology can combine multiple wafers in a side-by-side manner, a stacked manner, or both. The three-dimensional package has the advantages of small footprint, high performance and low cost.

Since the wafers are arranged in a layered manner, heat dissipation and ground shielding are one of the problems that affect the acceptance of the three-dimensional package.

The stacked semiconductor package structure includes a first package, a plurality of first connection conductors, a second package, an electronic functional module, a plurality of second connection conductors, and a patterned layer of thermally conductive material.

The first package includes a first circuit board, at least one first wafer, and a first sealant. The first chip is located on the upper surface of the first circuit board and electrically connected to the first circuit board. The first glue is located on the upper surface of the first circuit board and encapsulates the first wafer.

The first connection conductor is located on a lower surface of the first circuit board. Each of the first wafers is electrically coupled to the at least one first connecting conductor.

The second package includes a second circuit board, at least one second wafer, and a second sealant. The second circuit board is located above the first sealant. The second chip is located on the upper surface of the second circuit board and electrically connected to the second circuit board. The second sealant is located on the upper surface of the second circuit board and encapsulates the second wafer.

The electronic function module comprises: a third circuit board and at least a third chip. The third circuit board is located above the first sealant. The third wafer is located on the upper surface of the third circuit board and electrically connected to the third circuit board.

The second connecting conductor is located between the first circuit board and the second circuit board or between the first circuit board and the third circuit board. The second connecting conductors include: at least one ground conductor and at least one signal conductor.

The grounding conductor is electrically coupled to the corresponding first connecting conductor, and the signal conductor is electrically coupled to the corresponding first connecting conductor. The second chip and each of the third chips are electrically connected to at least one signal conductor.

The patterned layer of thermally conductive material is between the first encapsulant and the second circuit board and between the first encapsulant and the third circuit board, and the thermal conduction is connected to at least one ground conductor. Wherein, the size of the patterned thermally conductive material layer corresponds to the outer shape of the first wafer.

In summary, the stacked semiconductor package structure according to the present invention directly sets a heat conductive material (patterned heat conductive material layer) in the interlayer corresponding to the heat source (wafer) to homogenize the heat generated by the heat source and transmit heat through the pattern. The material layer is thermally conducted to ground to remove heat from the heat source.

The terms "first", "second" and "third" are used to distinguish the elements referred to, and are not intended to rank or limit the differences of the elements referred to, and are not intended to limit The scope of the invention. In the following the term "circuit board", it includes at least one of a single layer or a plurality of layers and at least one electrically conductive line. The conductive traces are formed on the outer surface of the substrate, on the surface of the interlayer of the substrate, or through one or more layers of the substrate to provide electrical connection between different surfaces of the substrate.

1 is a schematic cross-sectional view showing a stacked semiconductor package structure according to a first embodiment of the present invention. 2 is an exploded view of the stacked semiconductor package structure of FIG. 1.

Referring to FIGS. 1 and 2 simultaneously, the stacked semiconductor package structure includes a first package body 110, a plurality of first connection conductors 120, a second package body 130, a plurality of second connection conductors 140, and a patterned heat conductive material. Layer 150.

The first package body 110 includes a first circuit board 112, at least a first wafer 114, and a first sealant 116.

The first wafer 114 is located on the upper surface 112a of the first circuit board 112 and electrically connected to the first circuit board 112.

The first adhesive 116 is located on the upper surface 112a of the first circuit board 112. The first glue 116 encloses the first wafer 114 to secure the first wafer 114 to the first circuit board 112. That is, the first sealant 116 may cover the first wafer 114 and the first circuit board 112 to wrap the first wafer 114 on the first circuit board 112.

The first connecting conductor 120 is then disposed on the lower surface 112b of the first circuit board 112 and electrically connected to the first circuit board 112. Moreover, the first wafer 114 is electrically connected to the at least one first connecting conductor 120 via the first circuit board 112.

Therefore, the electronic components in the first package 116 (eg, the first wafer 114, resistors, capacitors, inductors, other active or passive components, combinations thereof, etc.) can be electrically conducted to the first via the first circuit board 112. The conductor 120 is connected.

Here, the first connecting conductor 120 provides external signal communication of the stacked semiconductor package structure. In other words, the stacked semiconductor package structure is electrically coupled to the external line by the first connection conductor 120.

The second package body 130 includes a second circuit board 132, at least one second wafer 134, and a second sealant 136.

The second wafer 134 is located on the upper surface 132a of the second circuit board 132 and electrically connected to the second circuit board 132.

The second sealant 136 is located on the upper surface 132a of the second circuit board 132. The second sealant 136 encapsulates the second wafer 134 to secure the second wafer 134 to the second circuit board 132. That is, the second sealant 136 may cover the second wafer 134 and the second circuit board 132 to wrap the second wafer 134 on the second circuit board 132.

The second connecting conductor 140 is located between the first circuit board 112 and the second circuit board 132 and is electrically connected to the first connecting conductor 120.

The second connecting conductor 140 includes at least one ground conductor 142 and at least one signal conductor 144.

The ground conductor 142 and the signal conductor 144 are disposed on the lower surface 132b of the second circuit board 132 and electrically connected to the first circuit board 112. The grounding conductor 142 and the signal conductor 144 can be electrically connected to the corresponding first connecting conductor 120 via the first circuit board 112, respectively.

The second chip 134 is electrically connected to the at least one signal conductor 144 via the second circuit board 132. In other words, the second wafer 134 can be electrically connected to the first connecting conductor 120 via the second circuit board 132 , the signal conductor 144 , and the first circuit board 112 .

The electronic components in the second package 130 (eg, the second wafer 134, resistors, capacitors, inductors, other active or passive components, combinations thereof, etc.) may be passed through the second circuit board 132, the signal conductors 144, and the first The circuit board 112 is electrically connected to the corresponding first connecting conductor 120.

Figure 3 is a bottom plan view of one embodiment of the tangent I-I' in Figure 2;

Referring to FIG. 3, the patterned thermal conductive material layer 150 is disposed between the first package body 110 and the second package body 130 corresponding to the first wafer 114, that is, between the first sealant 116 and the second circuit board 132. between. Moreover, the patterned thermally conductive material layer 150 is thermally coupled to the at least one ground conductor 142.

The size of the patterned thermally conductive material layer 150 corresponds to the outer shape of the first wafer 114. In some embodiments, the patterned thermally conductive material layer 150 is sized to be equal to the projected shape of the first wafer 114. In other words, the patterned thermally conductive material layer 150 is a projected shape in which a thermally conductive material is disposed in the first wafer 114.

Here, the patterned heat conductive material layer 150 can be used to homogenize the heat generated by the corresponding heat source (ie, the first wafer 114), and then directly coupled to the ground conductor 142 via the heat conductive connection 152 to conduct the heat energy outward. To ground, to achieve the effect of heat dissipation. Wherein, the thermally conductive connector 152 can be formed between the patterned thermally conductive material layer 150 and the ground conductor 142 using a thermally conductive material. The first package body 110 and the second package body 130 can have respective electronic functions, so that the first package body 110 and the second package body 130 are functionally an electronic function module.

Furthermore, a plurality of electronic function modules may be disposed above the first package body 110, and the patterned heat conductive material layer 150 may be disposed and arranged in a specific shape corresponding to the heat generating chips of the electronic function modules.

4 is a schematic cross-sectional view showing a stacked semiconductor package structure according to a second embodiment of the present invention. Figure 5 is an exploded view of the stacked semiconductor package structure of Figure 4.

In some embodiments, referring to FIGS. 4 and 5, the stacked semiconductor package structure may include an electronic function module 170.

The electronic function module 170 includes a third circuit board 172 and at least a third wafer 174. The third wafer 174 is located on the upper surface 172a of the third circuit board 172 and electrically connected to the third circuit board 172.

Fig. 6 is a bottom view of the embodiment taken along line II-II' in Fig. 5.

Here, please refer to FIG. 6 in combination, and the second connecting conductor 140 is located between the first circuit board 112 and the third circuit board 172. In other words, a portion of the second connecting conductor 140 is located between the first circuit board 112 and the second circuit board 132, and another portion of the second connecting conductor 140 is located between the first circuit board 112 and the third circuit board 172. between.

The second connection conductor 140 located between the first circuit board 112 and the second circuit board 132 can be arranged in the same manner as the foregoing embodiment.

The second connecting conductor 140 between the first circuit board 112 and the third circuit board 172 may also include at least one grounding conductor 143 and at least one signal conductor 145.

The ground conductor 143 and the signal conductor 145 are disposed on the lower surface 172b of the third circuit board 172 and electrically connected to the first circuit board 112. The grounding conductor 142 and the signal conductor 144 can be electrically connected to the corresponding first connecting conductor 120 via the first circuit board 112, respectively.

The third chip 174 is electrically connected to the at least one signal conductor 145 via the third circuit board 172. In other words, the third chip 174 can be electrically connected to the corresponding first connecting conductor 120 via the third circuit board 172 , the signal conductor 145 , and the first circuit board 112 .

The electronic components in the third package 170 (eg, the third wafer 174, resistors, capacitors, inductors, other active or passive components, combinations thereof, etc.) may be passed through the third circuit board 172, the signal conductors 145, and the first The circuit board 112 is electrically connected to the corresponding first connecting conductor 120.

In some embodiments, the electronic function module 170 can be a wireless module, and the electronic function module 170 can be provided with an electromagnetic shielding cover 178. The electromagnetic shielding cover 178 is disposed outside the third chip 174 to prevent the radio frequency signal from interfering with the electronic function of other packages, that is, to avoid interference with the operation of other electronic functional modules.

Figure 7 is an exploded view of a stacked semiconductor package structure in accordance with a third embodiment of the present invention.

Referring to FIG. 7 , in some embodiments, the electronic function module 170 can also be a third package, and the third package can further include a third sealant 176 .

The third sealant 176 is located on the upper surface 172a of the third circuit board 172. The third sealant 176 encloses the third wafer 174 to secure the third wafer 174 to the third circuit board 172. That is, the third sealant 176 can be overlaid on the third wafer 174 and the third circuit board 172 to wrap the third wafer 174 on the third circuit board 172.

The electromagnetic shielding cover 178 can be disposed outside the third sealing material 156 to prevent the RF signal from interfering with the electronic function in other packages.

In other words, the aforementioned electronic function module operates through the electronic components in such a manner that the electronic function modules perform a specific electronic function.

In some embodiments, the second package 130 and the electronic function module 170 have different electronic functions. Wherein, the first wafer 114 can be a main wafer. The main chip is, for example, a central processing unit (CPU). The second wafer 134 can be a memory wafer. Memory chips such as NAND flash, double data rate synchronous dynamic random access memory (DDR SDRAM), second generation double data rate synchronous dynamic random access memory (DDR2 SDRAM) and The third generation double data rate synchronous dynamic random access memory (DDR3 SDRAM). The third wafer 174 can be a wireless communication chip. Wireless communication chips such as Bluetooth chips, wireless area network (WiFi) chips, or combinations thereof.

In some embodiments, the above-described wafers may be electrically connected to corresponding circuit boards by wire-bonding or flip-chip.

In some embodiments, the surface of the circuit board described above has a plurality of interconnects to provide electrical connections to other components (eg, wafers or tie conductors, etc.). Wherein, the interconnects can be electrical contacts or pads.

In some embodiments, when the electronic function module has a plurality of wafers, the wafers may be disposed on the surface of the corresponding circuit board in a side-by-side manner or in a stacked manner. In addition, the wafers may also be partially disposed on the circuit board in a side-by-side manner, and the other portions may be disposed on the circuit board in a stacked manner.

In some embodiments, the patterned thermally conductive material layer 150 can be a particular pattern of thermally conductive paste, metal sheet, or graphite material.

In some embodiments, when the heat source is the second wafer 134, the patterned thermally conductive material layer 150 can be disposed corresponding to the shape and position of the second wafer 134. When the heat source is the third wafer 174, the patterned heat conductive material layer 150 can be disposed corresponding to the shape and position of the second wafer 134.

Figure 8 is an exploded view of a stacked semiconductor package structure in accordance with a fourth embodiment of the present invention. Figure 9 is an exploded view of a stacked semiconductor package structure in accordance with a fifth embodiment of the present invention. Figure 10 is an exploded view of a stacked semiconductor package structure in accordance with a sixth embodiment of the present invention.

Referring to FIG. 8, the stacked semiconductor package structure may further include: a fourth circuit board 190.

The second package body 130, the fourth circuit board 190, and the first package body 110 are sequentially stacked, and the electronic function module 170, the fourth circuit board 190, and the first package body 110 are also sequentially stacked. The patterned heat conductive material layer 150 is a patterned circuit layer 192 of the fourth circuit board 190.

In some embodiments, referring to FIGS. 8-10, the aforementioned patterned thermally conductive material layer 150 is implemented with a plurality of patterned circuit layers 192, 194 of a fourth circuit board 190. At this time, the patterned circuit layers 192, 194 may be the upper surface and the lower surface of the fourth circuit board 190, respectively.

In some embodiments, referring to FIGS. 8 and 9, the fourth circuit board 190 is substantially equal in size to the first package body 110. At this time, the second connecting conductor 140 can penetrate the fourth circuit board 190 to directly electrically couple the first circuit board 112 and the second circuit board 132 or directly electrically couple the first circuit board 112 and the third circuit board 172. . However, the second connecting conductor 140 can also be electrically coupled to the fourth circuit board 190, such that the first circuit board 112 and the second circuit board 132 are electrically connected to each other or the first circuit board 112 and the third circuit board 172 are mutually connected. Electrical connection.

In some embodiments, referring to FIG. 10, the fourth circuit board 190 is smaller in size than the first package body 110, and the second connection conductor 140 is circumferentially disposed around the fourth circuit board 190.

In summary, the stacked semiconductor package structure according to the present invention directly sets a heat conductive material (patterned heat conductive material layer) in the interlayer corresponding to the heat source (wafer) to homogenize the heat generated by the heat source and transmit heat through the pattern. The material layer is thermally conducted to ground to remove heat from the heat source. In some embodiments, a layer of patterned thermally conductive material using a metallic material can also serve as a signal shielding layer.

110. . . First package

112. . . First board

112a. . . Upper surface

112b. . . lower surface

114. . . First wafer

116. . . First glue

120. . . First connecting conductor

130. . . Second package

132. . . Second circuit board

132a. . . Upper surface

132b. . . lower surface

134. . . Second chip

136. . . Second sealant

140. . . Second connecting conductor

142. . . Grounding conductor

143. . . Grounding conductor

144. . . Signal conductor

145. . . Signal conductor

150. . . Patterned thermal material layer

152. . . Thermal connection

170. . . Electronic function module

172. . . Third circuit board

172a. . . Upper surface

172b. . . lower surface

174. . . Third chip

176. . . Third sealant

178. . . Electromagnetic shield

190. . . Fourth circuit board

192. . . Patterned circuit layer

194. . . Patterned circuit layer

I-I’. . . Tangent

II-II’. . . Tangent

1 is a schematic cross-sectional view showing a stacked semiconductor package structure according to a first embodiment of the present invention.

2 is an exploded view of the stacked semiconductor package structure of FIG. 1.

Figure 3 is a bottom plan view of one embodiment of the tangent I-I' in Figure 2;

4 is a schematic cross-sectional view showing a stacked semiconductor package structure according to a second embodiment of the present invention.

Figure 5 is an exploded view of the stacked semiconductor package structure of Figure 4.

Fig. 6 is a bottom view of the embodiment taken along line II-II' in Fig. 5.

Figure 7 is an exploded view of a stacked semiconductor package structure in accordance with a third embodiment of the present invention.

Figure 8 is an exploded view of a stacked semiconductor package structure in accordance with a fourth embodiment of the present invention.

Figure 9 is an exploded view of a stacked semiconductor package structure in accordance with a fifth embodiment of the present invention.

Figure 10 is an exploded view of a stacked semiconductor package structure in accordance with a sixth embodiment of the present invention.

110. . . First package

112. . . First board

112a. . . Upper surface

112b. . . lower surface

114. . . First wafer

116. . . First glue

120. . . First connecting conductor

130. . . Second package

132. . . Second circuit board

132a. . . Upper surface

132b. . . lower surface

134. . . Second chip

136. . . Second sealant

140. . . Second connecting conductor

170. . . Electronic function module

172. . . Third circuit board

172a. . . Upper surface

172b. . . lower surface

174. . . Third chip

178. . . Electromagnetic shield

190. . . Fourth circuit board

192. . . Patterned circuit layer

194. . . Patterned circuit layer

Claims (10)

A stacked semiconductor package structure includes: a first package, comprising: a first circuit board; at least one first chip, located on an upper surface of the first circuit board, electrically connected to the first circuit board, wherein Each of the first wafers is a processor wafer; and a first sealant is disposed on the upper surface of the first circuit board to encapsulate the at least one first wafer; a plurality of first connecting conductors are located at the first a second circuit board electrically connected to the first circuit board; a second package body comprising: a second circuit board on the first sealant; at least one second chip located in the second circuit The second circuit board is electrically connected to the second circuit board, wherein each of the second chips is a memory chip; and a second sealant is located on the upper surface of the second circuit board to encapsulate the at least a second chip; an electronic functional module, comprising: a third circuit board located above the first sealant; and at least a third chip on the upper surface of the third circuit board, electrically connected to the first a three-circuit board, wherein each of the third wafers is a wireless communication chip; a plurality of second connecting conductors between the first circuit board and the second circuit board or between the first circuit board and the third circuit board, the second connecting conductors including: at least a grounding conductor electrically coupled to the at least one first connecting conductor; and at least one signal conductor electrically coupled to the at least one first connecting conductor, wherein each of the second wafer and each of the third wafers are electrically connected to each other One news And a patterned layer of thermally conductive material between the first encapsulant and the second circuit board and between the first encapsulant and the third circuit board, the thermal conduction connecting at least one of the ground conductors, wherein The patterned heat conductive material layer has a size corresponding to at least one first wafer shape, and the second connecting conductors are disposed around the patterned heat conductive material layer. The stacked semiconductor package structure of claim 1 further comprising: a thermally conductive connector coupled to the patterned thermally conductive material layer and the at least one ground conductor. The stacked semiconductor package structure of claim 1, wherein the patterned heat conductive material layer has a size equal to an outer shape of the at least one first wafer. The stacked semiconductor package structure of claim 1, wherein the patterned heat conductive material layer has a size equal to a projected shape of the at least one first wafer. The stacked semiconductor package structure of claim 1, further comprising: a fourth circuit board, the electronic functional module, the fourth circuit board and the first packaging system are sequentially stacked, wherein the patterned thermal conductive material The layer is at least one patterned circuit layer of the fourth circuit board. The stacked semiconductor package structure of claim 1, wherein the electronic functional module is a third package, the third package further comprising a third seal on the upper surface of the third circuit board Upper to encapsulate the at least one third wafer. The stacked semiconductor package structure of claim 1 or 6, further comprising: an electromagnetic shielding cover disposed outside the at least one third wafer. The stacked semiconductor package structure of claim 1, wherein the second package has a different electronic function from the electronic functional mold. The stacked semiconductor package structure of claim 1, wherein the second package and the electronic functional module are disposed on the first package at a distance from each other. The stacked semiconductor package structure of claim 1, wherein the patterned thermally conductive material layer is a specific pattern of thermal conductive paste, metal sheet or graphite material.