KR101048966B1 - Array substrate for liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

An array substrate for a liquid crystal display device and a method of manufacturing the same of the present invention form a local n-layer in an active layer to reduce the resistance between the channel layer and the ohmic contact layer of the active layer. Thereby improving on current and charge mobility, comprising: forming a gate electrode and a gate line on the substrate; Forming a gate insulating film on the substrate on which the gate electrode and the gate line are formed; Sequentially forming a first active layer, an n-layer, a second active layer, and an ohmic contact layer formed of a first amorphous silicon, an n− amorphous silicon thin film, a second amorphous silicon thin film, and an n + amorphous silicon thin film on the gate insulating layer. step; Forming a source electrode and a drain electrode on the ohmic contact layer, and forming a data line crossing the gate line to define a pixel region; Forming a passivation layer on the substrate on which the source electrode, the drain electrode, and the data line are formed; Selectively removing the passivation layer to form a contact hole exposing the drain electrode; And forming a pixel electrode electrically connected to the drain electrode through the contact hole, wherein the n-layer is formed between the first active layer and the second active layer to form a channel of the first active layer. Reducing the resistance between the layer and the ohmic contact layer.

In addition, the above-described array substrate for a liquid crystal display device and a method of manufacturing the same may form a local n-layer in the active layer to increase the electron density in the channel layer, thereby controlling the threshold voltage. .

Active layer, n-layer, channel layer, ohmic-contact layer, charge mobility, threshold voltage

Description

ARRAY SUBSTRATE OF LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME

The present invention relates to an array substrate for a liquid crystal display device and a method of manufacturing the same, and more particularly, to an array substrate for a liquid crystal display device and a method for manufacturing the same for improving electrical characteristics of a thin film transistor by improving on current and charge mobility. will be.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 defining a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by a sealant (not shown) formed outside the image display area to form a liquid crystal display panel. The bonding of the 5 and the array substrate 10 is made through a bonding key (not shown) formed on the color filter substrate 5 or the array substrate 10.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required. ought.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG. 1.

As shown in FIG. 2A, a gate electrode 21 made of a conductive metal material is formed on the array substrate 10 using a photolithography process (first mask process).

Next, as illustrated in FIG. 2B, the gate insulating film 15a, the amorphous silicon thin film, and the n + amorphous silicon thin film are sequentially deposited on the entire surface of the array substrate 10 on which the gate electrode 21 is formed. An active layer 24 made of the amorphous silicon thin film is formed on the gate electrode 21 by selectively patterning the amorphous silicon thin film and the n + amorphous silicon thin film by using a photolithography process (second mask process).

In this case, the n + amorphous silicon thin film pattern 25 patterned in the same manner as the active layer 24 is formed on the active layer 24.

Thereafter, as illustrated in FIG. 2C, a conductive metal material is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (third mask process) to form a source on the active layer 24. The electrode 22 and the drain electrode 23 are formed. In this case, the n + amorphous silicon thin film pattern formed on the active layer 24 has a predetermined region removed through the third mask process, thereby forming an ohmic − between the active layer 24 and the source / drain electrodes 22 and 23. An ohmic contact layer 25n is formed.

Next, as shown in FIG. 2D, after forming the protective film 15b on the entire surface of the array substrate 10 on which the source electrode 22 and the drain electrode 23 are formed, a photolithography process (fourth mask process) The contact hole 40 exposing a part of the drain electrode 23 is formed by removing a part of the passivation layer 15b.

Finally, as shown in FIG. 2E, a transparent conductive metal material is deposited on the entire surface of the array substrate 10 and then selectively patterned by using a photolithography process (a fifth mask process) through the contact hole 40. The pixel electrode 18 electrically connected to the drain electrode 23 is formed.

As described above, fabrication of an array substrate including a thin film transistor requires a total of five photolithography processes to pattern a gate electrode, an active layer, a source / drain electrode, a contact hole, a pixel electrode, and the like.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development processes. It has the disadvantage of dropping.

In addition, referring to FIG. 3, a structure of a general thin film transistor is formed, and a channel portion is formed through a back channel etch process after the active layer 24 is deposited. At this time, the current flows through the channel layer of the ohmic contact layer 25n and the active layer 24 through the metal electrode of the source electrode 22 and again of the ohmic contact layer 25n and the drain electrode 23. It flows to a metal electrode (A → B → C → D). At this time, an electrical barrier exists between the channel layer of the active layer 24 and the ohmic contact layer 25n (A to B and C to D) to prevent the flow of electrons and increase the resistance. do.

For reference, reference numeral d denotes the depth of the back channel etch, and Vs, Vd, and Vg denote source voltage, drain voltage, and gate voltage, respectively.

This vertical series resistance in the linear region causes a problem of decreasing the linear charge mobility of the thin film transistor.

In addition, since the active layer has an intrinsic characteristic, the active layer has a Vth value, which is a threshold voltage in the range of 1V to 2V, and there is a limit that a gate voltage must be applied according to the Vth when driving the panel. To date, there is no technique for shifting the Vth value.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. An array substrate for a liquid crystal display device and a method of manufacturing the same, which reduce the resistance between the channel layer and the ohmic contact layer of the active layer to improve the on-current and charge mobility of the thin film transistor. The purpose is to provide.

Another object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same, which realizes high frequency driving by improving charge mobility affecting charging characteristics.

Another object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same, which can control the threshold voltage of a thin film transistor.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above object, the liquid crystal display array substrate of the present invention comprises a gate electrode and a gate line formed on the substrate; A gate insulating film formed on the substrate on which the gate electrode and the gate line are formed; A first active layer, an n-layer, and a second active layer formed in order on the gate insulating film, each of which comprises a first amorphous silicon thin film, an n- amorphous silicon thin film, and a second amorphous silicon thin film; An ohmic contact layer formed of an n + amorphous silicon thin film on the second active layer; A data line defining a pixel region crossing the source electrode, the drain electrode, and the gate line formed on the ohmic contact layer; A passivation layer formed on the substrate on which the source electrode, the drain electrode and the data line are formed, and a contact hole exposing the drain electrode; And a pixel electrode electrically connected to the drain electrode through the contact hole.

A method of manufacturing an array substrate for a liquid crystal display device according to the present invention includes forming a gate electrode and a gate line on the substrate; Forming a gate insulating film on the substrate on which the gate electrode and the gate line are formed; Sequentially forming a first active layer, an n-layer, a second active layer, and an ohmic contact layer formed of a first amorphous silicon, an n− amorphous silicon thin film, a second amorphous silicon thin film, and an n + amorphous silicon thin film on the gate insulating layer. step; Forming a source electrode and a drain electrode on the ohmic contact layer, and forming a data line crossing the gate line to define a pixel region; Forming a passivation layer on the substrate on which the source electrode, the drain electrode, and the data line are formed; Selectively removing the passivation layer to form a contact hole exposing the drain electrode; And forming a pixel electrode electrically connected to the drain electrode through the contact hole, wherein the n-layer is formed between the first active layer and the second active layer to form a channel of the first active layer. Reducing the resistance between the layer and the ohmic contact layer.

As described above, the array substrate for the liquid crystal display device and the method of manufacturing the same according to the present invention provide an effect of reducing the number of masks used for manufacturing the thin film transistor and reducing the manufacturing process and cost.

In addition, the array substrate for a liquid crystal display device and the method of manufacturing the same according to the present invention provide an effect of improving the performance of the thin film transistor as the on current and charge mobility in the linear region are improved.

In addition, the array substrate for a liquid crystal display device and the method of manufacturing the same according to the present invention have an effect that no tack time loss occurs when the amorphous silicon thin film and the n- amorphous silicon thin film are formed by successive deposition.

In addition, when the thin film transistor manufactured according to the present invention is used as a driving thin film transistor, it has an effect of improving the lifespan, and has an advantage of being suitable as a driving device having a high duty ratio.

Hereinafter, exemplary embodiments of an array substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a cross-sectional view schematically illustrating the structure of a thin film transistor according to a first embodiment of the present invention, and illustrates an example in which an n-layer is locally formed in an intermediate region of an active layer.

As shown in the figure, the thin film transistor according to the first embodiment of the present invention includes a first active layer 124a and n formed of a first amorphous silicon thin film with a gate insulating film 115a interposed therebetween on the gate electrode 121. An n-layer 135 made of an amorphous silicon thin film, a second active layer 124b made of a second amorphous silicon thin film, and an ohmic contact layer 125n made of an n + amorphous silicon thin film are formed. A source electrode 122 and a drain electrode 123 are formed on the ohmic contact layer 125n to form an ohmic contact with the second active layer 124b through the ohmic contact layer 125n. have.

At this time, the active layer according to the first embodiment of the present invention is composed of the first active layer 124a and the second active layer 124b with the n-layer 135 interposed therebetween to form a channel layer. When the back channel is etched, a part of the thickness of the first active layer 124a is etched.

As such, by forming the local n-layer 135 in the active layer, the series resistance between the source / drain electrodes 122 and 123 and the channel layer is reduced, thereby increasing conductivity. As a result, the electrical characteristics of the thin film transistor, such as the improvement of the on-current and charge mobility, are improved.

In this case, the n− amorphous silicon thin film according to the first embodiment of the present invention is formed by injecting PH ₃ gas into a region about 100 μs to 300 μs apart from the n + amorphous silicon thin film, wherein the first amorphous silicon thin film and the second amorphous The silicon thin film may be formed by continuous deposition or the first amorphous silicon thin film may be formed by additional PH ₃ plasma treatment. At this time, in the case of forming an n-amorphous silicon thin film by continuously depositing PH ₃ there is an advantage that there is no loss of tack time.

The liquid crystal display according to the first exemplary embodiment of the present invention uses a half-tone mask or a diffraction mask (hereinafter referred to as a half-tone mask to include a diffraction mask) in one mask process. By forming the active layer, the source electrode and the drain electrode, an array substrate can be manufactured by a total of four mask processes, which will be described in detail through the following manufacturing method.

5A through 5D are cross-sectional views sequentially illustrating a manufacturing process of an array substrate for a liquid crystal display device, wherein an n-amorphous silicon thin film is formed together with a first amorphous silicon thin film and a second amorphous silicon thin film by continuous deposition. The manufacturing process of a board | substrate is shown, for example.

As shown in FIG. 5A, a gate electrode 121 and a gate line (not shown) are formed in the pixel portion of the array substrate 110 made of a transparent insulating material such as glass.

In this case, the gate electrode 121 and the gate line are formed by depositing a first conductive layer on the entire surface of the array substrate 110 and then selectively patterning the same through a photolithography process (first mask process).

The first conductive layer may include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), or the like. The same low resistance opaque conductive material can be used. In addition, the first conductive film may be formed in a multilayer structure in which two or more low-resistance conductive materials are stacked.

Next, as shown in FIG. 5B, the gate insulating layer 115a, the first amorphous silicon thin film, the n-amorphous silicon thin film, and the second amorphous silicon are disposed on the entire surface of the array substrate 110 on which the gate electrode 121 and the gate line are formed. After the silicon thin film, the n + amorphous silicon thin film and the second conductive film are formed, they are selectively removed through a photolithography process (second mask process) to form a first amorphous silicon thin film made of the first amorphous silicon thin film in the pixel portion of the array substrate 110. 1 active layer 124a, n-layer 135 made of the n- amorphous silicon thin film, second active layer 124b made of the second amorphous silicon thin film, and ohmic-contact layer made of the n + amorphous silicon thin film ( 125n) and a source electrode 122 and a drain electrode 123 formed of the second conductive layer and electrically connected to a part of the second active layer 124b. In this case, the first amorphous silicon thin film and the second amorphous silicon thin film may be formed of substantially the same amorphous silicon, or may be formed of amorphous silicon under different conditions.

In addition, a data line (not shown) formed of the second conductive layer through the second mask process and defining a pixel area is formed to cross the gate line.

As described above, in the case of the first embodiment of the present invention, the source / drain electrodes 122 and 123 are formed of the n- amorphous silicon thin film, the amorphous silicon thin film, and the n + amorphous silicon thin film in order on the first active layer 124a. The n-layer 135, the second active layer 124b, and the ohmic contact layer 125n that are patterned in the same manner as in FIG.

In this case, in the case of the first embodiment of the present invention, during the process of forming the first amorphous silicon thin film on the gate insulating film 115a, an additional PH ₃ gas is injected to continuously form the n-amorphous silicon thin film. As described above, in the case of forming the n-layer 135 by continuously depositing an n-amorphous silicon thin film, there is an advantage in that there is no loss of tack time.

Here, the first active layer 124a, the n-layer 135, the second active layer 124b, the ohmic contact layer 124b, the source / drain electrode 122 according to the first embodiment of the present invention. 123) and the data line are simultaneously formed in one mask process (second mask process) using a half-tone mask. Hereinafter, the second mask process will be described in detail with reference to the accompanying drawings.

6A to 6H are cross-sectional views specifically illustrating the second mask process illustrated in FIG. 5B.

As shown in FIG. 6A, a gate insulating layer 115a made of an insulating material such as a silicon nitride layer is formed on the entire surface of the array substrate 110 on which the gate electrode 121 and the gate line are formed.

Thereafter, as shown in FIG. 6B, the first amorphous silicon thin film 120a is formed to have a thickness of 600 μm to 1600 μm by depositing first amorphous silicon on the entire surface of the array substrate 110 on which the gate insulating layer 115a is formed. In addition, an n− amorphous silicon thin film 130 made of n− amorphous silicon is formed on the first amorphous silicon thin film 120a to a predetermined thickness (˜100 μs). At this time, the n- amorphous silicon thin film 130 is first formed by injection there is additionally a PH ₃ gas with a low concentration in the process of forming the amorphous silicon thin film (120a), thus the process other than the injection of the PH ₃ gas The conditions are substantially the same to continuously form the n− amorphous silicon thin film 130 together with the first amorphous silicon thin film 120a.

Subsequently, the second amorphous silicon thin film 120b is formed on the n− amorphous silicon thin film 130 to have a thickness of 100 μs to 300 μs by continuously depositing the second amorphous silicon while blocking the injection of the PH ₃ gas. In the same manner, an n + amorphous silicon thin film 125 made of n + amorphous silicon is formed on the second amorphous silicon thin film 120b to have a predetermined thickness (˜300 μs). At this time, the n + amorphous silicon thin film 125 and the second there is formed by injection by adding a high concentration of PH ₃ gas in the process of forming the amorphous silicon thin film (120b), thus process conditions other than the injection of the PH ₃ gas Is substantially the same, thereby forming a tack time by continuously forming the n + amorphous silicon thin film 125 together with the first amorphous silicon thin film 120a, the n- amorphous silicon thin film 130, and the second amorphous silicon thin film 120b. The loss of does not occur.

Next, as illustrated in FIG. 6C, an array substrate on which the first amorphous silicon thin film 120a, the n− amorphous silicon thin film 130, the second amorphous silicon thin film 120b, and the n + amorphous silicon thin film 125 is formed The second conductive layer 150 is formed on the entire surface of the layer 110.

In this case, the second conductive layer 150 may be made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, etc. to form a source electrode, a drain electrode, and a data line.

6D, after the photoresist film 170 made of photosensitive material such as photoresist is formed on the entire surface of the array substrate 110, the photoresist film 170 is formed through the half-tone mask 180. Selectively irradiates light.

In this case, the half-tone mask 180 includes a first transmission region I transmitting all of the irradiated light, a second transmission region II transmitting only a part of the light, and blocking a portion of the light, and blocking all the irradiated light. The region III is provided, and only the light transmitted through the half-tone mask 180 is irradiated to the photosensitive film 170.

Subsequently, after the photoresist film 170 exposed through the half-tone mask 180 is developed, as shown in FIG. 6E, all the light passes through the blocking region III and the second transmission region II. The first photoresist pattern 170a to the third photoresist pattern 170c having a predetermined thickness remain in the blocked or partially blocked region, and the photoresist is completely removed in the first transmission region I through which all light is transmitted. The surface of the second conductive film 150 is exposed.

In this case, the first photoresist pattern 170a to the second photoresist pattern 170b formed in the blocking region III is formed thicker than the third photoresist pattern 170c formed through the second transmission region II. In addition, the photosensitive film is completely removed in a region where all the light is transmitted through the first transmission region I. This is because the photoresist of the positive type is used, and the present invention is not limited thereto. May be used.

Next, as shown in FIG. 6F, the first amorphous silicon thin film and the n− amorphous silicon thin film formed below the first photosensitive film pattern 170a to the third photosensitive film pattern 170c formed as a mask are used as a mask. When the second amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film are selectively removed, the first amorphous silicon thin film, the n− amorphous silicon thin film, and the second amorphous silicon thin film are formed in the pixel portion of the array substrate 110. , the first amorphous silicon thin film pattern 120a 'including the n + amorphous silicon thin film and the second conductive layer, the n- amorphous silicon thin film pattern 130', the second amorphous silicon thin film pattern 120b ', and the n + amorphous silicon thin film pattern 125 'and the second conductive film pattern 150' are formed. In this case, a data line (not shown) formed of the second conductive layer and substantially crossing the gate line is defined in the data line part of the array substrate 110.

Subsequently, when an ashing process of removing a portion of the first photoresist pattern 170a to the third photoresist pattern 170c is performed, as illustrated in FIG. 6G, the second transmission region II may be formed. The third photoresist pattern is completely removed.

In this case, the first photoresist pattern and the second photoresist pattern correspond to the blocking region III by the fourth photoresist pattern 170a 'and the fifth photoresist pattern 170b', which have the thickness of the third photoresist pattern removed. Only the source electrode region and the drain electrode region remain.

6H, the first amorphous silicon thin film pattern, the n− amorphous silicon thin film pattern, and the first photosensitive film pattern 170a 'and the fifth photosensitive film pattern 170b' are used as masks. The first amorphous silicon thin film, the n− amorphous silicon thin film, and the second amorphous silicon thin film pattern, the n + amorphous silicon thin film pattern, and the second conductive film pattern may be selectively removed, respectively, in the pixel portion of the array substrate 110. A first active layer 124a, an n-layer 135, a second active layer 124b, and an ohmic contact layer 125n formed of an amorphous silicon thin film and an n + amorphous silicon thin film are formed. In addition, a source electrode 122 and a drain electrode 123 formed of the second conductive layer and electrically connected to a portion of the second active layer 124b are formed.

As described above, according to the first embodiment of the present invention, the first active layer 124a, the n-layer 135, the second active layer 124b, the ohmic contact layer 125n, and the source by using a half-tone mask are provided. The / drain electrodes 122 and 123 and the data line can be formed through a single mask process.

Next, as shown in FIG. 5C, after forming the protective film 115b made of an insulating material on the entire surface of the array substrate 110, the protective film 115b may be formed using a photolithography process (third mask process). The contact hole 140 exposing a part of the drain electrode 123 is formed by selectively removing a portion of the region.

As shown in FIG. 5D, after forming a third conductive film on the entire surface of the array substrate 110, the contact hole is selectively patterned by selectively patterning the third conductive film using a photolithography process (fourth mask process). The pixel electrode 118 is electrically connected to the drain electrode 123 through the 140.

The array substrate of the present invention configured as described above is bonded to the color filter substrate by a sealant formed on the outside of the image display area, wherein the color filter substrate is exposed to the thin film transistors, the gate lines, and the data lines. The black matrix to prevent and the color filter to implement the colors of red, green and blue are formed.

At this time, the bonding of the color filter substrate and the array substrate is made through a bonding key formed on the color filter substrate or the array substrate.

FIG. 7 is a cross-sectional view schematically illustrating a structure of a thin film transistor according to a second exemplary embodiment of the present invention, and illustrates an example in which an n-layer is formed directly under an ohmic contact layer.

As shown in the figure, the thin film transistor according to the second embodiment of the present invention is an n-amorphous silicon thin film and an active layer 224 made of an amorphous silicon thin film with a gate insulating film 215a therebetween on the gate electrode 221. An ohmic contact layer 225n formed of an n-layer 235 and an n + amorphous silicon thin film is formed. A source electrode 222 and a drain electrode 223 are formed on the ohmic contact layer 225n to form an ohmic contact with the active layer 224 through the ohmic contact layer 225n.

In this case, the n-layer 235 according to the second embodiment of the present invention is located directly under the ohmic contact layer 225n, and when the back channel etch is performed to form the channel layer, It is etched up to a part of the thickness.

As such, by forming a local n-layer 235 between the active layer 224 and the ohmic contact layer 225n, the series resistance between the source / drain electrodes 222 and 223 and the channel layer is reduced to increase conductivity. Done. As a result, the electrical characteristics of the thin film transistor, such as the improvement of the on-current and charge mobility, are improved.

In this case, as described above, the n-layer 235 according to the second embodiment of the present invention is formed by injecting PH ₃ gas into a region immediately below the ohmic contact layer 225n. As in the case of the exemplary embodiment, the active layer 224 may be formed by continuous deposition or the active layer 224 may be formed by additional PH ₃ plasma treatment. In this case, when the n-layer 235 is formed by continuously depositing PH ₃ , there is an advantage in that there is no loss of tack time.

FIG. 8 is a graph showing the electrical characteristics of the thin film transistors manufactured according to the first and second embodiments of the present invention, and shows the drain current according to the gate voltage when the drain voltage is 1V.

8 illustrates the basic condition in which the n-layer is not formed and the n-layer is deposited in the active layer according to the first embodiment, and the n-layer is the ohmic contact layer according to the second embodiment. The case where it is deposited directly below is shown together.

As shown in the figure, it can be seen that the on-current is higher than the basic conditions in the case of n-deposition and n-step deposition, and among them, it can be seen that the on-current is the highest in the case of n-step deposition.

This is because the conductivity between the channel and the ohmic contact layer of the active layer is increased due to the decrease of the vertical resistance in the active layer, and also the charge mobility in the linear region is higher than the basic condition in the case of n-deposition and n-step deposition. It can be seen that the electrical properties of the thin film transistor are excellent due to the increase in measurement.

9A to 9G are cross-sectional views sequentially illustrating another manufacturing process of an array substrate for a liquid crystal display device, in which an n-amorphous silicon thin film is formed by forming a first amorphous silicon thin film and then performing an additional PH ₃ plasma treatment. The manufacturing process of a board | substrate is shown, for example.

As shown in FIG. 9A, a gate electrode 121 and a gate line (not shown) are formed in the pixel portion of the array substrate 110 made of a transparent insulating material such as glass.

In this case, the gate electrode 121 and the gate line are formed by depositing a first conductive layer on the entire surface of the array substrate 110 and then selectively patterning the same through a photolithography process (first mask process).

Next, as shown in FIG. 9B, a gate insulating film 115a is formed on the entire surface of the array substrate 110 on which the gate electrode 121 and the gate line are formed, and then the array substrate on which the gate insulating film 115a is formed ( 110, the first amorphous silicon thin film 120a is formed by depositing the first amorphous silicon on the entire surface.

As shown in FIG. 9C, an n − amorphous silicon thin film 160 having a predetermined thickness is formed by performing a PH ₃ plasma treatment on the entire surface of the array substrate 110.

As described above, after forming the n− amorphous silicon thin film 160 by performing a PH ₃ plasma treatment, second amorphous silicon and n + amorphous silicon are deposited again on the entire surface of the array substrate 110 as shown in FIG. 9D. Each of the second amorphous silicon thin film 120b and the n + amorphous silicon thin film 125 is formed to have a predetermined thickness.

Subsequently, as shown in FIG. 9E, an array substrate on which the first amorphous silicon thin film 120a, the n− amorphous silicon thin film 160, the second amorphous silicon thin film 120b, and the n + amorphous silicon thin film 125 is formed After forming the second conductive film on the entire surface of the (110), by selectively patterning through a photolithography process (second mask process), the first amorphous silicon thin film, n- amorphous silicon, respectively, in the pixel portion of the array substrate 110 A first active layer 124a, an n-layer 165, a second active layer 124b, and an ohmic contact layer 125n formed of a thin film, a second amorphous silicon thin film, and an n + amorphous silicon thin film are formed. In addition, a source electrode 122 and a drain electrode 123 formed of the second conductive layer and electrically connected to a portion of the second active layer 124b are formed.

Next, as shown in FIG. 9F, a protective film 115b made of an insulating material is formed on the entire surface of the array substrate 110, and then a photolithography process (third mask process) is used to form the protective film 115b. The contact hole 140 exposing a part of the drain electrode 123 is formed by selectively removing a portion of the region.

As shown in FIG. 9G, after forming a third conductive film on the entire surface of the array substrate 110, the contact hole is selectively patterned by selectively patterning the third conductive film using a photolithography process (fourth mask process). The pixel electrode 118 is electrically connected to the drain electrode 123 through the 140.

FIG. 10 is a graph showing electrical characteristics of the thin film transistor fabricated according to FIGS. 9A to 9G, and illustrates a transfer curve representing a drain current according to a gate voltage when the drain voltage is 15V.

In this case, the Fig. 10 shows a case in which the n- layer located between the first active layer and the second active layer subjected to basic conditions, and PH ₃ plasma treatment is not conducted with PH ₃ plasma treatment. Here, referring to FIG. 4, 600, 800, 1000, 1200, and 1400 μs represent a height at which an n-layer is positioned from a lower surface of the first active layer, that is, a thickness of the first active layer.

FIG. 11 is a graph showing charge mobility according to the thickness of the first active layer, in which part A represents charge mobility in a channel of a general thin film transistor having the basic conditions, and part B represents a semiconductor device according to the present invention. The charge mobility according to the position (600 kPa to 1600 kPa) where the n-layer is formed in the thin film transistor is shown, respectively.

10 and 11, the TFT according to aspects of the present invention is a charge transfer of 50 to 60% than that of a general charge transfer TFTs (~ 0.42cm ² / Vs) even (~ 0.68cm ² / Vs It can be seen that) is improved. In particular, when the n-layer is located in the range of 1200 Å to 1600 Å, it can be seen that the charge mobility (˜0.7 cm ² / Vs) characteristics of the thin film transistor are the best.

As described above, in the present invention, the n-layer is interposed between the first active layer and the second active layer, and thus, the high frequency driving can be realized by improving the charging time according to the improvement of the charge mobility.

12A and 12B are cross-sectional views schematically illustrating structures of the thin film transistors according to the third and fourth exemplary embodiments of the present invention, for example, in which a back channel etch is performed to a part of the thickness of the second active layer. have.

First, as shown in FIG. 12A, the thin film transistor according to the third exemplary embodiment of the present invention includes a first active layer 324a formed of a first amorphous silicon thin film with a gate insulating film 315a interposed therebetween on the gate electrode 321. ), an n-layer 335 made of an n- amorphous silicon thin film, a second active layer 324b made of a second amorphous silicon thin film, and an ohmic contact layer 325n made of an n + amorphous silicon thin film. A source electrode 322 and a drain electrode 323 are formed on the ohmic contact layer 325n to form an ohmic contact with the active layer 324 through the ohmic contact layer 325n.

In this case, the n-layer 335 according to the third exemplary embodiment of the present invention is positioned between the first active layer 324a and the second active layer 324b and performs back channel etching to form a channel layer. When the thickness of the second active layer 324b is etched.

In the third embodiment of the present invention, the first amorphous silicon is deposited by about 300 kPa to 400 kPa to form the first amorphous silicon thin film, followed by PH ₃ plasma treatment to form P atoms on the surface of the first amorphous silicon thin film. Doping. Next, the second amorphous silicon and the n + amorphous silicon are further deposited to form the second amorphous silicon thin film and the n + amorphous silicon thin film. Subsequently, the process is substantially the same as described above, and the P atoms doped onto the surface of the first amorphous silicon thin film by PH ₃ plasma treatment are surplus electrons because they are a Group 5 element having one more electron than silicon (Si). These affect the thin film transistor when it is operating. That is, the threshold voltage Vth has a negative value because the number of electron carriers is increased compared to the existing structure. In this case, when the time of the plasma treatment of PH ₃ is adjusted, the degree of movement of Vth may be controlled, which is a driving thin film transistor of an organic light emitting diode (OLED) and a thin film having a high duty ratio. When applied to the transistor can be expected to improve the life.

When the PH ₃ plasma treatment is performed once, as in the third embodiment, the result is that Vth does not move any longer but saturates even if the PH ₃ flow rate is increased while the plasma treatment time is increased. Thus, unlike the third embodiment, the degree of Vth shift can be increased by performing the PH ₃ plasma treatment several times in the middle of the deposition of the amorphous silicon thin film, which is illustrated through the fourth embodiment of FIG. 12B.

As shown in FIG. 12B, the thin film transistor according to the fourth embodiment of the present invention may include a first active layer 424a formed of a first amorphous silicon thin film with a gate insulating film 415a interposed therebetween on a gate electrode 421, A first n-layer 435a made of a first n- amorphous silicon thin film, a second active layer 424b made of a second amorphous silicon thin film, and a second n-layer 435b made of a second n- amorphous silicon thin film The third active layer 424c made of the third amorphous silicon thin film and the ohmic contact layer 425n made of the n + amorphous silicon thin film are formed. A source electrode 422 and a drain electrode 423 are formed on the ohmic contact layer 425n to form an ohmic contact with the active layer 424 through the ohmic contact layer 425n.

In this case, the n-layer according to the fourth embodiment of the present invention may include a first n-layer 435a and a second active layer (435a) disposed between the first active layer 424a and the second active layer 424b. 424b and a second n-layer 435b positioned between the third active layer 424c, and the thickness of the third active layer 324c when the back channel etch is formed to form the channel layer. Will be etched. However, the present invention is not limited thereto, and the present invention is also applicable to a case where the PH ₃ plasma treatment is performed three or more times in the middle of the deposition of the amorphous silicon thin film.

In the case of the fourth embodiment of the present invention, the number of electron carriers is increased compared to the existing structure and the third embodiment, and thus the degree of movement of Vth can be increased.

13A and 13B are graphs showing electrical characteristics of a thin film transistor according to a third exemplary embodiment of the present invention, and show changes in current and Vth when the PH ₃ gas treatment time in a plasma state is changed from 0 to 30 seconds. It is a graph.

As shown in FIGS. 13A and 13B, it can be seen that the size of Vth decreases in proportion to the plasma processing time and the number of times.

At this time, in order to maintain the size of the Vth constant within the range of 1V to 2V, the treatment time of the PH ₃ gas in the plasma state should be maintained within 20 seconds.

The present invention can be used not only in liquid crystal display devices, but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting elements are connected to driving transistors.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG.

3 is a cross-sectional view schematically showing the structure of a general thin film transistor.

4 is a cross-sectional view schematically showing the structure of a thin film transistor according to a first embodiment of the present invention.

5A through 5D are cross-sectional views sequentially illustrating a manufacturing process of an array substrate for a liquid crystal display device.

6A to 6H are cross-sectional views illustrating the second mask process shown in FIG. 5B in detail.

7 is a cross-sectional view schematically showing the structure of a thin film transistor according to a second embodiment of the present invention.

8 is a graph showing electrical characteristics of thin film transistors manufactured according to the first and second embodiments of the present invention.

9A to 9G are cross-sectional views sequentially showing another manufacturing process of an array substrate for a liquid crystal display device.

10 is a graph illustrating electrical characteristics of a thin film transistor manufactured according to FIGS. 9A to 9G.

11 is a graph showing the charge mobility according to the thickness of the first active layer.

12A and 12B are cross-sectional views schematically showing the structure of a thin film transistor according to a third embodiment and a fourth embodiment of the present invention.

13A and 13B are graphs showing electrical characteristics of a thin film transistor according to a third embodiment of the present invention.

DESCRIPTION OF REFERENCE NUMERALS

121 to 421: gate electrode 122 to 422: source electrode

123 to 423: drain electrodes 124a, 324a and 424a: first active layer

124b, 324b, 424b: second active layer 125n to 425n: ohmic contact layer

135-335,435a, 435b: n-layer 224: active layer

424c: third active layer

Claims (19)

Forming a gate electrode and a gate line on the substrate; Forming a gate insulating film on the substrate on which the gate electrode and the gate line are formed; A first active layer, an n-layer, a second active layer, and an ohmic contact layer formed of a first amorphous silicon thin film, an n− amorphous silicon thin film, a second amorphous silicon thin film, and an n + amorphous silicon thin film are sequentially formed on the gate insulating film. Doing; Forming a source electrode and a drain electrode on the ohmic contact layer, and forming a data line crossing the gate line to define a pixel region; Forming a passivation layer on the substrate on which the source electrode, the drain electrode, and the data line are formed; Selectively removing the passivation layer to form a contact hole exposing the drain electrode; And Forming a pixel electrode electrically connected to the drain electrode through the contact hole, wherein the n-layer is formed between the first active layer and the second active layer to form a channel layer of the first active layer And reducing the resistance between the ohmic contact layer and the ohmic contact layer. The method of claim 1, wherein forming a first active layer, an n-layer, a second active layer, an ohmic contact layer, and a source / drain electrode is formed on the gate insulating layer. Sequentially forming a first amorphous silicon thin film, an n− amorphous silicon thin film, a second amorphous silicon thin film, and an n + amorphous silicon thin film on the gate insulating film; Forming a conductive film on the n + amorphous silicon thin film; And Selectively patterning the first amorphous silicon thin film, the n- amorphous silicon thin film, the second amorphous silicon thin film, the n + amorphous silicon thin film, and the conductive film to respectively form the first amorphous silicon thin film, the n- amorphous silicon thin film, the second amorphous silicon thin film, and forming a first active layer, an n-layer, a second active layer, an ohmic contact layer, and a source / drain electrode formed of an n + amorphous silicon thin film and a conductive film. Manufacturing method. 3. The method of claim 2, wherein the n− amorphous silicon thin film is continuously formed together with the first amorphous silicon thin film by injecting a low concentration PH ₃ gas during the process of forming the first amorphous silicon thin film. A method of manufacturing an array substrate for a liquid crystal display device. The method of claim 2, wherein the first amorphous silicon thin film and the second amorphous silicon thin film are formed of the same amorphous silicon. The method of claim 2, wherein a back channel is etched to the inside of the first amorphous silicon thin film when the source electrode and the drain electrode are formed. 3. The method of claim 2, wherein a back channel is etched to the inside of the second amorphous silicon thin film when the source electrode and the drain electrode are formed. 3. The method of claim 2, further comprising forming a second n- amorphous silicon thin film and a third amorphous silicon thin film sequentially on the second amorphous silicon thin film. . The method of claim 7, wherein a back channel is etched up to the inside of the third amorphous silicon thin film when the source electrode and the drain electrode are formed. The method of claim 2, wherein the n− amorphous silicon thin film is formed at a position of 100 μm to 300 μm away from the n + amorphous silicon thin film. 10. The method of claim 9, wherein the n− amorphous silicon thin film is formed at a position 600 Å to 1600 로부터 away from a lower portion of the first amorphous silicon thin film. 3. The method of claim 2, wherein the n- amorphous silicon thin film is formed by forming a first amorphous silicon thin film and then performing a PH ₃ plasma treatment. A gate electrode and a gate line formed on the substrate; A gate insulating film formed on the substrate on which the gate electrode and the gate line are formed; A first active layer, an n-layer, and a second active layer formed in order on the gate insulating film, each of which comprises a first amorphous silicon thin film, an n- amorphous silicon thin film, and a second amorphous silicon thin film; An ohmic contact layer formed of an n + amorphous silicon thin film on the second active layer; A data line defining a pixel region crossing the source electrode, the drain electrode, and the gate line formed on the ohmic contact layer; A passivation layer formed on the substrate on which the source electrode, the drain electrode and the data line are formed, and a contact hole exposing the drain electrode; And And a pixel electrode electrically connected to the drain electrode through the contact hole. 13. The array substrate of claim 12, wherein the first amorphous silicon thin film and the second amorphous silicon thin film are made of the same amorphous silicon. 13. The array substrate of claim 12, wherein a back channel is etched to the inside of the first amorphous silicon thin film. 13. The array substrate of claim 12, wherein a back channel is etched into the second amorphous silicon thin film. 13. The array substrate of claim 12, further comprising a second n- amorphous silicon thin film and a third amorphous silicon thin film sequentially formed on the second amorphous silicon thin film. 18. The array substrate of claim 16, wherein the back channel is etched into the third amorphous silicon thin film. 13. The array substrate of claim 12, wherein the n− amorphous silicon thin film is located at a position of 100 ns to 300 ns away from the n + amorphous silicon thin film. 19. The array substrate of claim 18, wherein the n− amorphous silicon thin film is positioned at a position of 600 m to 1600 m from a lower portion of the first amorphous silicon thin film.

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