KR20050117846A - Method for fabricating of an array substrate for a liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display device.

The present invention is to simplify the process by reducing the dry etching step of the two steps that are successively performed in the second mask process in the process of manufacturing the array substrate for the liquid crystal display device using a four mask process and a three mask process. The purpose.

The core of the array substrate manufacturing method according to the present invention for achieving the above object is a PR (photosensitive pattern) by changing the etching gas ratio during the PR ashing process performed in the second mask process to form the source electrode and the drain electrode Dry etching the metal for forming the source and drain electrodes at the same time as the ashing.

In this way, since the dry etching step can be easily reduced, the process can be simplified as mentioned above, and thus, there is an advantage that the mass productivity is improved.

Description

Method for fabricating of an array substrate for a liquid crystal display device}

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display device manufactured by a four mask process and a three mask process.

1 is a plan view schematically illustrating a general liquid crystal display device.

As shown in the drawing, a general liquid crystal display device 9 includes a color filter 26 including a black matrix 22 and a sub-color filter 24 and a transparent electrode deposited on the color filter 26. An upper substrate 20 having electrodes 28 formed thereon, and a lower substrate 10 having an array wiring including a pixel region P and a pixel electrode 16 formed on the pixel region and a switching element T, The liquid crystal 18 is filled between the upper substrate 20 and the lower substrate 10.

The lower substrate 10 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and includes a gate wiring 12 and a data wiring 14 passing through the plurality of thin film transistors. Is formed.

The pixel area P is an area defined by the gate line 12 and the data line 14 intersecting with each other. The pixel electrode 16 formed on the pixel region P uses a transparent conductive metal having a relatively high light transmittance, such as indium-tin-oxide (ITO).

In the liquid crystal display configured as described above, the thin film transistor T and the pixel electrode 16 connected to the thin film transistor are present in a matrix to display an image.

The gate wiring 12 transfers a pulse voltage driving a gate electrode, which is a first electrode of the thin film transistor T, and the data wiring 14 receives a source electrode, which is a second electrode of the thin film transistor T. It is a means for transmitting the driving signal voltage.

The driving of the liquid crystal panel having the configuration as described above is due to the electro-optical effect of the liquid crystal.

In detail, the liquid crystal layer 18 is a dielectric anisotropic material, and when a voltage is applied, the arrangement direction of molecules changes according to an application direction of an electric field.

Therefore, the optical characteristic is changed according to this arrangement state, thereby causing electrical light modulation.

By the light modulation phenomenon of the liquid crystal, an image is realized by a method of blocking or passing light.

The liquid crystal display device exhibiting the above operation is very complicated in manufacturing process, and efforts have been made to shorten the process time and manufacturing cost by simplifying the process.

FIG. 2 is an enlarged plan view schematically illustrating a part of an array substrate for a liquid crystal display device manufactured by a conventional four mask process.

As shown in the drawing, the gate line 32 and the data line 54 are orthogonal to define the pixel area P, and at the intersection of the gate line 32 and the data line 54, a thin film transistor (S) is used as a switching element. T) is located.

The thin film transistor T is connected to the gate line 32 to receive a scan signal, a gate electrode 34, a source electrode 50 connected to the data line 54 to receive a data signal, and a predetermined value. The drain electrodes 52 are spaced apart from each other.

The gate electrode 34 includes an active layer 38 formed on the gate electrode 34 and in contact with the source electrode 50 and the drain electrode 52.

In addition, a transparent pixel electrode 64 is formed on the pixel region P in contact with the drain electrode 52.

An island-shaped metal pattern 56 is formed on the gate line 32, and the metal pattern 56 is in contact with the pixel electrode 64 formed in the pixel region P.

With the above configuration, a part of the gate wiring 32 is used as the first storage electrode, and the metal pattern 56 in contact with the pixel electrode 64 is used as the second storage electrode, and the first and the second A storage capacitor C _ST having a gate insulating film (not shown) positioned between the two storage electrodes 32 and 56 as a dielectric is formed.

In this case, although not shown, an ohmic contact layer (not shown) is formed between the active layer 38 and the source and drain electrodes 50 and 52, and a pure amorphous silicon layer forming the active layer and the ohmic contact layer. The impurity amorphous silicon layer is patterned to be positioned below the data line 54 and below the metal pattern 56.

The configuration of the array substrate as described above is manufactured by a four mask process.

Hereinafter, a method of fabricating an array substrate in a four mask process will be described with reference to FIGS. 3 to 10.

3 is a diagram illustrating a first mask process, and as illustrated, the substrate 30 is defined as a pixel region P including a switching region S and a storage region ST.

A metal material including aluminum (Al), aluminum alloy (AlNd), or the like is deposited and patterned on the substrate 30 on which the plurality of regions S, P, and ST are defined to correspond to the switching region S. The gate wiring 32 is formed on one side of the pixel electrode P including the gate electrode 34 and the storage area ST.

One or more materials selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) are deposited on the entire surface of the substrate 30 on which the gate electrode 34 and the gate wiring 32 are formed. The gate insulating film 36 is formed.

Subsequently, a pure amorphous silicon layer 38 and an amorphous silicon layer 40 including impurities are stacked on the gate insulating layer 36.

Next, molybdenum (Mo) is deposited on the impurity amorphous silicon layer 40 to form a metal layer 42.

4A to 4G are cross-sectional views illustrating a second mask process.

As shown in FIG. 4A, a photoresist is applied to the entire surface of the substrate 30 on which the metal layer 42 is formed to form a photosensitive layer 46.

The mask M including the transmissive part A1, the reflecting part A2, and the transflective part A3 is positioned on a spaced upper portion of the substrate 30 on which the photosensitive layer 46 is formed.

At this time, if it is assumed that the photosensitive layer 46 has a positive characteristic, the photosensitive layer 46 corresponding to the reflective portion A2 is not exposed because it is blocked from light, and the transmissive portion ( The portion corresponding to A1) is completely exposed by the light, and the portion corresponding to the transflective portion A3 is weakly exposed because the light intensity is weak.

At this time, the transflective portion A3 and the reflecting portion A2 are positioned at one side and the other side of the gate region 32 corresponding to the switching region S, and the gate wiring 32 corresponding to the storage region ST. The reflector A2 is positioned at a portion of the upper portion.

The process of exposing and developing the lower photosensitive layer 46 by irradiating light to the upper portion of the mask (M).

As shown in FIG. 4B, a first photosensitive pattern 48a having a different height corresponding to the switching region S and a second photosensitive pattern 48b are formed corresponding to the storage region ST.

The metal layer 42 exposed to the peripheries of the first and second photosensitive patterns 48a and 48b is removed through a wet etch process.

Next, the impurity amorphous silicon layer and the pure amorphous silicon layer exposed under the metal layer 42 are removed through a dry etch process.

In this case, as shown in FIG. 4C, the pure amorphous silicon layer 38, the impurity amorphous silicon layer 40, and the metal layer 42 patterned corresponding to the switching area and the storage area S and ST are stacked. Is formed.

FIG. 4D illustrates a process of ashing the photosensitive pattern 48a. The metal layer corresponding to the center region of the switching region S is processed by the process of ashing the photosensitive pattern 48a. The ashing process proceeds to the extent that (42) is exposed.

In this case, the SF ₆ gas trace and the O ₂ gas trace are used in the process for ashing the photosensitive pattern 48a.

When the process of ashing the photosensitive patterns 48a and 48b is performed, the channel portion CH and the peripheral portion F of the metal layer 42 patterned in the switching region S are exposed and the storage region ( The peripheral portion F of the metal layer 42 patterned on ST is exposed.

At this time, the surface shape of the removed photosensitive pattern is transferred to the metal layer 42 of the channel portion CH as it is.

As shown in FIG. 4E, a process of dry etching the exposed metal layer 42 is performed.

During the dry etching of the metal layer 42, a trace amount of the impurity amorphous silicon layer of the channel part is etched.

At this time, the surface shape of the metal layer on which the surface shape of the photosensitive pattern 48a is transferred as it is is transferred to the impurity amorphous silicon layer 40 as it is.

As shown in FIG. 4F, a process of removing the exposed impurity amorphous silicon layer and the pure amorphous silicon layer below it through dry etching is performed.

At this time, dry etching is performed using a small amount of SF ₆ gas and Cl ₂ gas.

Next, a process of removing the first and second photosensitive patterns 48a and 48b is performed.

In this case, as illustrated in FIG. 4G, the source electrode 50 and the drain electrode 52 spaced apart corresponding to the upper portion of the gate electrode 34 are formed, and the data connected to the source electrode 50 is formed. An interconnection line 54 of FIG. 2 is formed, and an island-shaped metal pattern 56 is formed on a portion of the gate interconnection 32 corresponding to the storage area ST.

In the above-described process, the storage region _ST is formed with the storage capacitor C _ST having the gate wiring 32 as the first electrode and the upper metal pattern 56 as the second electrode.

As described above, the second mask process may be completed through 4a to 4g.

5 is a diagram illustrating a third mask process, and includes silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 30 on which the source and drain electrodes 50 and 52 are formed. A protective film is deposited by depositing one or more materials selected from the group of inorganic insulating materials or by applying one or more materials selected from the group of organic insulating materials including benzocyclobutene (BCB) and an acrylic resin (resin). Form 58.

Subsequently, the passivation layer 58 is patterned by a third mask process to drain the drain contact hole 60 exposing the drain electrode 52 and the storage contact hole 62 exposing the metal pattern 56. Form.

6 is a view illustrating a fourth mask process, and includes indium tin oxide (ITO) and indium zinc oxide (IZO) on the entire surface of the substrate 30 on which the passivation layer 58 is formed. A selected one of the transparent conductive metal oxide groups is deposited and patterned to form a pixel electrode 64 positioned in the pixel region P while simultaneously contacting the drain electrode 52 and the metal pattern 56.

Through the above-described process, an array substrate for a liquid crystal display device can be manufactured using a conventional four mask process.

However, in the above-described process, the ashing process of dry etching the photosensitive pattern in the second mask process and the dry etching process of removing the patterned metal layer exposed to the periphery of the ashed photosensitive pattern are performed twice.

Since such a process uses different gases, when the first dry etching process is completed, there is a problem in that the process time is lengthened by gas exchange and vacuum / exhaust.

In addition, during two successive dry etching processes, since the surface shape of the photosensitive pattern is transferred to the active layer as it is, the surface characteristics of the active layer are not good, which causes problems in stability of the device.

The present invention is to solve the above-mentioned problem, the array substrate manufacturing method according to the present invention is a two-step dry etching process performed in the second mask process of the process of manufacturing the array substrate in a three mask process and a four mask process It is characterized by simplifying to one step.

The present invention simplifies the two dry etching processes in one dry etching step as described above, thereby simplifying the process to improve the mass productivity, and to stabilize the device.

An array substrate for a liquid crystal display device according to the present invention for achieving the above object comprises the steps of preparing a substrate; A first mask process step of forming a gate electrode and a gate wiring on the substrate; Stacking a gate insulating film, a pure amorphous silicon layer, an impurity amorphous silicon layer, a metal layer, and a photosensitive layer on an entire surface of the substrate on which the gate electrode and the gate wiring are formed; Placing a second mask on the spaced upper portion of the photosensitive layer, exposing and developing the photosensitive layer to form a stepped photosensitive pattern corresponding to a direction perpendicular to the gate electrode and the gate wiring; Removing the metal layer exposed to the periphery of the stepped photosensitive pattern, an impurity amorphous silicon layer below it, and a pure amorphous silicon layer; Removing the photosensitive pattern of the lower portion of the photosensitive pattern and the metal layer thereunder through a single step of dry etching; Removing the impurity amorphous silicon layer exposed between the removed metal layers, and defining a pixel region connected to the source electrode and the drain electrode spaced apart from the gate electrode, and connected to the source electrode and perpendicularly crossing the gate wiring; Forming a data line and a stacked active layer and an ohmic contact layer under the source and drain electrodes; A third mask process step of forming a passivation layer formed on an entire surface of the substrate on which the source and drain electrodes are formed and exposing a portion of the drain electrode; And a fourth mask process step of forming a pixel electrode positioned in the pixel region in contact with the exposed drain electrode.

According to another aspect of the present invention, a method of manufacturing an array substrate for a liquid crystal display device includes preparing a substrate; A first mask process step of forming a gate electrode and a gate wiring on the substrate; Stacking a gate insulating film, a pure amorphous silicon layer, an impurity amorphous silicon layer, a metal layer, and a photosensitive layer on an entire surface of the substrate on which the gate electrode and the gate wiring are formed; Placing a second mask on the spaced upper portion of the photosensitive layer and exposing and developing the photosensitive layer to form a stepped photosensitive pattern corresponding to a direction perpendicular to the gate electrode and the gate wiring; Removing the metal layer exposed to the periphery of the stepped photosensitive pattern, an impurity amorphous silicon layer and a pure amorphous silicon layer thereunder; Removing the photosensitive pattern of the lower portion of the photosensitive pattern and the metal layer thereunder through a single step of dry etching; Removing the impurity amorphous silicon layer exposed between the removed metal layers, and defining a pixel region connected to the source electrode and the drain electrode spaced apart from the gate electrode, and connected to the source electrode and perpendicularly crossing the gate wiring; Forming a data line and a stacked active layer and an ohmic contact layer under the source and drain electrodes; And forming a passivation layer formed over the substrate on which the source and drain electrodes are formed and exposing a portion of the drain electrode, and forming a pixel electrode in contact with the drain electrode and positioned in the pixel region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

The first embodiment of the present invention aims to reduce the continuous two-step dry etching process performed in the second mask process into one process in fabricating the array substrate in a four mask process.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to the present invention will be described with reference to the process drawings.

7 is a cross-sectional view illustrating the first mask process.

As illustrated, the substrate 100 is defined as a pixel area P including the switching area S and a storage area ST.

A metal material including aluminum (Al), aluminum alloy (AlNd), or the like is deposited and patterned on the substrate 100 in which the plurality of regions S, P, and ST are defined to correspond to the switching region S. The gate wiring 102 is formed on one side of the pixel electrode P including the gate electrode 104 and the storage area ST.

One or more materials selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) are deposited on the entire surface of the substrate 100 on which the gate electrode 104 and the gate wiring 102 are formed. The gate insulating film 106 is formed.

Subsequently, a pure amorphous silicon layer 108 and an amorphous silicon layer 110 including impurities are stacked on the gate insulating layer 106.

Next, molybdenum (Mo) is deposited on the impurity amorphous silicon layer 110 to form a metal layer 112.

8A to 8G are cross-sectional views illustrating a second mask process.

As shown in FIG. 8A, a photoresist is applied to the entire surface of the substrate 100 on which the metal layer 112 is formed to form a photosensitive layer 116.

The mask M including the transmissive part A1, the reflecting part A2, and the transflective part A3 is positioned on the spaced upper portion of the substrate 100 on which the photosensitive layer 116 is formed.

In this case, when the photosensitive layer 116 is assumed to have a positive characteristic, the photosensitive layer 116 corresponding to the reflective part A2 is not exposed because it is blocked from light, and the transmissive part ( The portion corresponding to A1) is completely exposed from the light, and the portion corresponding to the transflective portion A3 is weakly exposed because the light intensity is weak.

At this time, the transflective portion A3 and the reflecting portion A2 are positioned at one side and the other side with respect to the switching region S, and a part of the gate wiring 102 corresponding to the storage region ST. The reflector A2 is positioned above.

The process of exposing and developing the lower photosensitive layer 46 by irradiating light to the upper portion of the mask (M).

As shown in FIG. 8B, a first photosensitive pattern 118a having a different height corresponding to the switching region S and a second photosensitive pattern 118b corresponding to the storage region ST are formed.

In this case, the first photosensitive pattern 118a is formed corresponding to a direction perpendicular to the switching region S and the gate wiring 102.

As shown in FIG. 8C, the metal layer 112 exposed to the peripheries of the first and second photosensitive patterns 118a and 118b is removed through a wet etch process.

As shown in FIG. 8D, the impurity amorphous silicon layer 110 and the pure amorphous silicon layer 108 exposed to the lower portion of the wet etched metal layer are removed by dry etching.

8E is a diagram illustrating a process of dry etching the photosensitive pattern and the metal layer simultaneously.

That is, while removing the lower portion of the first photosensitive pattern 118a completely, the lower metal layer 112 is also removed at the same time.

In order to pattern the photosensitive pattern (118a, 118b) and a metal layer 112 at the same time, SF, but using a ₆ gas and O ₂ gas etching gas a mixed gas of, SF ₆ gas and O ₂ the ratio of the gas 1: 2 to It is characterized by mixing in the ratio of 1:10.

The ratio of the above-described mixed gas etches the photosensitive patterns 118a and 118b, the metal layer 112, and the gate insulating layer 106, but the impurity amorphous silicon layer 110 and the pure amorphous silicon layer 108 are not etched. Has characteristics.

That is, if the impurity amorphous silicon layer 110 appears as the dry etching process progresses, the etching stops at the portion.

Therefore, since the photosensitive patterns 118a and 118b and the metal layer 112 may be simultaneously etched using only one gas, the dry etching process may be simplified.

In addition, since the etching is stopped in the amorphous silicon layer 110, the dry etching process may prevent the surface morphology of the photosensitive pattern 118a from being transferred to the surface of the amorphous silicon layer 110. .

As shown in FIG. 8F, the impurity amorphous silicon layer 110 exposed between the photosensitive patterns 118a and 118b is removed through dry etching, thereby exposing the lower pure amorphous silicon layer 108.

Subsequently, a process of removing the photosensitive patterns 118a and 118b is performed.

In this case, as shown in FIG. 8G, the source electrode 150 and the drain electrode 152 spaced corresponding to the upper portion of the gate electrode 104 are formed, and the data connected to the source electrode 150 is formed. An interconnection (not shown) is formed, and an island-shaped metal pattern 156 is formed on a portion of the gate interconnection 102 corresponding to the storage area ST.

In this case, when the pure amorphous silicon layer and the impurity amorphous silicon layer stacked under the source and drain electrodes 150 and 152 are a first semiconductor pattern 158, the first semiconductor pattern is disposed below the data line (not shown). A second semiconductor pattern (not shown) extending from 158 is positioned, and a third semiconductor pattern 162 is positioned below the metal pattern 156.

The pure amorphous silicon layer of the first semiconductor pattern 158 is called an active layer 158a, and the impurity amorphous silicon layer is called an ohmic contact layer 158b.

In the above-described process, the storage region _ST is formed with a storage capacitor C _ST having the gate wiring 102 as the first electrode and the upper metal pattern 156 as the second electrode.

As described above, the second mask process may be completed through 8a to 8g.

FIG. 9 illustrates an inorganic layer including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on an entire surface of the substrate 100 on which the source and drain electrodes 150 and 152 are formed, as shown in a third mask process. The protective layer 166 may be deposited by depositing one or more materials selected from the group of insulating materials or by coating one or more materials selected from the group of organic insulating materials including benzocyclobutene (BCB) and an acrylic resin (resin). ).

Subsequently, the passivation layer 166 is patterned in a third mask process to drain the drain contact hole 168 exposing the drain electrode 152 and the storage contact hole 170 exposing the metal pattern 156. Form.

As shown in FIG. 10, one selected from the group of transparent conductive metal oxides including indium tin oxide (ITO) and indium zinc oxide (IZO) on the entire surface of the substrate 100 on which the passivation layer 166 is formed. Is deposited and patterned to form a pixel electrode 172 positioned in the pixel region P while simultaneously contacting the drain electrode 152 and the metal pattern 156.

An array substrate for a liquid crystal display device according to a first embodiment of the present invention can be manufactured through the four mask process as described above.

The second embodiment of the present invention will be described below.

Second Embodiment

The second embodiment of the present invention is characterized by reducing the continuous two-step dry etching process performed in the second mask process to one process in fabricating the array substrate in the three mask process.

11 is a process sectional view showing the first mask process.

As illustrated, the substrate 200 is defined as a pixel area P including the switching area S and a storage area ST.

A metal material including aluminum (Al), aluminum alloy (AlNd), or the like is deposited and patterned on the substrate 200 in which the plurality of regions S, P, and ST are defined to correspond to the switching region S. The gate wiring 202 is formed on one side of the gate electrode 204 and the pixel region P including the storage region ST.

One or more materials selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) are deposited on the entire surface of the substrate 200 on which the gate electrode 204 and the gate wiring 202 are formed. The gate insulating film 206 is formed.

12A to 12G are cross sectional views illustrating a second mask process.

As shown in FIG. 12A, a pure amorphous silicon layer 208 and an amorphous silicon layer 210 including impurities are stacked on the gate insulating layer 206.

Next, molybdenum (Mo) is deposited on the impurity amorphous silicon layer 210 to form a metal layer 212.

A photoresist is applied on the entire surface of the substrate 200 on which the metal layer 212 is formed to form the photosensitive layer 216.

The mask M including the transmissive part A1, the reflecting part A2, and the transflective part A3 is positioned on the spaced upper portion of the substrate 200 on which the photosensitive layer 216 is formed.

In this case, when the photosensitive layer 216 has a positive characteristic, the photosensitive layer 216 corresponding to the reflector A2 is not exposed because it is blocked from light, and thus the transmissive part ( The portion corresponding to A1) is completely exposed from the light, and the portion corresponding to the transflective portion A3 is weakly exposed because the light intensity is weak.

In this case, the transflective portion A3 and the reflecting portion A2 are positioned at one side and the other side with respect to the switching region S, and a part of the gate wiring 202 corresponding to the storage region ST. The reflector A2 is positioned above.

The process of exposing and developing the lower photosensitive layer 216 by irradiating light to the upper portion of the mask (M).

As shown in FIG. 12B, a first photosensitive pattern 218a having a different height corresponding to the switching region S and a second photosensitive pattern 218b are formed corresponding to the storage region ST.

In this case, the first photosensitive pattern 218a is formed corresponding to a direction perpendicular to the switching region and the gate lines S and 202.

As shown in FIG. 12C, the metal layer 212 exposed to the peripheries of the first and second photosensitive patterns 218a and 218b is removed through a wet etch process.

As shown in FIG. 12D, the impurity amorphous silicon layer and the pure amorphous silicon layer exposed to the lower portion of the wet etched metal layer are removed by dry etching.

FIG. 12E illustrates a process of dry etching the photosensitive pattern and the metal layers 218a, 218b, and 212 simultaneously.

In other words, the lower portion of the stepped first photosensitive pattern 218a is completely removed and the lower metal layer 212 is removed.

In order to pattern the photosensitive pattern (218a, 218b) and a metal layer at the same time, but using SF ₆ gas as an etching gas and O ₂ gas in the mixed gas, SF ₆ gas and O ₂ gas ratio of 1: 2 to 1:10 It is characterized by mixing at a ratio of.

The ratio of the above-described mixed gas etches the photosensitive patterns 218a and 218b, the metal layer 212 and the gate insulating layer 206, but the impurity amorphous silicon layer 210 and the pure amorphous silicon layer 208 are not etched. Has characteristics.

In other words, when the impurity amorphous silicon layer 210 appears as the dry etching process progresses, etching stops at the portion.

Accordingly, since the photosensitive patterns 218a and 218b and the metal layer 212 may be simultaneously etched using only one gas, the dry etching process may be simplified.

In addition, since the etching is stopped in the amorphous silicon layer 210, the dry etching process may be prevented from being transferred to the surface of the amorphous silicon layer 210 having a surface shape of the photosensitive patterns 218a and 218b.

As shown in FIG. 12F, the impurity amorphous silicon layer 210 exposed between the photosensitive patterns 218a and 218b is removed through dry etching to expose the lower pure amorphous silicon layer 208.

Subsequently, a process of removing the photosensitive pattern is performed.

In this case, as illustrated in FIG. 12G, the source electrode 250 and the drain electrode 252 spaced apart from the upper portion of the gate electrode 204 are formed, and the data connected to the source electrode 250 is formed. An interconnection (not shown) is formed, and an island-shaped metal pattern 256 is formed on a portion of the gate interconnection 202 corresponding to the storage area ST.

In this case, when the pure amorphous silicon layer and the impurity amorphous silicon layer stacked below the source and drain electrodes 250 and 252 are referred to as a first semiconductor pattern 258, the first semiconductor pattern is disposed below the data line (not shown). A second semiconductor pattern (not shown) extending from 258 is positioned, and a third semiconductor pattern 262 is positioned under the metal pattern 256.

The pure amorphous silicon layer of the first semiconductor pattern 258 is called an active layer 158a, and the impurity amorphous silicon layer is called an ohmic contact layer 158b.

In the above-described process, the storage region _ST is formed with the storage capacitor C _ST having the gate wiring 202 as the first electrode and the upper metal pattern 256 as the second electrode.

13A to 13D are cross sectional views illustrating a third mask process.

As shown in FIG. 13A, one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate 200 on which the source and drain electrodes 250 and 252 are formed. The vapor deposition is performed to form the protective film 264.

Subsequently, a photoresist pattern is formed on the passivation layer 264 and then patterned by a third mask process to form a photosensitive pattern 266.

The photosensitive pattern 266 is formed by exposing a portion of the switching region S, a portion of the storage region ST, and a passivation layer 264 corresponding to the pixel region P.

As shown in FIG. 13B, a process of etching the passivation layer 264 exposed between the photosensitive patterns 266 and the gate insulating layer 206 thereunder is performed.

In this case, a part of the drain electrode 252 and a part of the metal pattern (storage second electrode 234) are exposed.

Subsequently, as shown in FIG. 13C, a transparent conductive metal including indium tin oxide (ITO) and indium zinc oxide (IZO) is formed on the entire surface of the substrate 200 on which the photosensitive pattern 266 is formed. By depositing, the pixel electrode 270 positioned in the pixel region P is formed while contacting the exposed drain electrode 252 and the metal pattern 256.

In this case, since the side surface of the photosensitive pattern 266 is formed to be reverse tapered, the transparent electrode is cut by the reverse taper of the photosensitive pattern 266 even though the transparent electrode is deposited on the entire surface of the substrate 200. Each can be formed in an independent pattern.

Therefore, as described above, by using the protective film as the photosensitive organic film as a mask, it is possible to produce an array substrate for a liquid crystal display device in a three mask process.

Therefore, the array substrate manufacturing method according to the 3 mask process and the 4 mask process according to the present invention can reduce the two dry etching steps performed through separate etching gases in the second mask process to one, thereby simplifying the process. This can shorten the time.

Therefore, there is an effect that can improve the production yield by improving the mass production.

In addition, since the lower amorphous silicon layer is not etched during the process of simultaneously etching the photosensitive pattern and the metal layer, there is an effect of stabilizing the device because it is not transferred directly to the amorphous silicon layer of the surface shape of the photosensitive pattern. .

1 is a plan view schematically illustrating a general liquid crystal display device;

2 is an enlarged plan view enlarging a single pixel of a conventional array substrate for a liquid crystal display device;

3 is a cross-sectional view taken along line III-III of FIG. 2, showing a conventional first mask process;

4A to 4G are diagrams illustrating a second mask process, which is a cross-sectional view of the process according to the process sequence of FIG.

FIG. 5 is a cross-sectional view taken along line III-III of FIG. 2, illustrating a conventional third mask process;

6 is a cross-sectional view taken along line III-III of FIG. 2, showing a conventional fourth mask process;

7 is a cross-sectional view illustrating a first mask process according to the first embodiment;

8A to 8G are process cross-sectional views illustrating a second mask process according to a first embodiment according to a process sequence;

9 is a cross-sectional view illustrating a third mask process according to the first embodiment;

10 is a cross-sectional view illustrating the fourth mask process according to the first embodiment;

11 is a process sectional view showing the first mask process according to the second embodiment,

12A to 12G are process cross-sectional views illustrating a second mask process according to a second embodiment according to a process sequence;

13A to 13D are cross-sectional views illustrating a third mask process according to a second embodiment in a process sequence.

<Description of the symbols for the main parts of the drawings>

100: substrate 102: gate wiring

104: gate electrode 106: gate insulating film

108: pure amorphous silicon layer 110: impurity amorphous silicon layer

112: metal layer 118a, 118b: photosensitive layer

Claims (16)

Preparing a substrate; A first mask process step of forming a gate electrode and a gate wiring on the substrate; Stacking a gate insulating film, a pure amorphous silicon layer, an impurity amorphous silicon layer, a metal layer, and a photosensitive layer on an entire surface of the substrate on which the gate electrode and the gate wiring are formed; Placing a second mask on the spaced upper portion of the photosensitive layer, exposing and developing the photosensitive layer to form a stepped photosensitive pattern corresponding to a direction perpendicular to the gate electrode and the gate wiring; Removing the metal layer exposed to the periphery of the stepped photosensitive pattern, an impurity amorphous silicon layer below it, and a pure amorphous silicon layer; Removing the photosensitive pattern of the lower portion of the photosensitive pattern and the metal layer thereunder through a single step of dry etching; Removing the impurity amorphous silicon layer exposed between the removed metal layers, and defining a pixel region connected to the source electrode and the drain electrode spaced apart from the gate electrode, and connected to the source electrode and perpendicularly crossing the gate wiring; Forming a data line and a stacked active layer and an ohmic contact layer under the source and drain electrodes; A third mask process step of forming a passivation layer formed on an entire surface of the substrate on which the source and drain electrodes are formed and exposing a portion of the drain electrode; A fourth mask process step of forming a pixel electrode positioned in the pixel region while being in contact with the exposed drain electrode Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 1, In the second mask process, the etching gas for simultaneously dry etching the lower portion of the stepped photosensitive pattern and the metal layer thereunder is a gas in which SF ₆ and O ₂ are mixed 1: 2 to 1:10. Method of manufacturing array substrate for display device. The method of claim 1, And said second mask comprises a reflecting portion, a transmissive portion, and a transflective portion. The method according to any one of claims 1 to 3, And the stepped photosensitive pattern is formed by exposure and development in correspondence with the reflecting portion and the semi-transmissive portion of the second mask. The method of claim 1, In the second mask process, The metal layer exposed to the periphery of the stepped photosensitive pattern is removed by wet etching, and the impurity amorphous silicon layer and the pure amorphous silicon layer beneath it are removed by dry etching. The method of claim 1, And forming an island-shaped metal pattern in a region corresponding to a portion of the gate wiring in the second mask process. The method of claim 6, And a storage capacitor having the metal pattern as a first electrode and a lower gate wiring as a second electrode, wherein the storage capacitor is formed. Preparing a substrate; A first mask process step of forming a gate electrode and a gate wiring on the substrate; Stacking a gate insulating film, a pure amorphous silicon layer, an impurity amorphous silicon layer, a metal layer, and a photosensitive layer on an entire surface of the substrate on which the gate electrode and the gate wiring are formed; Placing a second mask on the spaced upper portion of the photosensitive layer and exposing and developing the photosensitive layer to form a stepped photosensitive pattern corresponding to a direction perpendicular to the gate electrode and the gate wiring; Removing the metal layer exposed to the periphery of the stepped photosensitive pattern, an impurity amorphous silicon layer and a pure amorphous silicon layer thereunder; Removing the photosensitive pattern of the lower portion of the photosensitive pattern and the metal layer thereunder through a single step of dry etching; Removing the impurity amorphous silicon layer exposed between the removed metal layers, and defining a pixel region connected to the source electrode and the drain electrode spaced apart from the gate electrode, and connected to the source electrode and perpendicularly crossing the gate wiring; Forming a data line and a stacked active layer and an ohmic contact layer under the source and drain electrodes; A third mask process step of forming a passivation layer formed on an entire surface of the substrate on which the source and drain electrodes are formed and exposing a portion of the drain electrode and a pixel electrode in contact with the drain electrode and positioned in the pixel region; Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 8, In the second mask process, the etching gas for simultaneously dry etching the lower portion of the stepped photosensitive pattern and the metal layer thereunder is a gas in which SF ₆ and O ₂ are mixed 1: 2 to 1:10. Method of manufacturing array substrate for display device. The method of claim 8, And said second mask comprises a reflecting portion, a transmissive portion, and a transflective portion. The method according to any one of claims 8 to 10, And wherein the stepped photosensitive pattern is formed as a result of exposure and development in correspondence with the reflecting portion and the semi-transmissive portion of the second mask. The method of claim 8, In the second mask process, The metal layer exposed to the periphery of the stepped photosensitive pattern is removed by wet etching, and the impurity amorphous silicon layer and the pure amorphous silicon layer beneath it are removed by dry etching. The method of claim 8, And forming an island-shaped metal pattern in a region corresponding to a portion of the gate wiring in the second mask process. The method of claim 13, And a storage capacitor having the metal pattern as a first electrode and a lower gate wiring as a second electrode, wherein the storage capacitor is formed. The method of claim 8, The third mask process step Forming a protective film on an entire surface of the substrate on which the source and drain electrodes are formed; Forming a photosensitive pattern exposing a portion of the drain electrode and a passivation layer corresponding to the pixel area in a third mask process corresponding to the upper portions of the source and drain electrodes; Exposing a portion of the drain electrode by removing the passivation layer exposed between the photosensitive patterns; Forming a transparent electrode layer on an entire surface of the substrate from which the protective film is removed; Removing the photosensitive pattern to form a pixel electrode positioned in the pixel region while being in contact with the drain electrode; Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 15, And the transparent electrode layer is formed of one selected from the group consisting of transparent conductive oxides including indium tin oxide (ITO) and indium zinc oxide (IZO).