KR101028607B1 - 디스플레이 가능한 컨텐츠의 부분들을 선택적으로 이중 버퍼링하기 위한 장치 및 방법 - Google Patents

디스플레이 가능한 컨텐츠의 부분들을 선택적으로 이중 버퍼링하기 위한 장치 및 방법 Download PDF

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KR101028607B1
KR101028607B1 KR1020097000016A KR20097000016A KR101028607B1 KR 101028607 B1 KR101028607 B1 KR 101028607B1 KR 1020097000016 A KR1020097000016 A KR 1020097000016A KR 20097000016 A KR20097000016 A KR 20097000016A KR 101028607 B1 KR101028607 B1 KR 101028607B1
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South Korea
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display
rendered
selected group
rendering
display elements
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KR20090019001A (ko
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자콥 벤자민 블라우코프
니콜라스 칼 브룩
스테판 제오프레이 불틴
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콸콤 인코포레이티드
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • User Interface Of Digital Computer (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Image Generation (AREA)
KR1020097000016A 2006-06-01 2007-05-31 디스플레이 가능한 컨텐츠의 부분들을 선택적으로 이중 버퍼링하기 위한 장치 및 방법 Expired - Fee Related KR101028607B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US80363306P 2006-06-01 2006-06-01
US60/803,633 2006-06-01
US11/755,732 2007-05-30
US11/755,732 US8004535B2 (en) 2006-06-01 2007-05-30 Apparatus and method for selectively double buffering portions of displayable content

Publications (2)

Publication Number Publication Date
KR20090019001A KR20090019001A (ko) 2009-02-24
KR101028607B1 true KR101028607B1 (ko) 2011-04-11

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KR1020097000016A Expired - Fee Related KR101028607B1 (ko) 2006-06-01 2007-05-31 디스플레이 가능한 컨텐츠의 부분들을 선택적으로 이중 버퍼링하기 위한 장치 및 방법

Country Status (7)

Country Link
US (1) US8004535B2 (https=)
EP (1) EP2038874A2 (https=)
JP (1) JP5350227B2 (https=)
KR (1) KR101028607B1 (https=)
CN (1) CN101454823B (https=)
IN (1) IN266729B (https=)
WO (1) WO2007143511A2 (https=)

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US20090305782A1 (en) * 2008-06-10 2009-12-10 Oberg Gregory Keith Double render processing for handheld video game device
JP5458524B2 (ja) * 2008-08-04 2014-04-02 富士通モバイルコミュニケーションズ株式会社 携帯端末
US8448074B2 (en) * 2009-05-01 2013-05-21 Qualcomm Incorporated Method and apparatus for providing portioned web pages in a graphical user interface
US20110066971A1 (en) * 2009-09-14 2011-03-17 Babak Forutanpour Method and apparatus for providing application interface portions on peripheral computing devices
US8823721B2 (en) * 2009-12-30 2014-09-02 Intel Corporation Techniques for aligning frame data
US8643658B2 (en) * 2009-12-30 2014-02-04 Intel Corporation Techniques for aligning frame data
JP5793082B2 (ja) * 2010-06-24 2015-10-14 パナソニック インテレクチュアル プロパティ コーポレーション オブアメリカPanasonic Intellectual Property Corporation of America 電子出版物閲覧装置、電子出版物閲覧方法、プログラム、及び集積回路
WO2012006741A1 (en) * 2010-07-14 2012-01-19 Research In Motion Limited Methods and apparatus to draw animations
JP5829626B2 (ja) * 2011-01-07 2015-12-09 シャープ株式会社 再生装置、再生装置の制御方法、生成装置、生成装置の制御方法、制御プログラム、及び該プログラムを記録した記録媒体
US8847970B2 (en) 2012-04-18 2014-09-30 2236008 Ontario Inc. Updating graphical content based on dirty display buffers
US10482165B2 (en) * 2015-03-18 2019-11-19 Microsoft Technology Licensing, Llc Declarative cascade reordering for styles
KR102261961B1 (ko) 2015-05-19 2021-06-07 삼성전자주식회사 디스플레이 구동 회로 및 이를 포함하는 디스플레이 장치
KR101717355B1 (ko) 2015-07-29 2017-03-16 엘에스산전 주식회사 에너지 관리 시스템의 디스플레이 장치 및 방법
US20170243322A1 (en) * 2016-02-19 2017-08-24 Remi Sigrist Multiple frame buffering for graphics processing
WO2018020647A1 (ja) * 2016-07-28 2018-02-01 富士通株式会社 描画データ生成プログラム、描画データ生成装置、及び描画データ生成方法

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US20020085013A1 (en) 2000-12-29 2002-07-04 Lippincott Louis A. Scan synchronized dual frame buffer graphics subsystem

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US20020085013A1 (en) 2000-12-29 2002-07-04 Lippincott Louis A. Scan synchronized dual frame buffer graphics subsystem

Also Published As

Publication number Publication date
WO2007143511A2 (en) 2007-12-13
IN266729B (https=) 2015-05-28
CN101454823B (zh) 2011-03-30
JP5350227B2 (ja) 2013-11-27
JP2009539147A (ja) 2009-11-12
CN101454823A (zh) 2009-06-10
US20070291037A1 (en) 2007-12-20
KR20090019001A (ko) 2009-02-24
EP2038874A2 (en) 2009-03-25
WO2007143511A3 (en) 2008-01-31
US8004535B2 (en) 2011-08-23

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