KR101010447B1 - Array substrate for LCD and the fabrication method thereof - Google Patents

Abstract

The present invention relates to a flat panel display device capable of preventing electrostatic defects.

The present invention forms a structure that can dissipate or block the static electricity generated in the outer driving circuit portion of the array substrate for the liquid crystal display device, thereby effectively preventing the electrostatic defects generated during the manufacturing process, thereby preventing a decrease in the manufacturing yield of the liquid crystal panel. In addition, the dummy pattern is formed in the driving circuit to eliminate the potential defect caused by static electricity in the liquid crystal display, thereby completely eliminating the static electricity source, thereby improving the reliability of the product.

Static electricity, dummy pattern, drive circuit, short circuit

Description

Array substrate for LCD and manufacturing method thereof

1 is a plan view showing a liquid crystal display device using a conventional polysilicon thin film transistor.

2 is a cross-sectional view illustrating a driving element of a driving circuit unit in a conventional liquid crystal display.

FIG. 3 is a view schematically showing a layout of the driving portion in a conventional liquid crystal display. FIG.

4 is a cross-sectional view taken along line AA ′ in FIG. 3.

FIG. 5 is a view schematically illustrating a driving circuit part layout of an outer portion of an array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention. FIG.

6 is a cross-sectional view taken along line B-B 'and C-C' in FIG.

FIG. 7 is a view schematically showing a driving circuit portion layout of an outer portion of an array substrate for a liquid crystal display device in one embodiment according to the present invention. FIG.

8 is a cross-sectional view taken along line D-D 'and E-E' of FIG. 7.

FIG. 9 is a schematic view showing a driving circuit portion layout of an outer portion of an array substrate for a liquid crystal display device according to another embodiment of the present invention. FIG.                 

FIG. 10 is a cross-sectional view taken along the line F-F ′ of the dummy pattern in FIG. 9; FIG.

<Description of Signs of Major Parts of Drawings>

316, 416: buffer film 320, 420: substrate

342 and 442: gate insulating film 348: protective film

356: interlayer insulating film 366, 466: gate electrode

374 and 474 active layer 374S source region

374D: drain region 374C: channel region

384S: Source Contact Hole 384D: Drain Contact Hole

388, 388a, 388b, 488a, 488b: gate wiring

389: short circuit connection metal

455: dummy active layer 456: dummy gate pattern

The present invention relates to a flat panel display device capable of preventing an electrostatic defect.

In general, a flat panel display device includes a liquid crystal display device (LCD), a plasma display panel (PDP), a field emission display (FED), and the like.

Here, the liquid crystal display adjusts the light transmittance of the liquid crystal cells according to the video signal, thereby displaying an image corresponding to the video signal on the liquid crystal panel in which the liquid crystal cells are arranged in a matrix form.

In this case, a thin film transistor (TFT) is usually used as an element for switching liquid crystal cells.

The thin film transistor used in the liquid crystal display device uses amorphous silicon or polysilicon as a semiconductor layer.

The amorphous silicon thin film transistor has the advantage that the uniformity of the amorphous silicon film is relatively good and the characteristics are stable.

However, the amorphous silicon thin film transistor has a disadvantage in that the response speed is low due to low charge mobility.

Accordingly, the amorphous silicon thin film transistor has a disadvantage in that it is difficult to apply to a driving device of a high resolution display panel, a gate driver, and a data driver requiring fast response speed.

As the polysilicon thin film transistor has a high charge mobility, the polysilicon thin film transistor is not only suitable for a high resolution display panel requiring a fast response speed but also has an advantage of embedding peripheral driving circuits in the display panel.

Accordingly, liquid crystal displays using the polysilicon thin film transistors have emerged.

1 is a plan view illustrating a liquid crystal display using a conventional polysilicon thin film transistor.

Referring to FIG. 1, a liquid crystal display using a conventional polysilicon thin film transistor includes an image display unit 196 including a pixel matrix and a data driver for driving the data lines 104 of the image display unit 196. 192 and a gate driver 192 for driving the gate wires 102 of the image display unit 196.

In the image display unit 196, liquid crystal cells are arranged in a matrix to display an image.

Each of the liquid crystal cells is driven by a thin film transistor (TFT) using polysilicon implanted with n-type (or p-type) impurities as a switching element connected to the intersection of the gate wiring 102 and the data wiring 104.

The n-type thin film transistor 130 (or p-type thin film transistor) causes the video signal, that is, the pixel signal, from the data line 104 to be charged in the liquid crystal cell in response to a scan pulse from the gate line 102. The liquid crystal cell adjusts the light transmittance according to the charged pixel signal.

The gate driver 194 sequentially drives the gate lines 102 by a horizontal period for each frame by gate control signals.

The thin film transistors are sequentially turned on in the horizontal wiring unit by the gate driver 194 to connect the data wiring 104 to the liquid crystal cell.

The data driver 192 samples a plurality of digital data signals every horizontal period and converts the digital data signals into analog data signals.

The data driver 192 supplies an analog data signal to the data lines 104.                         

Accordingly, the liquid crystal cells connected to the turned-on thin film transistors adjust light transmittance in response to data signals from each of the data lines 104.

The gate driver 194 and the data driver 192 are composed of a plurality of thin film transistors.

The driving device is composed of one large thin film transistor having a large channel width W1 so that a relatively large amount of current can flow for switching of a relatively high voltage.

Such a driving device uses poly-silicon for fast response speed.

As such, a control clock for controlling the operation of the driving circuit is required in a structure in which the driving circuit is incorporated in the display panel, and the control clock is used every stage (about 480 stages in the case of the VGA gate driving circuit).

In this case, when the length of the wire drawn into the driving circuit is long, there is a problem that break-down occurs at a specific part by static electricity during the manufacturing process.

Here, the same applies to the p-type thin film transistor as well as the n-type thin film transistor mentioned as the above embodiment.

2 is a cross-sectional view illustrating a driving element of a driving circuit unit in a conventional liquid crystal display.

As shown in FIGS. 1 and 2, the gate driving circuit unit includes a plurality of thin film transistor elements, a plurality of control clocks, and power lines for controlling the operation of the thin film transistor elements.

The driving device including one thin film transistor includes an active layer 174 implanted with impurities (for example, n + ions or p + ions) formed on the lower substrate 120 with the buffer layer 116 interposed therebetween. And a gate electrode 166 formed to overlap the channel region 174c of the active layer 174 with the gate insulating layer 142 interposed therebetween, and the gate electrode 166 and the interlayer insulating layer 156 interposed therebetween. The source electrode 168, the drain electrode 170, and the passivation layer 148 formed on the source electrode 168 and the drain electrode 170 are provided.

The source electrode 168 and the drain electrode 170 may have an active layer 174 implanted with a predetermined impurity through the source / drain contact holes 184S and 184D passing through the gate insulating layer 142 and the interlayer insulating layer 156. Contact source / drain regions 174S and 174D, respectively.

The passivation layer 148 is formed on the source electrode 168 and the drain electrode 170 to protect the driving element.

3 is a view schematically illustrating a layout of a driving circuit unit in a conventional liquid crystal display, and FIG. 4 is a cross-sectional view taken along line AA ′ of FIG. 3.

At this time, the layout of the driving circuit portion shown in FIG. 3 shows a case where only the active layer and the gate wiring are formed.

4A is a schematic cross-sectional view taken along the line A-A 'of the driving circuit shown in FIG. 3, and FIG. 4B is a photograph showing a defect due to static electricity generated between the active layer and the gate wiring.

3 and 4A, a buffer layer 216 is formed on the substrate 220, and an active layer 201 pattern is formed on the buffer layer 216 at the lowermost layer. The gate insulating film 142 is formed on the 201 pattern.

A gate electrode 266, a gate pad 287, and a gate wiring 288 are formed on the gate insulating layer 242 using a gate metal.

At this time, after the active layer 201 and the gate wiring 288 are formed in the gate driving circuit unit, there is a problem that the process is very vulnerable to static electricity before the source and drain electrodes are formed.

The reason for this is that, as shown in Figs. 3 and 4A, the conductive layer 201 and the gate electrode 266 are already formed, and the regions where they cross vertically have a capacitor structure. to be.

Therefore, an electrostatic charge generated during the process flows into the gate wiring 288 and is driven to the intersection of the active layer 201 and the gate electrode 266 to cause break-down. do.

In this case, the long length 'L' of the gate wiring 288 acts as a kind of antenna to easily cause static electricity, and the longer the wiring length 'L', the greater the probability of generating static electricity (S).

As described above, when a short occurs between the gate wiring 288 and the active layer 201, a fatal defect is caused in the embedded circuit.                         

For example, in the liquid crystal panel of the XGA class model, the gate driving circuit unit is composed of a repetitive array of 768 stages, and there are dozens of thin film transistor elements in the gate driving circuit of each stage. 10,000 thin film transistor elements are formed. Among these, assuming that the number of thin film transistors having a structure susceptible to static electricity is about 10%, there is a possibility of causing static electricity to about 1000 thin film transistors.

When the driving circuit defect occurs due to the static electricity generated as described above, there is a problem that the yield of the liquid crystal panel is lowered.

The present invention provides an array substrate for a liquid crystal display device which prevents electrostatic defects generated in a manufacturing process by forming a structure capable of dissipating or blocking static electricity generated in an outer driving circuit portion of an array substrate for a liquid crystal display device, and manufacturing the same. The purpose is to provide a method.

In order to achieve the above object, an embodiment of an array substrate for a liquid crystal display device according to the present invention includes an image display unit including a plurality of liquid crystal cells formed at each intersection of gate lines and data lines, and an outer portion of the image display unit. In the liquid crystal panel, a gate wiring for applying a driving signal to the image display unit is at least one short circuit before a driving switch element made of a thin film transistor. It is characterized by having a wealth.

The gate wiring shorted by the short circuit is electrically connected by a short circuit connecting metal when the data wiring is formed.

A dummy gate pattern may be further formed between the gate line to which the external input signal is input and a short circuit portion, with a dummy active layer and an insulating layer interposed therebetween.

The driving switch element includes an active layer made of polycrystalline silicon on a substrate, a gate electrode formed on the active layer with a gate insulating film interposed therebetween, and a source and drain electrode formed on the gate electrode with an interlayer insulating film interposed therebetween. Characterized in that it is formed to include.

In addition, another embodiment of an array substrate for a liquid crystal display device according to the present invention in order to achieve the above object is an image display unit including a plurality of liquid crystal cells formed for each intersection region of the gate wirings and the data wirings, and the image display portion In a liquid crystal panel disposed in an outer region of the liquid crystal panel for supplying driving signals required by driving circuits for driving liquid crystal cells, at least one gate wiring for applying a driving signal to the image display unit is formed before a driving switch element formed of a thin film transistor. The above-mentioned short circuit portion is characterized in that a dummy gate pattern is formed in the shorted gate wiring with a dummy active layer and an insulating layer interposed therebetween.

The gate wiring shorted by the short circuit is electrically connected by a short circuit connecting metal when the data wiring is formed.                     

In addition, a method of manufacturing a liquid crystal display device according to the present invention as an embodiment for achieving the above object, an image display unit including a plurality of liquid crystal cells formed for each intersection region of the gate wirings and the data wirings, and the image display unit In the manufacturing of a liquid crystal display device having a drive switch element consisting of a plurality of thin film transistors (TFT) and a plurality of control clocks for controlling the gate driver circuit portion of the outer portion of the gate driving circuit portion, Forming a gate wiring having at least one short circuit portion before the driving switch element at an input portion supplied to an image display portion; And forming a short circuit connection part using a data wiring material with an insulating layer therebetween on the short circuit part.

The method may further include forming a dummy active layer between the gate line to which the external input signal is input and the short circuit unit before forming the gate line.

The forming of the gate line may further include forming a dummy gate pattern on the dummy active layer to form a capacitor with the insulating layer interposed therebetween.

In addition, another example of a method of manufacturing an array substrate for a liquid crystal display device according to the present invention for achieving the above object is an image display unit including a plurality of liquid crystal cells formed for each intersection region of the gate wirings and the data wirings; In the manufacturing of a liquid crystal display device having a drive switch element consisting of a plurality of thin film transistors (TFTs) and a plurality of control clocks for controlling the same in the gate driving circuit portion of the outer portion of the image display portion, the thin film on the substrate Forming an active layer and a dummy active layer of the transistor; Forming a gate wiring having at least one short circuit portion before the driving switch element at an input portion for supplying input signals from the outside to the image display portion; And forming a short circuit connection part using a data wiring material with an insulating layer therebetween on the short circuit part.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

<First Embodiment>

FIG. 5 is a diagram schematically illustrating a driving circuit part layout of an outer portion of an array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 6 is B-B 'and C- in FIG. 5. Figure showing a cross section cut by C '.

Here, the driving circuit part shown in FIG. 5 is a layout which has progressed to the active layer and the gate wiring formation process.

As shown in FIGS. 5 and 6, the driving element B-B ′ including the thin film transistor TFT is formed on the lower substrate 320 with the buffer layer 316 interposed therebetween. For example, the active layer 374 forming the source / drain regions 374S and 374D implanted with n + ions or p + ions, and the channel region 374c of the active layer 374 with the gate insulating layer 342 interposed therebetween. There is a gate electrode 366 formed to overlap with the gate circuit 388 and a gate wiring 388 for applying a clock signal for controlling the operation of the thin film transistor in the driving circuit unit.

Referring to FIG. 6, a buffer layer 316 is formed on a substrate 320, and an active layer 374 pattern is formed on the buffer layer 316.

In addition, a gate insulating layer 342 is formed on the active layer 374 pattern.

A gate wiring 388b connected to the thin film transistor TFT is formed on the gate insulating layer 342 as a gate metal.

At this time, if the length 'L' of the gate wiring 388 is long, the active layer 374 and the gate wiring 388 are formed in the gate driving circuit part, and then, the process is very susceptible to static electricity in the process before the source and drain electrodes are formed. Therefore, the short circuit part C-C 'is formed to prevent the gate wirings 388a and 388b from being split.

As a result, a short circuit portion may be formed in the gate line 388 having a high rate of static electricity generation to prevent static electricity.

Gate wirings 388a and 388b separated by the short circuit portion are connected in a later source and drain process.

Therefore, the 'M' region of the gate wiring 388 is a region that does not overlap with the active layer 374, and a defect does not occur due to external static electricity.

In the gate line 388, an 'N' region overlaps the active layer 374 and is connected to the gate electrode 366 in the thin film transistor, and is not formed long from the active layer 374 and extends over a minimum region. Because of their distribution, they are less susceptible to static electricity.

Thus, the 'M' and 'N' regions of the gate lines 388a and 388b are formed to be separated from each other by a short circuit portion, and are then connected when forming source and drain electrodes.

FIG. 7 is a view schematically illustrating a driving circuit part layout of an outer portion of an array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 8 is a view illustrating D-D ′ and E− in FIG. 7. The figure which shows the cross section cut by E '.

Here, the driving circuit unit shown in FIG. 7 shows a layout that proceeds to the source and drain electrode forming process.

In the liquid crystal display device having the embedded circuit on the lower substrate 320, a plurality of control clocks for controlling operations of the plurality of TFTs and the corresponding TFT transistors may be provided in the gate driving circuit part of the outer edge of the array substrate. (399).

Here, in the drawings described with reference to FIGS. 7 and 8, 5 and 7, the description of the same reference numerals will be omitted.

As shown in FIGS. 7 and 8, the source electrode 368, the drain electrode 370, and the source electrode 368 are insulated from the gate electrode 366 and the interlayer insulating layer 356 therebetween. A protective film 348 formed on the drain electrode 370 is provided.

The source electrode 368 and the drain electrode 370 have an active layer 374 implanted with a predetermined impurity through the source / drain contact holes 384S and 384D passing through the gate insulating layer 342 and the interlayer insulating layer 356. Are in contact with the source / drain regions 374S and 374D, respectively.

The passivation layer 348 is formed on the source electrode 368 and the drain electrode 370 to protect the driving element.

In addition, the 'M' and 'N' regions of the gate lines 388a and 388b are separated from each other in the short circuit portion, and then, when the source and drain electrodes 368 and 370 are formed, the short interconnect metal 389 is formed. Are electrically connected by

Accordingly, it is possible to prevent a panel failure due to static electricity, which may occur up to the process steps of forming the source and drain electrodes 368 and 370.

&Lt; Embodiment 2 >

FIG. 9 is a view schematically illustrating a driving circuit part layout of an outer portion of an array substrate for a liquid crystal display device according to another exemplary embodiment of the present invention, and FIG. 10 illustrates a dummy pattern F-F ′ in FIG. 9. Figure showing a cross section cut into.

Here, the driving circuit portion shown in Fig. 9 is a layout that has advanced to the active layer and the gate wiring formation process.

9 and 10, in a liquid crystal display having an embedded circuit in a lower substrate, a plurality of control clocks for controlling operations of a plurality of thin film transistors (TFTs) and the corresponding elements in a gate driving circuit portion of an outer edge of an array substrate. (control clock)

If the lengths of the gate wires 488a and 488b are long, the active circuit 474 and the gate electrode 466 are formed in the gate driving circuit part, and are short-circuited because they are very susceptible to static electricity in the process before the source and drain electrodes are formed. To prevent this by forming a portion (Z).

The gate wires 488a and 488b are connected to the thin film transistors having different lengths 'L' in order to apply a control clock signal from the driving circuit part. It can prevent.

The gate lines 488a and 488b separated by the short circuit portion Z are connected in a later source and drain process.

Therefore, the 'M' region of the gate wiring 488a is a region that does not overlap with the acti- tion layer, and defects are not generated by external static electricity.

The 'N' region of the gate wiring 488b overlaps the active layer 474 and is connected to the gate electrode 466 in the thin film transistor, and is not formed long from the active layer 474 and extends over a minimum region. Because of their distribution, they are less susceptible to static electricity.

In addition, a dummy pattern is formed at a predetermined position of the 'M' region, which is a region that does not overlap with the active layer, in the gate wiring 488a, and thus, an electrostatic source that flows into the panel when an electrostatic (S) defect occurs. By eliminating (electro-static charge) in the dummy pattern, the possibility of potential defects can be eliminated.

In the dummy pattern, the dummy active layer 455 and the dummy gate pattern 456 which are already conductive in the dummy pattern are formed, and the regions S vertically intersecting thereof have a capacitor structure, which is generated during the process. The reason is that an electrostatic source flows into the gate line and is driven to the intersection where the dummy active layer 455 and the dummy gate pattern 456 cross each other, causing breakdown.

The electrostatic source generated as described above is converted into heat energy by the breakdown and then extinguished, thereby reducing the potential possibility of generating a defect in a later process.

Thereafter, the 'M' and 'N' regions of the gate lines 488a and 488b are separated from each other by the short circuit portion Z, and are then connected when the source and drain electrodes are formed.

Referring to FIG. 10, a buffer layer 416 is formed on a substrate 420, and a dummy active layer pattern 455 is formed on the buffer layer 416.

A gate insulating layer 442 is formed on the dummy active layer pattern 455.

A dummy gate pattern 456 is formed on the gate insulating layer 442 to be connected to a predetermined position of the 'M' region of the gate line 488a using a gate metal.

As described above, a defect may occur due to a short circuit due to the generation of static electricity at the position S at which the dummy active layer 455 overlaps the dummy gate pattern 456, which is a gate wiring connected to the dummy gate pattern 456. Since 488a is not electrically connected to the gate electrode of the thin film transistor, no defect occurs.

In addition, since the electrostatic source is converted into thermal energy and extinguished in the dummy active layer 455 and the dummy gate pattern 456, the electrostatic source that may exist temporarily on the panel is completely removed.                     

Although the present invention has been described in detail with reference to specific examples, this is for describing the present invention in detail, and the array substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention are not limited thereto, and the technical concept of the present invention is defined. It will be apparent to those skilled in the art that modifications and variations are possible.

The present invention forms a structure that can dissipate or block the static electricity generated in the outer driving circuit portion of the array substrate for the liquid crystal display device, thereby effectively preventing the electrostatic defects generated during the manufacturing process, thereby preventing a decrease in the manufacturing yield of the liquid crystal panel. It can work.

In addition, the present invention has the effect of improving the reliability of the product by completely disappearing the static electricity source by forming a dummy pattern in the driving circuit in order to remove the potential defect caused by the static electricity in the liquid crystal display device.

Claims (10)

An image display unit including a plurality of liquid crystal cells formed at intersections of the gate lines and the data lines, and a liquid crystal display for supplying driving signals required by driving circuits disposed in an outer region of the image display unit to drive the liquid crystal cells; An array substrate for an apparatus, The gate wiring for applying a driving signal to the image display unit has at least one short circuit portion before the driving switch element made of a thin film transistor, The gate wiring of the first region does not overlap with the active layer based on the short circuit portion, And the gate wiring of the second region is connected to the gate electrode by overlapping the active layer of the thin film transistor with respect to the short circuit portion. The method of claim 1, And the gate wiring shorted by the short circuit portion is electrically connected by a short circuit connection metal when the data wiring is formed. The method of claim 1, And a dummy gate pattern is formed between the gate wiring and the short circuit portion with a dummy active layer and an insulating layer interposed therebetween. The method of claim 1, The driving switch element includes an active layer made of polycrystalline silicon on a substrate, a gate electrode formed on the active layer with a gate insulating film interposed therebetween, and a source and drain electrode formed on the gate electrode with an interlayer insulating film interposed therebetween. Array substrate for a liquid crystal display device comprising a. An image display unit including a plurality of liquid crystal cells formed at intersections of the gate lines and the data lines, and a liquid crystal display for supplying driving signals required by driving circuits disposed in an outer region of the image display unit to drive the liquid crystal cells; An array substrate for an apparatus, The gate wiring for applying a driving signal to the image display unit has at least one short circuit portion before the driving switch element made of a thin film transistor, The gate wiring of the first region does not overlap with the active layer based on the short circuit portion, The gate wiring of the second region is connected to the gate electrode by overlapping with the active layer of the thin film transistor based on the short circuit portion. And a dummy active layer and an insulating film are formed between the gate wiring and the short circuit portion, and a dummy gate pattern is formed between the dummy active layer and the insulating film. The method of claim 5, And the gate wiring shorted by the short circuit portion is electrically connected by a short circuit connection metal when the data wiring is formed. An image display unit including a plurality of liquid crystal cells formed at each intersection of the gate lines and the data lines; In the method for manufacturing an array substrate for a liquid crystal display device having two control clocks, Forming a gate wiring having at least one short circuit portion before the driving switch element at an input portion for supplying input signals from an external portion to the image display portion; Forming a short circuit connection portion using a data wiring material with an insulating layer therebetween on the short circuit portion, The gate wiring of the first region does not overlap with the active layer based on the short circuit portion, The gate wiring of the second region is connected to the gate electrode overlapping the active layer of the thin film transistor based on the short circuit portion. The method of claim 7, wherein Prior to forming the gate wiring, And forming a dummy active layer between the gate wiring and the short circuit portion. The method of claim 8, In the forming of the gate wiring, And forming a dummy gate pattern on the dummy active layer to form a capacitor with an insulating film interposed therebetween. An image display unit including a plurality of liquid crystal cells formed at each intersection of the gate lines and the data lines; In the method for manufacturing an array substrate for a liquid crystal display device having two control clocks, Forming an active layer and a dummy active layer of the thin film transistor on a substrate; Forming a gate wiring having at least one short circuit portion before the driving switch element at an input portion for supplying input signals from the outside to the image display portion; Forming a short circuit connection portion using a data wiring material with an insulating layer therebetween on the short circuit portion, The gate wiring of the first region does not overlap with the active layer based on the short circuit portion, The gate wiring of the second region is connected to the gate electrode overlapping the active layer of the thin film transistor based on the short circuit portion.

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