KR102454961B1 - Display device and gate driver - Google Patents

Abstract

The present embodiments provide a pixel region in which two or more pixels are disposed on a plastic substrate, two or more gate driver integrated circuits each including at least one transistor disposed on one surface of the plastic substrate and supplying a gate signal to the pixels, and a gate Provided are a display device and a gate driver thereof, which are disposed adjacent to a transistor included in driver integrated circuits and include a wiring portion to which a voltage having a polarity opposite to that of a doped polarity is applied to an active layer of the transistor.

Description

DISPLAY DEVICE AND GATE DRIVER

The present embodiments relate to a display device and a gate driver included in the display device.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Accordingly, in recent years, various types of display devices such as a liquid crystal display device, a plasma display device, and an organic light emitting display device have been utilized.

Such a display device includes a display panel in which a plurality of gate lines and a plurality of data lines are disposed and a plurality of pixels defined in a region where the gate lines and the data lines intersect, a gate driver driving the gate lines, and a data line It includes a data driver for driving the , a controller for controlling the gate driver and the data driver, and the like.

Recently, when a plastic substrate is used, various types of defects occur in the process of commercializing a display device according to a change in characteristics of a gate driver, which is an obstacle to commercialization.

It is an object of the present embodiments to provide a display device and a gate driver that do not cause a horizontal band defect when driving when a plastic substrate is used.

In one aspect, the present embodiment integrates two or more gate drivers each including a pixel region in which two or more pixels are disposed on a plastic substrate, and at least one transistor disposed on one surface of the plastic substrate and supplying a gate signal to the pixels. Provided is a display device including circuits and a wiring portion disposed adjacent to a transistor included in gate driver integrated circuits and to which a voltage having a polarity opposite to a polarity doped in an active layer of the transistor is applied.

In another aspect, the present embodiment provides at least one transistor included in a gate driver integrated circuit disposed on a plastic substrate and a wiring disposed adjacent to the transistor and applied with a voltage having a polarity opposite to that of a doped active layer of the transistor. A gate driver comprising a portion is provided.

According to the present exemplary embodiments, a decrease in mobility of a transistor included in a gate driver is improved during driving in a display device using a plastic substrate, so that a horizontal band defect does not occur.

1 is a diagram illustrating a schematic configuration of a display device according to the present exemplary embodiment.
2A and 2B are plan views of a display device according to an exemplary embodiment.
FIG. 3 is an enlarged view of a side A of the display device shown in FIG. 2A .
4 is a cross-sectional view taken along line B-B' of FIG. 3 .
FIG. 5 is a diagram illustrating characteristics of a transistor included in a gate driver integrated circuit as a comparative example when a specific type and a voltage having the same polarity as that of the specific type are applied to the wiring unit.
6 is a comparative example of a drain junction region under stress in which NBTS and HJS are alternately applied as a result of simulation when a transistor included in the gate driver integrated circuit is of a specific type and a voltage having the same polarity as the specific type is applied to the wiring unit; It is a diagram showing the carrier concentration.
7 is a comparative example, when a transistor included in a gate driver integrated circuit is of a specific type and a voltage having the same polarity as that of the specific type is applied to the wiring portion. is a diagram showing
8 is a diagram comparing the strength of an electric field in the active region and the drain region of the comparative example and the present embodiment.
9 and 10 show a case in which a transistor included in the gate driver integrated circuit is of a specific type and a voltage having the same polarity as a specific type is applied to the wiring section as a comparative example, and a transistor included in the gate driver integrated circuit is a specific type as an embodiment. and are diagrams showing the distribution of electric charges in plastic when a voltage opposite to a specific type and polarity is applied to the wiring part.
11 shows a case in which a transistor included in the gate driver integrated circuit is of a specific type and a voltage having the same polarity as that of a specific type is applied to the wiring part as a comparative example, and the transistor included in the gate driver integrated circuit is a specific type and the wiring part It is a diagram comparing the driving currents of transistors when voltages of a specific type and opposite polarities are applied to the .
12 is a plan view of the smart watch when the display device is applied to the smart watch.
13 is an enlarged view of a surface C of the display device of FIG. 12 .

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the nature, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It will be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

1 is a diagram illustrating a schematic configuration of a display device according to the present exemplary embodiment.

Referring to FIG. 1 , in the display device 100 according to the present exemplary embodiments, a plurality of gate lines GL and a plurality of data lines DL are disposed, and the gate lines GL and the data lines DL cross each other. A display panel 110 including a plurality of pixels disposed in a region to be used, a gate driver 120 driving a plurality of gate lines GL, and a data driver supplying data voltages to the plurality of data lines DL 130 and a controller 140 that controls driving of the gate driver 120 and the data driver 130 .

The display panel 110 is a liquid crystal display panel, a field emission display panel, an organic light emitting diode display panel, or an electrophoretic display panel. Panel) can be implemented. In addition, the display panel 110 may be implemented as a flexible display panel implemented with a flexible plastic substrate.

The gate driver 120 sequentially drives the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL.

The data driver 130 drives the plurality of data lines DL by supplying data voltages to the plurality of data lines DL.

The controller 140 supplies various control signals to the gate driver 120 and the data driver 130 to control the gate driver 120 and the data driver 130 . The controller 140 starts scanning according to the timing implemented in each frame, converts the input image data input from the outside to match the data signal format used by the data driver 130, and outputs the converted image data, , to control the data drive at an appropriate time according to the scan.

The gate driver 120 may include one or more gate driver integrated circuits.

Each gate driver integrated circuit is connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) method, or a GIP (GIP) method. Gate In Panel) type and may be directly disposed on the display panel 110 .

In addition, each gate driver integrated circuit may be integrated and disposed on the display panel 110 , and may be implemented in a Chip On Film (COF) method mounted on a film connected to the display panel 110 . .

However, hereinafter, for convenience of description, it is assumed that one or more gate driver integrated circuits included in the gate driver 120 are of the GIP type, but the present invention is not limited thereto.

In this case, as shown in FIGS. 2A and 2B , which are exemplary views of the gate driver 120 , a plurality of gate driver integrated circuits implemented in the GIP type are disposed on the display panel 110 and disposed on the display panel 110 . A plurality of gate lines GL may be driven.

The gate driver integrated circuit receives a gate start signal VST, a clock signal CLK, a reset signal RST, and the like, and generates a scan signal based on the received signals.

The gate driver integrated circuit sequentially outputs the generated scan signal to the plurality of gate lines GL to drive the gate lines GL.

2A and 2B are plan views of a display device according to an exemplary embodiment. FIG. 3 is an enlarged view of a side A of the display device shown in FIG. 2A .

2A, 2B, and 3 , in the display device 200 according to an exemplary embodiment, a pixel area 210 in which two or more pixels are disposed on a plastic substrate 205 is formed on one surface of the plastic substrate 205 . It includes a gate driver 220 disposed and a wiring unit 240 disposed adjacent to the gate driver 220 .

The plastic substrate 205 may be divided into a pixel region 210 in which two or more pixels are disposed and a non-pixel region 215 in which a gate driver 220 or a wiring unit 240 is disposed.

The plastic substrate 205 is made of various polymer materials such as plastic, for example, polyimide, polyethylene terephthalate, polyethylene naphthalate (PEN), polycarbonate, polyester sulfone (PES), etc. It may be a manufactured plastic substrate.

The gate driver 220 is described as being disposed on one side of the substrate 205 , for example, on the left side of FIGS. 2A and 2B , but on both sides of the substrate 205 , for example, on the left side of FIGS. It may be disposed on the right side. When the gate driver 220 is disposed on both surfaces, the structure of the gate driver 220 described below may be substantially the same on both surfaces.

The gate driver 220 includes two or more gate driver integrated circuits 222 each including at least one transistor for supplying a gate signal to the pixels.

The wiring unit 240 is disposed adjacent to the transistor included in the gate driver integrated circuits 222 , and a voltage having a polarity opposite to that of the doped polarity may be applied to the active layer of the transistor.

The gate driver integrated circuit 222 included in the gate driver 220 may include one pull-up transistor, one pull-down transistor, and the like. Although the transistor is illustrated as a P type, an N type may also be applied. The wiring unit 240 may include at least one wiring. In other words, the wiring unit 240 may be composed of only one wiring or two or more wirings.

The wiring unit 240 may be disposed in the non-pixel region 215 as shown in FIGS. 2A, 2B and 3 , and more specifically, between the gate driver integrated circuits 222 or the gate driver integrated circuit. It may be disposed on the outer surface of the 222 .

The wiring unit 240 may include at least one wiring on the left side of the gate driver integrated circuits 222 as shown in FIG. 2A , and as shown in FIG. 2B , the gate driver integrated circuits 222 . ) may be composed of at least one wiring on the right side.

The wiring unit 240 may be a wiring exclusively used to apply a voltage having a polarity opposite to the polarity doped in the active layer of the transistor to the gate driver integrated circuits 222 . On the other hand, the wiring unit 240, a clock signal, a base voltage, a common voltage, VGH, VGL, etc., may be used as a wiring for other purposes used to supply various voltages or power. In other words, a wiring to which a voltage having a polarity opposite to the polarity doped in the active layer of the transistor is applied to the gate driver integrated circuits 222 among other wirings may be disposed as the wiring unit 240 .

The above-described voltage or power supplied from a power controller disposed on the printed circuit board 250 , for example, a power management integrated circuit (PMIC) 270 is supplied to the wiring unit 240 through the power pad 260 . can be authorized

4 is a cross-sectional view taken along line B-B' of FIG. 3 .

Referring to FIG. 4 , the gate driver 220 is disposed adjacent to at least one transistor 224 and the transistor 224 included in the gate driver integrated circuit 222 disposed on the plastic substrate 205 and disposed adjacent to the transistor ( A wiring portion 240 to which a voltage having a polarity opposite to that of the doped active layer 224a is applied.

For example, the transistor 224 is a P-type thin film transistor in which the active layer 224a is P-doped, and a negative voltage is applied to the wiring part 240 , or the transistor 224 has the active layer 224a of N It is a doped N-type thin film transistor, and a (+) voltage may be applied to the wiring unit 240 .

The transistor 224 may be a top gate transistor in which the gate 224b is disposed above the active layer 224a on the plastic substrate 205 as shown in FIG. 4 , but is not limited thereto.

The active layer 224a may be formed of poly-silicon by depositing an amorphous silicon (a-Si) material and performing dehydrogenation and crystallization.

The active layer 224a may include an active region 224ab forming a channel, and a source region 224ac and a drain region 224aa doped with a high concentration of impurities on both sides of the active region 224ab. For example, as shown in FIG. 4 , the drain region 224aa is positioned on the left side of the active region 224ab, and the source region 224ac is positioned on the right side of the active region 224ab.

The drain region 224aa is electrically connected to the drain 224d and the drain contact hole 230a, and the source region 224ac is electrically connected to the source 224c and the source contact hole 230b.

The source 224c extends from the non-pixel region 215 and is electrically connected to the gate line GL4 disposed in the pixel region 210 . The gate line GL may be disposed on the same layer as the gate 224b of the transistor 224 or may be disposed on a different layer. When the gate line GL is disposed on the same layer as the gate 224b of the transistor 224 , the gate line GL and the gate 224b of the transistor 224 may be formed of the same material and by the same process.

The wiring unit 240 is disposed on the same layer as the source 224c and the drain 224d of the transistor 224 , and a voltage of a specific magnitude may be applied to the wiring unit 240 . The wiring unit 240 and the active layer 224a of the transistor 224 may be disposed at a distance that affects the charge accumulated in the plastic substrate 205 positioned below the active layer 224a, as will be described later.

For example, the wiring unit 240 is a single wiring and may be designed by adjusting the magnitude of an applied voltage or a distance away from the transistor 224 . For another example, the wiring unit 240 is two or more wirings, and one wiring has a polarity opposite to that of the doped active layer 224a of the transistor 224 included in the gate driver integrated circuit 222 . may be applied and a voltage having the same polarity as the polarity doped to the active layer 224a of the transistor 224 included in the gate driver integrated circuit 222 may be applied to the other wiring.

In the transistor 224 , the active layer 224a may be disposed on at least one buffer layer BUF disposed on the plastic substrate 205 .

A gate insulating film GI positioned on the active layer 224a, a gate 224b positioned on the gate insulating film GI and overlapping the active layer 224a, and a first intermediate insulating film GI positioned on the gate 224b ILD1), the second intermediate insulating layer ILD2 disposed on the first intermediate insulating layer ILD1, the source 224c and the drain 224d disposed on the second intermediate insulating layer ILD2 and connected to the active layer 224a, the source and a passivation layer (PAS) disposed on the 224c and the drain 224d.

The wiring unit 240 may be disposed on the same layer as the source 224c and the drain 224d of the transistor 224 . The wiring unit 240 may be positioned on the second intermediate insulating layer ILD2 . When the wiring part 240 is located on the same layer as the source 224c and the drain 224d of the transistor 224, the same material as the source 224c and the drain 224d of the transistor 224 is used by the same process. may be formed, but may be formed by a separate process using a material different from that of the source 224c and drain 224d of the transistor 224 .

For example, a manufacturing method of manufacturing a P-type transistor having a top gate structure is as follows.

As a process, after forming a sacrificial layer (not shown), a plastic substrate 205, a buffer layer (BUF), and an active layer 224a on a glass substrate (not shown), a photolithographic process and an etching process are performed to form the active layer ( 224a) is patterned, the active layer 224a is P-doped (P-type) or N-doped (N-type) according to the type, and a gate insulating layer GI and a gate 224b are formed.

Thereafter, the gate 224b is patterned by a photolithographic process and an etching process, first to third intermediate insulating layers ILD1 to ILD3 are formed, and the source 224c and the source 224c are formed thereon by a photolithographic process and an etching process. After the drain 224d is formed, the wiring part 240 may be formed by a photolithographic process and an etching process simultaneously or separately, and a passivation layer PAS may be formed thereon. When the process is completed, the glass substrate (not shown) and the sacrificial layer (not shown) are removed from the plastic substrate 205 .

Hereinafter, when the polarity doped in the active layer 224a of the transistor 224 included in the gate driver integrated circuit 222 is positive and the transistor 224 is P-type, the wiring unit 240 has a polarity opposite to the positive polarity. A case in which a voltage of, for example, a (-) voltage is applied is exemplified as an embodiment, and a voltage having the same polarity as a positive polarity, for example, a (+) voltage is applied to the wiring unit 240 as a comparative example. However, it can be seen that the same can be applied to a case in which the polarity doped to the active layer 224a of the transistor 224 is negative and a voltage having the opposite polarity is applied to the wiring unit 240 . In the embodiment, the wiring unit 240 to which the (-) voltage is applied is described as being VGL, but is not limited thereto.

FIG. 5 is a diagram illustrating characteristics of a transistor included in a gate driver integrated circuit as a comparative example when a specific type and a voltage having the same polarity as that of the specific type are applied to the wiring unit.

Referring to FIG. 5 , as a comparative example, when a transistor included in a gate driver integrated circuit is of a specific type and a voltage having the same polarity as that of the specific type is applied to the wiring portion, the display device 200 using the plastic substrate 205 is When there is a wiring part 240 (eg, wiring or fluting nodes) to which a (+) voltage is applied around the transistor 224 included in the gate driver integrated circuit 222 , when the actual display device 200 is driven, the plastic (+) moving charges in the plastic constituting the substrate 205 are accumulated, and as will be described later, NBTS (Negative Bias Temperature Stress) and HJS (High) of the transistor 224 in the gate driver integrated circuit 222 due to various causes. Junction Stress) may be accelerated.

In general, Negative Bias Temperature Stress (NBTS) means that the characteristics of a transistor are biased in a negative direction depending on temperature, and High Junction Stress (HJS) is a heterogeneous medium in a transistor, for example, a charge or a charge between two layers. It means the stress that occurs during the movement of the hall.

Accordingly, when the display device 200 is driven, a horizontal band defect may occur in the display device 200 . When checking the characteristics of the transistor 224 in which the horizontal band defect has occurred, it can be seen that mobility degradation occurs.

Specifically, the cause of the decrease in mobility of the transistor 224 having the plastic substrate 205 is the Hot Carrier Effect and the influence of the electric charge of the plastic substrate 205 .

6 is a comparative example of a drain junction region under stress in which NBTS and HJS are alternately applied as a result of simulation when a transistor included in the gate driver integrated circuit is of a specific type and a voltage having the same polarity as the specific type is applied to the wiring unit; It is a diagram showing the carrier concentration. 7 is a comparative example, when a transistor included in a gate driver integrated circuit is of a specific type and a voltage having the same polarity as that of the specific type is applied to the wiring portion. is a diagram showing

The deterioration of the mobility of the transistor 224 occurs when the HJS is alternately applied after the NBTS. As shown in FIG. 6 , in the NBTS section, the trapped hole carriers exist in the active layer 224a, and during the transition to HJS, the hole carriers do not completely escape and HJS. This is because the current due to the hole flows in the drain junction during the period.

That is, a hot carrier is generated while causing an impact ionization phenomenon by a strong electric field at the drain junction. Trap states are formed at the interface (GI/ACT interface) of the gate insulating layer GI/active layer 224a, where a lot of weak bonding exists by the generated high-energy hot carriers. will be created Mobility is reduced by the trap states created in the drain junction.

On the other hand, a change in the charge distribution existing in the plastic of the plastic substrate 205 affects the characteristics of the transistor 224 . This charge variation varies with time depending on the driving voltage condition of the transistor 224 itself and the design of the surrounding wiring. In particular, an electric field distribution is formed around the drain of the transistor 224, which is currently defective, in which (+) charges in the plastic are collected. (eg 7×10 ¹¹ A, 5×10 ¹¹ A, 7×10 ¹⁰ A) causes an increase in the lateral electric field at the drain junction, resulting in impact ionization and mobility degradation ) can be accelerated.

8 is a diagram comparing the strength of an electric field in an active region and a drain region of a comparative example and the present embodiment.

Referring to FIG. 8 , the electric field strength of the comparative example and the embodiment was measured by applying a voltage to the wiring unit 240 . In addition, in the comparative example, the intensity of the voltage applied to the wiring unit 240 is greater than in the embodiment. In addition, in the case of a wiring unit having two or more wirings, the comparative example and the embodiment may be compared with the sum of voltages applied to the wirings.

Referring to FIG. 8 , when the strength of the electric field in the drain region 224aa is less than or equal to a specific size, for example, 7×10 ³ [V/cm], a horizontal band defect may not occur. This may be adjusted by calculating the magnitude of the voltage in the wiring unit 240 or by arithmetic calculation, or may be designed by separating the distance from the gate driver integrated circuit 222 .

For example, the wiring unit 240 is a single wiring to which a (-) voltage, such as VGL, is applied, and the amount of the applied (-) voltage or the distance from the transistor 224 is adjusted in the drain region 224aa. The electric field strength can be designed to a specific size. For example, when a voltage applied to the wiring of the embodiment is applied to -7.5 [V] while maintaining a constant distance from the gate driver integrated circuit 222, the strength of the electric field in the drain region 224aa is as shown in FIG. Likewise, it can be measured as 7×10 ³ [V/cm] or less. As another example, as the distance between the wiring applied to -7.5 [V] and the gate driver integrated circuit 222 increases, the same effect as in the above-described example may occur.

For another example, in the two or more wiring units 240 , a (+) voltage is applied to one wiring and a (-) voltage is applied to the other wiring to lower the overall voltage, thereby reducing the strength of the electric field.

9 and 10 show a case in which a transistor included in the gate driver integrated circuit is of a specific type and a voltage having the same polarity as a specific type is applied to the wiring section as a comparative example, and a transistor included in the gate driver integrated circuit is a specific type as an embodiment. and are diagrams showing the distribution of electric charges in plastic when a voltage opposite to a specific type and polarity is applied to the wiring part.

Referring to FIG. 9 , as described above, as a comparative example, when a transistor included in a gate driver integrated circuit is of a specific type and a voltage having the same polarity as that of the specific type is applied to the wiring unit, plastic is placed around the drain of the transistor 224 . An electric field distribution in which (+) charges are collected is formed, and as confirmed through FIGS. 6 and 7, the mobility of the transistor 224 is reduced ( Mobility Degradation) may occur. Accordingly, as described above with reference to FIG. 5 , a horizontal band defect may occur in the display device 200 when the display device 200 is driven.

Referring to FIG. 10 , when a transistor included in the gate driver integrated circuit is of a specific type and a voltage opposite to the specific type and polarity is applied to the wiring portion, (+) charges in the plastic of the plastic substrate 205 are As it accumulates in the lower portion of the wiring unit 240 , the electric field at the drain line is reduced when HJS is applied, and the mobility deterioration phenomenon may be improved.

11 shows a case in which a transistor included in the gate driver integrated circuit is of a specific type and a voltage having the same polarity as that of a specific type is applied to the wiring part as a comparative example, and the transistor included in the gate driver integrated circuit is a specific type and the wiring part It is a diagram comparing the driving currents of transistors when voltages of a specific type and opposite polarities are applied to the .

Referring to FIG. 11 , as a comparative example, when the transistor included in the gate driver integrated circuit is of a specific type and a voltage having the same polarity as that of the specific type is applied to the wiring unit, the transistor 224 is NBTS (Negative Bias Temperature Stress) and HJS. (High Junction Stress) Alternately applied stresses are applied, so as time goes by, mobility degradation occurs, and the degradation of mobility can be accelerated by plastic charges. As a result, the driving current of the transistor 224 inevitably decreases gradually.

Accordingly, the transistor 224 has a reduced mobility, which causes serious product issues in the display device 200 such as a horizontal band defect.

On the other hand, when the transistor included in the gate driver integrated circuit is of a specific type and a voltage opposite to the specific type and polarity is applied to the wiring portion, (+) charges in the plastic of the plastic substrate 205 are accumulated. When the HJS is applied, the electric field at the drain line is reduced, and the deterioration of the mobility of the transistor 224 may be improved. As a result, the driving current of the transistor 224 may not decrease.

Although the case in which the plastic substrate 205 is rectangular has been exemplarily described in the above embodiment, as the plastic substrate 205 is used for a flexible display device, it can be applied to various display devices or electronic devices including the display device. have. Hereinafter, a case in which the plastic substrate is generally circular and the gate driver integrated circuits are disposed in a semicircular shape on one side or both sides of the plastic substrate will be exemplarily described.

12 is a plan view of a smart watch when the display device is applied to the smart watch. 13 is an enlarged view of a surface C of the display device of FIG. 12 ;

The display device 300 in which the pixel region 210 is formed on the plastic substrate 205 may be applied to a circular smart watch 400 as shown in FIG. 11 .

Referring to FIG. 13 , the gate driver integrated circuits 222 and the wiring 340 are disposed in a stepwise manner on one surface of the display device 310 , and as can be seen with reference to FIG. 12 , an overall semicircular shape may be achieved. .

According to the above-described embodiments, the display device 200 using the plastic substrate 205 has an effect that a horizontal band defect does not occur by improving the mobility deterioration of the transistor 224 during driving.

The above description is merely illustrative of the technical spirit of the present invention, and various modifications and variations will be possible without departing from the essential characteristics of the present invention by those skilled in the art to which the present invention pertains. In addition, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, so the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100, 200, 300, 310: display device 110: display panel
205: plastic substrate 210: pixel area
120, 220: gate driver 130: data driver
140: controller 230: contact hole
222, 322: gate driver integrated circuit 224: transistor
240, 340: wiring part
250: printed circuit board (Printed Circuit Board)
260: power pad 270: PMIC
400: smart watch

Claims (14)

a pixel region in which two or more pixels are disposed on a plastic substrate;
two or more gate driver integrated circuits disposed on one surface of the plastic substrate and each including at least one transistor for supplying a gate signal to the pixels; and
and a wiring part disposed adjacent to the transistor included in the gate driver integrated circuits and to which a voltage having a polarity opposite to a polarity doped to an active layer of the transistor is applied. According to claim 1,
The wiring unit includes at least one wiring,
a display device disposed between the pixel region and the gate driver integrated circuits or on an outer surface of the gate driver integrated circuit. According to claim 1,
The wiring unit is a clock signal, a base voltage, a common voltage, VGH or VGL wiring for a display device. According to claim 1,
The transistor is a P-type thin film transistor in which the active layer is P-doped, and a (-) voltage is applied to the wiring part, or the transistor is an N-type thin film transistor in which the active layer is N-doped, and the wiring part is (+) A voltage applied display device. 5. The method of claim 4,
wherein the transistor is a top gate transistor in which a gate is disposed above the active layer on the plastic substrate. 6. The method of claim 5,
The wiring part is disposed on the same layer as the source and drain of the transistor, and the wiring part and the active layer of the transistor are disposed at a distance such that electric charges are accumulated in the plastic substrate positioned below the active layer. According to claim 1,
The gate driver integrated circuits are arranged in a stepwise manner and form a semicircular shape as a whole. 5. The method of claim 4,
When the transistor is a P-type thin film transistor,
The wiring part is one wire to which a (-) voltage is applied, or when it includes two or more wires, a (+) voltage is applied to one wire and a (-) voltage is applied to the other wire,
The intensity of the electric field in the drain region of the P-type thin film transistor is 7×10 ³ [V/cm] or less. at least one transistor included in a gate driver integrated circuit disposed on a plastic substrate; and
and a wiring part disposed adjacent to the transistor and to which a voltage having a polarity opposite to a polarity doped to an active layer of the transistor is applied. 10. The method of claim 9,
The wiring unit is a gate driver that is a wiring for a clock signal, a base voltage, a common voltage, VGH or VGL. 10. The method of claim 9,
The transistor is a P-type thin film transistor in which the active layer is P-doped, and a (-) voltage is applied to the wiring part, or the transistor is an N-type thin film transistor in which the active layer is N-doped, and the wiring part is (+) Voltage applied gate driver. 12. The method of claim 11,
wherein the transistor is a top gate transistor in which a gate is disposed above the active layer on the plastic substrate. 13. The method of claim 12,
The wiring part is disposed on the same layer as the source and drain of the transistor, and the wiring part and the active layer of the transistor are disposed at a distance such that electric charges are accumulated in the plastic substrate positioned below the active layer. 12. The method of claim 11,
When the transistor is a P-type thin film transistor,
The wiring part is one wire to which a (-) voltage is applied, or when it includes two or more wires, a (+) voltage is applied to one wire and a (-) voltage is applied to the other wire,
The electric field intensity in the drain region of the P-type thin film transistor is 7×10 ³ [V/cm] or less for the gate driver.

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