KR100985581B1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

In order to provide a semiconductor device suitable for reducing cell size and a method of manufacturing the same by providing a circular capacitor usable as a memory cell under the gate electrode, the semiconductor device of the present invention for achieving the above object is a field region of a substrate A field oxide film formed on the; A gate insulating film and a gate electrode stacked on one region of the substrate; A circular capacitor formed in the substrate below the gate electrode; A buried channel region formed in said substrate on both sides of said circular capacitor; Source / drain regions formed in the substrate on both sides of the buried channel region on both sides of the gate electrode; And the first and second ion implantation regions formed in the substrate between the source / drain regions and the field oxide film.

Circular capacitors, diffuse

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}             

1 is a structural cross-sectional view showing a capacitor of a semiconductor device according to the present invention.

2A to 2D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.

* Explanation of symbols for the main parts of the drawings

20: semiconductor substrate 21: field oxide film

22 well area 23 circular capacitor

24: buried channel region 25: gate insulating film

26: gate electrodes 27a and 27b: source and drain regions

28a, 28b: first and second ion implantation regions

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device having a circular capacitor usable as a memory cell under a gate electrode, and a method of manufacturing the same.

In digital systems, it must have the ability to store and retrieve data, and semiconductor memory is created by arranging memory cells that can store one bit.

Unlike the shift register, such a memory can store and read information in its memory element arbitrarily. Such a memory is called a random access memory, or RAM.

There are two kinds of static circuit and dynamic circuit to make the RAM, but almost all of the dynamic circuit is used for the large capacity memory.

The RAM basic memory cell is manufactured by MOS technology and bipolar technology. RAMs using MOS transistors are most commonly used because MOS transistors can increase component density, allowing more bits to be stored on chips of a given size. Static MOSFETs are commonly used for small amounts of RAM, and DynamicMOS memory cells are most commonly used for large amounts of RAM. Dynamic random access memory is referred to as DRAM, and static random access memory is referred to as SRAM.

The DRAM is the most widely used memory cell, and is a memory cell composed of one capacitor and a transistor serving as a charge gate for charging the capacitor and discharging the charge therein.

The conventional DRAM memory cell has an advantage of low cost per cell and high integration of memory, but requires a refresh of a value stored in a time constant according to a capacitor value, and a basic cell is a capacitor component. Since the read / write time is slower than the transistor component, it has a disadvantage.

SRAM is a high-resistance load type and includes a memory cell consisting of four transistors and a CMOS memory cell consisting of six transistors.

As long as a voltage is applied to the SRAM cell, data is not erased without a separate refresh, and the read / ride time is fast due to data storage by a transistor component.

However, since there are four or six cell components, high integration is difficult and cost per cell is high.

The present invention has been proposed to solve the above problems of the prior art, and has a circular capacitor that can be used as a memory cell under the gate electrode to provide a semiconductor device suitable for reducing the cell size and its manufacturing method There is this.

According to an aspect of the present invention for achieving the above technical problem, a field oxide film formed in the field region of the substrate; A gate insulating film and a gate electrode stacked on one region of the substrate; A circular capacitor formed in the substrate below the gate electrode; A buried channel region formed in said substrate on both sides of said circular capacitor; Source / drain regions formed in the substrate on both sides of the gate electrode and on the buried channel region; There is provided a semiconductor device including first and second ion implantation regions formed in the substrate between the source / drain regions and the field oxide film.

In addition, according to another aspect of the invention, forming a field oxide film in the field region of the substrate; Forming a circular capacitor on one region of the substrate; Forming a gate insulating film and a gate electrode on one region of the substrate; Forming a source / drain region in one region of the substrate on both sides of the buried channel region on both sides of the gate electrode; And forming first and second ion implantation regions in the substrate between the source / drain regions and the field oxide film.

Hereinafter, a capacitor of a semiconductor device and a method of manufacturing the same according to a preferred embodiment of the present invention will be introduced so that those skilled in the art can more easily implement the present invention.

First, the semiconductor device according to the present invention will be described.

1 is a cross-sectional view showing a semiconductor device according to the present invention.

As shown in FIG. 1, the field oxide film 21 is formed in the field region of the semiconductor substrate 20 in which the field region and the active region are defined, and the well region 22 is formed in the active region. In this case, the well region 22 is implanted with first conductivity type ions (P type ions).

The gate insulating film 25 and the gate electrode 26 are stacked on one region of the well region 22 of the semiconductor substrate 20.                     

A circular capacitor 23 having a donut shape is formed in the well region 22 below the gate electrode 26, and the buried channel region 24 is formed in the semiconductor substrate 20 on both sides of the circular capacitor 23. Is formed.

Source / drain regions 27a and 27b are formed in the well region 22 on both sides of the buried channel region 24 on both sides of the gate electrode 26. In this case, the source / drain regions 27a and 27b are formed by implanting high concentration of the first conductivity type ions N +.

The donut-shaped circular capacitor 23 is formed of ions whose outer region is lighter than the inner region. That is, the concentration of the first ion that is heavier than the outer region is higher in the inner region, and the concentration of the second ion that is lighter than the first ion is higher in the outer region.

First and second ion implantation regions 28a and 28b are formed in the well region 22 between the source / drain regions 27a / 27b and the field oxide film 21. In this case, the first and second ion implantation regions 28a and 28b are formed by implanting high concentration of the second conductivity type ions P +.

Contact holes are formed on the gate electrode 26, the source / drain regions 27a and 27b, and the first and second ion implantation regions 28a and 28b, respectively, on the entire surface of the semiconductor substrate 20 including the gate electrode 26. A formed interlayer insulating film (not shown) is provided, and a plurality of electrode layers (not shown) for applying a voltage are disposed on the contact hole and the interlayer insulating film adjacent thereto.

To store data in the capacitor of the semiconductor element having the above configuration, V _S and V _G are grounded, and a voltage is applied such that V _D > 0 and V _Sub > 0.

This generates Id through the buried channel region 24 and lowers the barrier of the circular capacitor. Lowering V _G and V _Sub in this state increases the barrier. As a result, electrons in the buried channel region 24 are quickly moved to the circular capacitor 23. At this time, lowering V _D and lowering V _G and V _Sub further depletes the channel region outside the circular capacitor 23, and the electrons in the circular capacitor 23 are preserved in the capacitor.

In addition, to read data stored in the circular capacitor 23, V _Sub and V _G are grounded to form a channel, and then a low voltage is applied to V _D.

As described above, the present invention injects first and second ions (heavy ions, light ions) having a difference in diffusion rate into the semiconductor substrate. At this time, the injection dose of the first and second ions is the same, or the dose of the first ions is increased to secure the storage area of the capacitor. The reason for doing this is because the depth of the depletion width is doped more lightly.

For example, when As and Boron (B) are used for the first and second ions, respectively, the diffusion rates of the first and second ions before and after heat treatment at 1000 ° C. in the semiconductor substrate are approximately 10 times different.

For example, when the number of first and second ions is 20 and 20 in the center region before diffusion and 0 and 0 in the edge region, respectively, the first and second in the center region after diffusion. The number of ions is 19 and 10, and the number of first and second ions in the edge region is 1 and 10.                     

For reference, φn (x) = -Dn (dn (x) / dx), φp (x) = -Dp (dp (x) / dx), n (x) gradient and p by simple diffusion. (x) If the gradient is the same, the amount of diffusion is 10 times different.

The present invention configures a circular capacitor using the above concept. Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described.

2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

First, as shown in FIG. 2A, the field oxide film 21 is formed in the field region of the semiconductor substrate 20 in which the field region and the active region are defined.

Thereafter, the first conductivity type ions are implanted into the active region to form the well region 22. In this case, the first conductivity type is defined as a P type, and the well region 22 is a P well.

Subsequently, as shown in FIG. 2B, a group 5 element is implanted into the well region 22 of the semiconductor substrate 20 to form a channel region (not shown). At this time, the Group 5 element is injected at a depth of 100 nm to have a concentration of about 10 ¹² cm 2.

Although not shown in the drawing, the photoresist pattern is formed in a quadrangular shape so as to have a minimum size that can be patterned by an exposure and development process after applying the photoresist on the semiconductor substrate 20.

Next, using the photosensitive film pattern as a mask, first ions for forming a circular capacitor and second ions lighter than the first ions are implanted to have the same projected range (Rp). In this case, the doping concentration is 10 ¹⁹ cm 2, and the deflation width is about 0.03 μm.

Subsequently, when the heat treatment process is performed, the second ions, which are lighter than the first ions, diffuse faster than the first ions, and the injection region, which was the highest peak at Rp, diffuses in a circular shape.

In this way, a circular capacitor 23 is formed in the shape of an oval shape having a peak in the middle of the channel region of the semiconductor substrate 20.

In the region far away from Rp, the second ion concentration is high, and in the region close to Rp, the concentration of the first ion is high.

In the above description, the first and second ions have a diffusivity of about 10 times, and the first ions have a higher concentration and a sharper profile.

As with the principle of diode formation, depletion occurs in circular capacitors. As with diodes, depletion width changes with bias. The depletion width is then determined by the substrate bias outside the depletion region and the doping concentration present in the capacitor. Therefore, no electrode is needed.

Next, as shown in FIG. 2C, the buried channel region 24 is formed on both sides of the circular capacitor 23 in the well region 22 of the semiconductor substrate 20 so as to have a concentration of approximately 10 ¹⁷ / cm 3 (EPI structure). In this case, since the buried channel region 24 is already formed, this process can be omitted.

Subsequently, as shown in FIG. 2D, an oxide film and a semiconductor layer are deposited on the semiconductor substrate 20. Then, the oxide film and the semiconductor layer are sequentially etched using a gate forming mask to form an oxide film and a semiconductor layer on one region of the semiconductor substrate 20. The gate insulating film 25 and the gate electrode 26 are laminated.

Subsequently, a high concentration of second conductivity type ions (N +) is implanted into the well regions 22 on both sides of the gate electrode 26, and an annealing process is performed to form source / drain regions 27a / 27b.

In addition, a high concentration of the first conductivity type ions P + is implanted between the source / drain regions 27a / 27b and the field oxide film 21 and the annealing process is performed to perform the first and second ion implantation regions 28a and 28b. To form.

Although not shown in the drawing, the source / drain regions 27a and 27b may be formed by coating a photoresist film on the semiconductor substrate 20 including the gate electrode 26, and subjecting the photoresist pattern to an exposure and development process so as to expose one region. After the formation, the second conductive type ion (N +) is implanted using the photosensitive film pattern as a mask.

The first and second ion implantation regions 28a and 28b also form a photoresist pattern as in the method of forming the source / drain regions 27a / 27b, and then use the mask as a mask to form a high concentration of the first conductivity type ion (P +). Inject to form.

Thereafter, an interlayer insulating film (not shown) is deposited on the entire surface of the semiconductor substrate 20 including the gate electrode 26, and the gate electrode 26, the source / drain regions 27a / 27b, and the first and second ions are formed. Contact holes are formed on the injection regions 28a and 28b, respectively. Thereafter, a plurality of electrode layers for voltage application are formed on the contact hole and the interlayer insulating film adjacent thereto.

The capacitor of the semiconductor device as described above is simpler than the conventional DRAM or SRAM, and its size is not large.

For example, in comparison with the conventional SRAM cell size of about 3.6㎛ ² , the capacitor active in the capacitor of the semiconductor device of the present invention manufactured according to the current design rule is at least 0.35㎛ × 0.35㎛, the first Since the second ion implantation region is 0.25 μm ² , each size has a minimum size of 0.5 μm. Therefore, the size of all the active regions is also 0.5 µm x 0.5 µm. Here, at least 0.3 µm is required to define the gate electrode and the source / drain regions on the left and right, respectively, and the minimum size is 0.5 µm x 1.1 µm, which is 0.55 µm ² .

Therefore, the area can be reduced by six times than that of an SRAM cell.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, the first and second ions forming the circular capacitor are all dopants in which the junction can be formed to have group 5 element, group 3 element, or diode characteristics having a difference in diffusivity in the semiconductor substrate. Is applicable.

 The present invention described above can form a capacitor inside the semiconductor substrate under the gate electrode, thereby reducing the cell size.

Claims (9)

A field oxide film formed in the field region of the substrate; A gate insulating film and a gate electrode stacked on one region of the substrate; A circular capacitor formed in the substrate below the gate electrode; A buried channel region formed in said substrate on both sides of said circular capacitor; Source / drain regions formed in the substrate on both sides of the gate electrode and on the buried channel region; And First and second ion implantation regions formed in the substrate between the source / drain regions and the field oxide layer; And a concentration of the first ions that are heavier than the ions of the outer region in the inner region of the circular capacitor, and a concentration of the second ions that are lighter than the first ions in the outer region. The method of claim 1, The circular capacitor has a donut shape. delete The method of claim 1, An interlayer insulating film having contact holes on the gate electrode, the source / drain regions, and the first and second ion implantation regions, respectively; And a plurality of electrode layers for applying voltage on the contact hole and the interlayer insulating layer adjacent thereto. Forming a field oxide film in the field region of the substrate; Forming a circular capacitor on one region of the substrate; Forming a gate insulating film and a gate electrode on one region of the substrate; Forming a source / drain region in one region of the substrate on both sides of the buried channel region on both sides of the gate electrode; And Forming first and second ion implantation regions in the substrate between the source / drain regions and the field oxide layer Method of manufacturing a semiconductor device comprising a. The method of claim 5, After performing the step of forming the circular capacitor, And forming a buried channel region in the substrate on both sides of the circular capacitor. The method of claim 6, The method of forming the circular capacitor may include applying a photosensitive film on the substrate; Patterning the photoresist film by an exposure and development process to form a photoresist pattern; Implanting first ions and second ions lighter than the first ions to have the same projected range (Rp) using the photoresist pattern as a mask; Method of manufacturing a semiconductor device comprising the step of performing a heat treatment process. The method of claim 6, Depositing an interlayer insulating film over the substrate including the gate electrode; Forming contact holes on the gate electrode, the source / drain region, and the first and second ion implantation regions, respectively; And forming voltage applying electrode layers on the contact hole and the interlayer insulating layer adjacent thereto. The method of claim 6, The buried channel region is formed of a first conductivity type ion, and the source / drain region is formed of a second conductivity type ion.

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