KR100981079B1 - Substrate for ??? package with ??? provention function and ??? package using the substrate - Google Patents

Substrate for ??? package with ??? provention function and ??? package using the substrate Download PDF

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Publication number
KR100981079B1
KR100981079B1 KR1020080046690A KR20080046690A KR100981079B1 KR 100981079 B1 KR100981079 B1 KR 100981079B1 KR 1020080046690 A KR1020080046690 A KR 1020080046690A KR 20080046690 A KR20080046690 A KR 20080046690A KR 100981079 B1 KR100981079 B1 KR 100981079B1
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South Korea
Prior art keywords
substrate
led package
electrode
varistor
zno
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KR1020080046690A
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Korean (ko)
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KR20090120741A (en
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최원길
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(주) 아모엘이디
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Priority to KR1020080046690A priority Critical patent/KR100981079B1/en
Priority to PCT/KR2008/007332 priority patent/WO2009075530A2/en
Publication of KR20090120741A publication Critical patent/KR20090120741A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

The present invention provides an LED package substrate having an antistatic function and an LED package using the same, which can prevent electrode peeling and electrical short-circuit of the electrode and minimize light loss. The LED package substrate having an antistatic function includes a ZnO series varistor substrate having internal and external electrodes formed thereon, and the external electrode is formed on a part of the top and bottom surfaces of the varistor substrate through an insulating layer, and the external electrode is insulated. The white reflective layer is formed on the remaining region except for a portion of the varistor substrate, which is electrically connected to the internal electrode and includes a region where the light emitting device is positioned on the upper surface of the varistor substrate. By forming an insulating layer on the upper and lower surfaces of the ZnO series varistor substrate and then forming an upper electrode and a lower electrode, the insulating layer prevents the erosion of the varistor surface due to the plating solution and thereby the adhesion between the upper electrode and the varistor substrate and the lower surface. Improve the adhesion between the electrode and the varistor substrate. Light in the visible region by selecting white TiO 2 , ZnO, Lithopone, ZnS, BaSO 4 , SiO 2 , PTFE (polytetrafluoroethylene), etc. In addition to almost no absorption, almost all the light from the light emitting device is reflected, thereby improving the light efficiency compared to the conventional LED package.

Description

Substrate for LED package with ESD provention function and LED package using the substrate}

The present invention relates to an LED package substrate having an antistatic function and an LED package using the same, and more particularly, to an LED package substrate having an antistatic function using a ZnO series varistor and an LED package using the same. .

Currently, light emitting diodes have advantages such as low power, high efficiency, high brightness, and long life, and thus are widely used in packaged form for electronic components. On the other hand, the light emitting diode has a disadvantage of being susceptible to static electricity or reverse voltage.

Therefore, because the LED chip employed in the LED package is weak against static electricity and reverse voltage, a Zener diode or a varistor is connected in parallel with the LED chip and used as a countermeasure against static electricity and reverse voltage.

However, a method of integrally packaging a Zener diode or varistor in parallel with an LED chip has problems such as space limitation due to an additional process, an increase in the number of processes and an increase in size due to additional mounting, and an increase in manufacturing cost.

In addition, side effects such as scattering and refraction of light generated in the LED chip by the Zener diode or varistor placed on the same plane as the LED chip have been limited in the effective control of the direction angle or light. Thus, a method of increasing the static resistance of the LED chip itself for efficient use of light, a method of embedding a zener diode or varistor in a separate cavity, and the like are used.

The latter method is advantageous in light efficiency or directivity over the former method, but has a disadvantage in that the manufacturing process is complicated and expensive. Of course, a structure in which a small stacked varistor is embedded in a space for wire bonding in the zener diode is possible, but this also has a disadvantage in that the manufacturing process is complicated and expensive.

In addition, the varistor has an electrical characteristic of converting from a non-conductor to a conductor when a certain voltage is introduced. Due to this electrical characteristic, when a high voltage (EDS) of several KV or more is introduced into the LED chip, the varistor is converted into a conductor to protect the LED chip by flowing a high voltage to ground.

Typically, the internal electrodes 1, 2 and the external electrodes 3, 4; 5, 6 are used for varistors as shown in FIG. The internal electrodes 1, 2 are printed between the green sheets and co-sintered. The outer electrodes 3, 4; 5, 6 are connected with the inner electrodes 1, 2 in the finished product which has been sintered. The external electrodes 3 and 4 are top electrodes, and the external electrodes 5 and 6 are bottom electrodes. In order to form the external electrodes 3, 4; 5, 6, an Ag pattern is printed on the top and bottom surfaces of the sintered product using Ag paste, and Ni plating and Ag plating are performed thereon, respectively. At this time, the characteristics of the varistor are evaluated by the varistor voltage and capacitance. The varistor voltage is determined by the linear distance between the internal electrode 1 and the internal electrode 2, and the capacitance is determined by the area and distance where the internal electrode 1 and the internal electrode 2 overlap and the material of the raw material. .

However, since varistors have semiconductor properties, the substrate material itself becomes conductive when plating proceeds. As a result, the electrical resistance is lowered at the time of electroplating, thereby spreading the plating layer formed on the external electrodes 3 and 4. As a result, instead of forming the external electrodes 3, 4; 5, 6 spaced apart from each other as shown in FIG. 1, the external electrodes 3, 4 are electrically shorted to each other, and the external electrodes 5, 6 are mutually separated. There is a problem of an electrical short.

In addition, during the plating process, the surface of the varistor is eroded by the plating solution, thereby lowering the adhesion between the Ag layer, which is the lowest layer of the electrode layers, and the surface of the varistor. Thus, a phenomenon in which the electrode is peeled off during wire bonding occurs.

In addition, ZnO is white, but due to the additive, ZnO series varistors become black when sintered. Since black absorbs light, the LED package using a conventional varistor substrate causes loss of light emitted from the LED by black. Of course, if the upper electrodes 3 and 4 are made of Ag having high reflectance, the loss due to black may be reduced to some extent, but when viewed from the top, the black part remains, causing loss of light.

The present invention has been proposed to solve the above-mentioned conventional problems, the LED package substrate and the LED package using the anti-static function to prevent the electrode peeling and electrical short circuit of the electrode and to minimize the loss of light The purpose is to provide.

In order to achieve the above object, the LED package substrate with an antistatic function according to a preferred embodiment of the present invention includes a ZnO series varistor substrate having an internal electrode and an external electrode,

The external electrode is formed on a portion of the top and bottom surfaces of the varistor substrate via the insulating layer, the external electrode is electrically connected to the internal electrode through the insulating layer, and a portion including a region where the light emitting element is located on the top of the varistor substrate A white reflective layer is formed in the remaining regions except for the region.

The insulating layer contains at least one material of BaO, CaO, K 2 O, ZnO.

The insulating layer includes 3-9 wt% BaO, 9-15 wt% CaO, 3-9 wt% K 2 O and 3-10 wt% ZnO as main materials.

As the insulating layer, a component material obtained by mixing 5-9 wt% Al 2 O 3 , 50-65 wt% SiO 2 , 1-5 wt% TiO 2, and 2-6 wt% B 2 O 3 together with the main material is used. .

The reflecting layer contains a white silicone epoxy resin.

The reflective layer comprises at least one of TiO 2 , ZnO, lithopone, ZnS, BaSO 4 , SiO 2 , PTFE (polytetrafluoroethylene).

The reflective layer includes at least one of TiO 2 , ZnO, lithopone, ZnS, BaSO 4 , SiO 2 , and PTFE (polytetrafluoroethylene) as a main material, and the main material is added at 5 to 60 wt%.

As the reflective layer, a component material containing 5 to 30 wt% of silicone resin and 20 to 65 wt% of epoxy resin is used together with the main material.

The reflective layer is formed flat or rounded inwardly.

On the other hand, the LED package according to an embodiment of the present invention, the substrate described above; And a light emitting device mounted on the upper surface of the substrate.

The light emitting element is an LED in the form of one or more chips.

According to the present invention having such a configuration, the upper and lower electrodes are formed after the insulating layers are formed on the upper and lower surfaces of the varistor substrate of the ZnO series, thereby preventing the erosion of the varistor surface due to the plating liquid and thereby the upper surface. The adhesion between the electrode and the varistor substrate and the adhesion between the lower surface electrode and the varistor substrate are improved.

In addition, the insulating layer prevents an electrical short between the upper and lower electrodes during the formation of the electrode by plating and prevents the electrode from peeling off during the wire bonding.

On the other hand, by selecting white TiO 2 , ZnO, lithopone, ZnS, BaSO 4 , SiO 2 , PTFE (polytetrafluoroethylene) and the like having low absorption and good reflectance, the reflective layer is formed in the visible light region. In addition to almost no light absorption, and reflects almost all the light from the light emitting device improves the light efficiency compared to the conventional LED package.

Hereinafter, an LED package having an antistatic function and an LED package using the same according to the present invention will be described with reference to the accompanying drawings. In the following description, the LED package may be applied to all SMD type packages such as ceramic packages, plastic packages, lead frame type packages, and plastic + lead frame type packages.

2 to 12 are views for explaining the structure and manufacturing process of the LED package substrate and the LED package using the same with an antistatic function according to an embodiment of the present invention.

For example, ZnO powder is added with additives such as Bi 2 O 3 , Sb 2 O 3 , and any one of AlN, BN, and BeO to match a desired composition. A ZnO powder having a suitable composition is ball milled for 24 hours using water or alcohol as a solvent to prepare a raw material powder. In order to prepare a molded sheet, PVB-based binder (binder) is measured as an additive to the prepared raw powder and then dissolved in toluene / alcohol (toluene / alcohol) -based solvent. The slurry is then milled and mixed for about 24 hours in a small ball mill. This slurry is produced by a method such as a doctor blade, a plurality of green sheets (sheets such as 10, 12, 14, 16, 18, 20 of Figure 2) of the desired size. Among the green sheets manufactured, some green sheets 14 and 16 are printed with patterns for internal electrodes 13 and 15 (for example, AgPd) for each unit element region. In order to sinter the material, a temperature of approximately 1000 to 1050 degrees is required, in which AgPd is used as the internal electrode. Since Ag has a melting point of about 960 degrees and is lower than the sintering temperature, AgPd is mainly used as an internal electrode.

In each of the green sheets 10, 12, 14, 16, 18, and 20, two through holes 11 spaced apart from each other by unit device regions are formed in the vertical direction. The inside of the through hole 11 is filled with a conductive material later. After sintering the green sheets 10, 12, 14, 16, 18, and 20, the final cutting process is separated into a plurality of LED packages. The separated LED packages are called unit devices. The area occupied by each unit element is called a unit element region. Therefore, it can be understood that a plurality of unit element regions exist in the green sheets 10, 12, 14, 16, 18, and 20.

Next, as shown in FIG. 2, the green sheet 12 is laminated on the upper surface of the green sheet 10 of the lowest layer. One green sheet having a thickness in which the thicknesses of the green sheet 10 and the green sheet 12 are combined may be used. The green sheet 14 is laminated on the upper surface of the green sheet 12, and the green sheet 16 is laminated thereon. The green sheet 18 is laminated on the upper surface of the green sheet 16 and the green sheet 20 is laminated thereon. Thus, what laminated | stacked the several green sheet 10, 12, 14, 16, 18, 20 is called laminated body.

Thereafter, the laminate is pressed. Then, cutting grooves 22 are formed in the upper and lower surfaces of the laminate as shown in FIG. The upper cutting grooves 22 are formed at a predetermined depth along the boundary line between the unit device regions in the downward direction from the upper surface of the laminate. Cutting grooves 22 on the lower surface are formed at predetermined values along the boundary line between the unit element regions in the upward direction from the lower surface of the laminate. In the embodiment of the present invention does not illustrate the depth of the cutting groove 22 of the upper surface and the height of the cutting groove 22 of the lower surface is not illustrated one by one because the size of the LED package of the single piece to be completed can be several types. For example, the upper cutting groove 22 is formed in the shape of a V (V), the lower cutting groove 22 is formed in the reverse V shape. Here, the cutting grooves of the upper surface and the cutting grooves of the lower surface are preferably formed to a depth such that they are not in contact with each other. As described above, the depth to be close to each other means a depth that can be easily separated into each unit element by the cutting groove 22 by applying mechanical or artificial force in the final separation process. Using the equipment that can groove the laminate of varistor material it is possible to form the cutting groove (22).

After the cutting grooves 22 are formed, the laminate of FIG. 3 is sintered. The sintering temperature at this time is about 1000 degree-1050 degree | times. Hereinafter, the sintered laminate is referred to as the body, and the reference numeral of the body is 24.

Then, the insulating layer 26 is formed on the upper and lower surfaces of the body 24 as shown in FIG. The insulating layer 26 is formed for each unit element region, and has a uniform thickness by a printing method using a mask or the like. In the insulating layer 26, two through holes 26a spaced apart from each other by unit device regions are formed in the vertical direction. The through hole 26a is formed at the same position in the same manner as the through hole 11. The insulating layer 26 is made of a glass material having excellent adhesion to the lower ZnO varistor during firing, excellent adhesion to the upper external electrode (eg, Ag), and strong resistance to the plating solution. Conventionally, when the top electrode and the bottom electrode are directly bonded to the ZnO varistor, when the simultaneous firing method is used, the surface of the varistor is eroded by the plating solution during the plating process, and thus the adhesion between the top electrode and the bottom electrode and the ZnO varistor is very weak. In the embodiment of the present invention, the insulating layer 26 is used to prevent the erosion of the varistor surface due to the plating liquid, thereby improving the adhesion between the upper electrode and the varistor substrate and the adhesion between the lower electrode and the varistor substrate. In addition, the insulating layer 26 prevents an electrical short between the upper and lower electrodes during the formation of the electrode by plating and prevents the electrode from peeling off during the wire bonding. Looking at the composition and content of the insulating layer 26 is shown in Table 1 below.

(Table 1)


Furtherance

Content (wt%)
Al 2 O 3

7
SiO 2

57
TiO 2

3
B 2 O 3

4
BaO

6
CaO

12
K 2 O

6
ZnO

5

The content for each composition indicated in Table 1 above is a preferable numerical example obtained by the present applicant by experiment. Of course, the content of each composition of Table 1 does not have a large amount even if a little addition or subtraction. Accordingly, in Table 1, the insulating layer 26 uses about 3 to 9 wt% BaO, about 9 to 15 wt% CaO, about 3 to 9 wt% K 2 O and about 3 to 10 wt% ZnO as main materials. Just do it. Insulating layer 26 is composed of about 5-9 wt% of Al 2 O 3 , about 50-65 wt% of SiO 2 , about 1-5 wt% of TiO 2, and about 2-6 wt% of B 2 O 3 . do.

In Table 1, since the material of the varistor substrate is ZnO, the content of ZnO is about 3 to 10 wt% in order to improve adhesion to the varistor substrate. If the content of ZnO is less than 3wt%, the adhesion to the varistor substrate is weak, and if the content of ZnO is more than 10wt%, the insulation is destroyed. K 2 O, CaO and BaO are to obtain a desired firing temperature, it is difficult to meet the desired firing temperature (approximately 810 degrees) when the respective content range is out of the above-described content range.

In Table 1, the materials of 5-9 wt% Al 2 O 3 , approximately 50-65 wt% SiO 2 , approximately 1-5 wt% TiO 2 and approximately 2-6 wt% B 2 O 3 were formed to form a glass phase. will be. In the composition used as the submaterial, SiO 2 is used as the main material for forming the glass phase. When the content of SiO 2 exceeds 50 ~ 65wt%, the firing temperature and strength drops. If the content of SiO 2 is less than 50-65wt%, the firing temperature increases.

Thereafter, as shown in FIG. 5, the conductive material 28 (eg, Ag) is filled in the through holes 26a and 11, and then the coupling between the body 24, the insulating layer 26, and the conductive material 28 is removed. In order to fire at a temperature of about 810 degrees. Here, although the conductive material 28 has been described as being filled only once, it may be somewhat cumbersome, but considering the filling accuracy of the conductive material 28, the inside of the through hole 11 is filled before sintering the laminate. Then, after the sintering process, the through-hole 26a of the insulating layer 26 may be filled and then fired.

As such, when the insulating layer 26 is formed on the upper and lower surfaces of the body 24 and then the upper and lower electrodes are formed, the varistor surface is eroded by the plating liquid by the insulating layer 26. This eliminates the short phenomenon between the top electrodes and the short phenomenon between the bottom electrodes during plating.

6 and 8, the process of forming the top electrode and the bottom electrode is performed. First, as shown in FIG. 6, Ag paste is printed on the top surface of the insulating layer 26 formed on the top surface of the body 24 and the bottom surface of the insulating layer 26 formed on the bottom surface of the body 24. The Ag paste may be printed on the top and bottom surfaces at the same time, or Ag paste printing may be performed after the body 24 is overturned after Ag paste printing on either side. Here, the Ag paste is printed on only a part of the surface, not on all portions of one surface of the insulating layer 26. That is, Ag paste printing is performed only at the positions where the top electrode and the bottom electrode are to be formed. In other words, the Ag paste is printed such that each unit element region is in contact with the conductive material 28 of the through hole 26a of the insulating layer 26. The reason for using Ag is that it can be wire bonded, serves as a reflector that reflects light, and has a good reaction with solder. In Fig. 6, reference numerals 30a and 30b denote Ag layers on which Ag print patterns are formed, and Ag layers 30a and 30b are collectively referred to as first metal layers 30.

Then, it is fired at a temperature of approximately 810 degrees for bonding the first metal layer 30 and the insulating layer 26.

As shown in FIG. 7, Ni plating is performed on the upper surface of the first metal layer 30 to form the second metal layer 32, and Ag plating is performed on the upper surface of the second metal layer 32 as shown in FIG. 8. The metal layer 34 is formed. Ni prevents the third metal layer 34 from being peeled off by the reaction with the solder during the reflow process. In FIG. 7, reference numerals 32a and 32b denote Ni layers on which Ni print patterns are formed, and Ni layers 32a and 32b are collectively referred to as second metal layers 32. In FIG. 8, reference numerals 34a and 34b denote Ag layers on which Ag print patterns are formed, and Ag layers 34a and 34b are collectively referred to as a third metal layer 34. Here, although Ag is used for the third metal layer 34, Au may be used. 6 to 8 illustrate that the metal layers 30, 32, and 34 are formed only on the insulating layer 26 on the upper surface of the body 24, but in practice, the insulating layer 26 on the bottom surface of the body 24 is formed. ), Metal layers 30, 32, and 34 are formed.

Thereafter, as shown in FIG. 9, the reflective layer 36 is flatly printed to cover the insulating layer 26 and the third metal layer 34 on the upper surface of the body 24. 10 is a cross-sectional view taken along the line A-A of FIG. The reflective layer 36 is not formed in the portion where the light emitting device is to be mounted and the portion where the wire is to be bonded. That is, as shown in FIG. 10, the reflective layer 36 covers the region where the third metal layer 34 is not located on the upper surface of the insulating layer 26 on the upper surface of the body 24 and the upper surface of the third metal layer 34. To cover some. For example, a white silicone epoxy resin (see Table 2 below) having a reflectance of 90% or more is used as the material of the reflective layer 36. The white silicone epoxy resin used as the material of the reflective layer 36 has thermosetting properties.

(Table 2)


material

content
Titanium dioxide,
Zinc Oxide,
Lithopone (BaSO 2 + ZnS)
ZnS,
BaSO 4 ,
SiO 2 ,
PTFE (polytetrafluoroethylene)




5 to 60 wt%
Silicone Resin

5 to 30% by weight
Additives such as solvents, etc.,
Epoxy resin etc

20 to 65 wt%

In Table 2, TiO 2 , ZnO, lithopone, ZnS, BaSO 4 , PTFE (polytetrafluoroethylene) and the like were used to implement white color. Silicone resins and epoxy resins were used for the viscosity and tack. In Table 2, TiO 2 , ZnO, lithopone, ZnS, BaSO 4 , SiO 2 , PTFE (polytetrafluoroethylene), and the like are the main materials for producing white color, and silicone resins, epoxy resins, and the like are materials. . In Table 2, the use of TiO 2 , ZnO, lithopone, ZnS, BaSO 4 , SiO 2 , PTFE (polytetrafluoroethylene) at less than 5% by weight makes white implementation difficult. When TiO 2 , ZnO, Lithopone (Lithopone), ZnS, BaSO 4 , SiO 2 , and PTFE (polytetrafluoroethylene) are used in excess of 60% by weight, the amount of addition of silicone resin and epoxy resin is reduced and the desired viscosity and Hard to get adhesiveness If the silicone resin is used at less than 5% by weight, the viscosity becomes too low. When the silicone resin is used in excess of 30% by weight, the viscosity becomes too high. When the epoxy resin is used in less than 20% by weight, the adhesive strength is weakened. When the epoxy resin is used in excess of 65% by weight, the content of TiO 2 , ZnO, lithopone, ZnS, BaSO 4 , SiO 2 , PTFE (polytetrafluoroethylene) or silicone resin is insufficient, resulting in white color. This makes it difficult to achieve the desired viscosity. The varistor is black after sintering. ZnO is white but appears black because of the additives. In general, since black absorbs light, light emitted from the light emitting device is lost due to black color. Thus, the white reflective layer 36 is formed to prevent the loss of light. In the visible region by selecting the white layer of TiO 2 , ZnO, Lithopone, ZnS, BaSO 4 , SiO 2 , PTFE (polytetrafluoroethylene), etc. Light absorption of the light emitting device is almost eliminated, and light is almost reflected from the light emitting device, thereby improving light efficiency. The above description of the reflective layer 36 applies as it is to the other embodiments below. In FIG. 10, reference numeral 38 denotes the Ag layer 30a, the Ni layer 32a, and the Ag layer 34a, and becomes one of the top electrodes (for example, an anode). Reference numeral 40 denotes the Ag layer 30b, the Ni layer 32b, and the Ag layer 34b, and becomes another one of the upper electrodes (for example, a cathode). Reference numeral 39 denotes the Ag layer 30a, the Ni layer 32a, and the Ag layer 34a, and becomes one of the bottom electrodes (for example, an anode). Reference numeral 41 denotes the Ag layer 30b, the Ni layer 32b, and the Ag layer 34b, and becomes another one of the lower electrodes (for example, a cathode). In FIG. 10, reference numeral 36a denotes a hole for wire bonding, 36b denotes a hole on which a light emitting element is to be mounted, and 36c denotes a hole for wire bonding.

Subsequently, as shown in FIG. 11, the light emitting devices 42 are mounted for each unit device region, and then wires 44 are bonded. In the above-described embodiment, two upper electrodes are formed on the upper surface of the elementary body 24 for each unit element region, which uses two wires 44 to connect the light emitting elements 42 to the upper electrodes 38 and 40, respectively. This is because the wire bonding method to connect is shown. For example, as long as the light emitting element 42 is a light emitting element capable of eutectic bonding, the number of wires may be one. On the other hand, if the light emitting element 42 is a light emitting element capable of flip bonding, the wire 44 is not necessary and the number of electrodes (more specifically, pads by connection with a flip chip) may be one. The light emitting element 42 is a chip-shaped LED and has a wavelength band of approximately 200 to 900 nm. The light emitting element 42 may be employed for each power up to a single chip or a multi chip according to a required specification. The light emitting element 42 may use a chip that emits light in an upward direction or a chip that emits light in an upward direction and a lateral direction. The partial region including the region where the light emitting element is located in the external electrode on the upper surface of the varistor substrate according to the claims of the present invention, in the case of the wire bonding method and the eutectic point bonding method, The bonding region refers to a region in which a flip chip is positioned in the flip bonding method.

Finally, as shown in FIG. 12, the substrate 46 having the cavity filled with the phosphor (not shown) is separately made and attached, and then the body 24 is separated by the cutting groove 22 by mechanical or artificial force. Separate into unit elements. Each separate unit device is an LED package. In FIG. 12, the substrate 46 is attached to the body 24 and then separated into a plurality of unit elements. However, the body 24 is first divided into several unit elements, and then a substrate (for each unit element) is formed. 46) may be attached. The LED package substrate may be regarded as a part (varistor substrate) except for a light emitting device and a wire.

In FIG. 12, when the light emitted from the light emitting element 42 is output to the outside, the efficiency thereof is reflected in the reflective layer 36 formed on the base substrate (the lower substrate (that is, the varistor substrate) on which the substrate 46 is stacked in FIG. 12). It also depends on the substrate 46 with the cavity made separately. The substrate 46 may be made of a variety of materials such as plastic, ceramic, metal, and the like. Materials used as the material of the substrate 46 have a property that the reflectance of visible light is different from each other. Ag plating may be used as a method for increasing the reflectance of the substrate 46. However, this method is limited in application depending on the material of the substrate 46. Therefore, the substrate 46 and the lower base substrate may be pasted after a process of coating and curing the material of the reflective layer 36 in the inside of the cavity in advance.

FIG. 13 is a view illustrating an LED package substrate having an antistatic function and an LED package using the same according to another embodiment of the present invention. Another embodiment is characterized in that the shape of the reflective layer 36 is different. That is, in the above-described embodiment, the reflective layer 36 is printed flat, but in another embodiment, the reflective layer 36 is rounded by dispensing. In the case of FIG. 13, after mounting the light emitting device 42, the substrate 46 is bonded to the base substrate 50, and then the reflective layer 36 is formed. The base substrate 50 is a substrate provided for each unit element, and corresponds to a varistor substrate existing under the substrate 46 when the body 24 is separated for each unit element in FIG. 12.

In FIG. 13, the process of manufacturing the varistor substrate 50, the top electrodes 38, 40, and the bottom electrodes 39, 41 is the same as in the above-described embodiment, and thus, description thereof is omitted and the shape of the reflective layer 36 is formed. A brief description of how to do this is as follows. White epoxy or silicone with added viscosity-based liquids (eg TiO 2 , ZnO, Lithopone, ZnS, BaSO 4 , SiO 2 , PTFE (polytetrafluoroethylene), etc.) Series liquid material) is dispensed around the top electrodes 38 and 40. As a result, the liquid material gradually spreads laterally and is connected to the outer surfaces of the upper electrodes 38 and 40 and the inner wall of the cavity. As a result, the liquid material becomes inwardly rounded, and, after a certain amount of time, becomes a reflective layer 36 in a gel state. In this case, the reflective layer 36 completely covers the bottom surface of the cavity. If the viscosity and the input amount of the reflective layer 36 is adjusted, it is sufficiently rounded to be naturally inward as shown in FIG. 13 by the surface tension. Depending on the product size, the viscosity, the amount of charge, and the like of the material constituting the reflective layer 36 should be changed.

Thereafter, the reflective layer 36 is cured for about 2 hours at a temperature of about 170 degrees to be well coupled with the base substrate 50. The reflective layer 36 and the base substrate 50 are firmly bonded by curing.

Comparing FIGS. 13A and 13B, in FIG. 13A, all of the top surfaces of the top electrodes 38 and 40 are exposed. In FIG. 13B, the top surfaces of the top electrodes 38 are exposed. Only exposed. In the LED package of FIG. 13A, the mounting of the light emitting device 42 and the bonding of the wire 44 may be performed after the reflective layer 36 is filled so that the top surfaces of the top electrodes 38 and 40 are exposed. Before mounting of the light emitting element 42, it is possible to perform a defective inspection (e.g., whether the electrode is properly formed or the reflective layer 36 is properly formed). In addition, in the LED package of FIG. 13A, the LED package may be sufficiently sold even without the light emitting device 42 and the wire 44.

On the other hand, the LED package of Figure 13 (b) can form a curvature symmetrically around the top electrode 38, it is easy to obtain a desired orientation angle compared to the LED package of Figure 13 (a). Since the LED package of FIG. 13B has a structure in which the reflective layer 36 needs to be charged after the mounting of the light emitting device 42 and the bonding of the wire 44, the finished product must be produced and sold.

In the above description of the embodiments, one light emitting device 42 is mounted on the light emitting diode package. However, even when two or more chip-shaped LEDs are mounted (mounted), the configuration is not only sufficiently applicable, but also the effect thereof. It gets bigger.

On the other hand, the present invention is not limited only to the above-described embodiments and can be carried out by modifications and variations within the scope not departing from the gist of the present invention, the technical idea that such modifications and variations are also within the scope of the claims Must see

1 is a view for explaining the problem of the conventional varistor substrate for the LED package.

2 to 12 are views for explaining the LED package substrate and the LED package using the same with an antistatic function according to an embodiment of the present invention.

FIG. 13 is a view illustrating an LED package substrate having an antistatic function and an LED package using the same according to another embodiment of the present invention.

Description of the Related Art

Green sheets: 10, 12, 14, 16, 18, 20

11, 26a: through hole 22: cutting groove

24: element 26: insulation layer

28 conductive material 30 first metal layer

32: second metal layer 34: third metal layer

36: reflective layer 38, 40: top electrode

39, 41: bottom electrode 42: light emitting element

44: wire 46: substrate

Claims (12)

Including a ZnO-based varistor substrate having an inner electrode and an outer electrode, The external electrode is formed on a portion of the top and bottom surfaces of the varistor substrate via an insulating layer, the external electrode and the internal electrode are electrically connected through a through hole formed in the insulating layer, the varistor substrate The LED package substrate, characterized in that a white reflective layer is formed in the remaining region except for a partial region including the region in which the light emitting element is located on the upper surface of the substrate. The method according to claim 1, The insulating layer is an LED package substrate, characterized in that it comprises at least one of BaO, CaO, K 2 O, ZnO. The method according to claim 1, The insulating layer is an LED package substrate, characterized in that the main material comprises 3 ~ 9wt% BaO, 9 ~ 15wt% CaO, 3 ~ 9wt% K 2 O and 3 ~ 10wt% ZnO. The method according to claim 3, The insulating layer was made of a material containing 5-9 wt% Al 2 O 3 , 50-65 wt% SiO 2 , 1-5 wt% TiO 2, and 2-6 wt% B 2 O 3 together with the main material. An LED package substrate, characterized in that. The method according to claim 1, The reflective layer is a LED package substrate, characterized in that containing a white silicone epoxy resin. The method according to claim 1, The reflective layer includes at least one of TiO 2 , ZnO, lithopone, ZnS, BaSO 4 , SiO 2 , PTFE (polytetrafluoroethylene). The method according to claim 1, The reflective layer includes at least one of TiO 2 , ZnO, lithopone, ZnS, BaSO 4 , SiO 2 , and PTFE (polytetrafluoroethylene) as a main material, and the main material is added at 5 to 60 wt%. LED package substrate. The method of claim 7, The reflective layer is a substrate package for an LED package, characterized in that the use of a subsidiary material having a silicone resin of 5 to 30wt% and an epoxy resin of 20 to 65wt% with the main material. The method according to claim 1, The reflective package is a substrate for an LED package, characterized in that formed flat. The method according to claim 1, And the reflective layer is inwardly rounded. The substrate of any one of Claims 1-10; And LED package, characterized in that it comprises a light emitting element mounted on the upper surface of the substrate. The method of claim 11, The LED package, characterized in that the light emitting device is one or more LED chip type.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101241133B1 (en) 2011-06-29 2013-03-11 (주) 아모엘이디 Non-shrinkage varistor substrate, led package having the same and method for manufacturing non-shrinkage varistor substrate
WO2014035143A1 (en) * 2012-08-28 2014-03-06 ㈜ 아모엘이디 Non-shrink varistor substrate and production method for same
US9391053B2 (en) 2012-08-28 2016-07-12 Amosense Co., Ltd. Non-shrink varistor substrate and production method for same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102084154B1 (en) * 2013-09-11 2020-03-03 엘지이노텍 주식회사 Resin composite and led package comprising esd protection layer using the same
KR101673488B1 (en) * 2014-09-24 2016-11-07 주식회사 아모센스 Non-shrinkage varistor substrate, non-shrinkage varistor substrate array and method for manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207621A (en) 2002-12-26 2004-07-22 Kyocera Corp Package for storing light emitting element and light emitting device
KR100606550B1 (en) 2005-07-04 2006-08-01 엘지전자 주식회사 Light emitting device package and method for fabricating the same
KR100719077B1 (en) 2005-12-13 2007-05-16 (주) 아모센스 Semiconductor package
KR100772646B1 (en) 2006-09-20 2007-11-02 (주) 아모센스 Semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207621A (en) 2002-12-26 2004-07-22 Kyocera Corp Package for storing light emitting element and light emitting device
KR100606550B1 (en) 2005-07-04 2006-08-01 엘지전자 주식회사 Light emitting device package and method for fabricating the same
KR100719077B1 (en) 2005-12-13 2007-05-16 (주) 아모센스 Semiconductor package
KR100772646B1 (en) 2006-09-20 2007-11-02 (주) 아모센스 Semiconductor package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101241133B1 (en) 2011-06-29 2013-03-11 (주) 아모엘이디 Non-shrinkage varistor substrate, led package having the same and method for manufacturing non-shrinkage varistor substrate
WO2014035143A1 (en) * 2012-08-28 2014-03-06 ㈜ 아모엘이디 Non-shrink varistor substrate and production method for same
US9391053B2 (en) 2012-08-28 2016-07-12 Amosense Co., Ltd. Non-shrink varistor substrate and production method for same

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