KR100980810B1 - Image Sensor Module Capable of Wafer Level-Chip Scale Package and Fabricating Method thereof - Google Patents

Abstract

The present invention relates to an image sensor module, an image sensor module assembly, and a method of manufacturing the same, which are simple in structure and manufacturing process and capable of a full wafer level-chip scale package (WL-CSP).

The image sensor module of the present invention comprises a glass substrate; An image sensing semiconductor device spaced apart from the glass substrate and formed to face each other, an image detection region formed on a central surface thereof, and a plurality of bump pads disposed on a periphery thereof; A plurality of wires extending outwardly from positions corresponding to the plurality of bump pads on the glass substrate, respectively; A plurality of solder bumps formed on the plurality of wires at positions corresponding to the plurality of bump pads, respectively, to couple the wires of the glass substrate to the semiconductor elements; And a sealing dam surrounding the outer side of the image detection region between the glass substrate and the semiconductor element in a closed loop shape to seal the image detection region, wherein the sealing dam is previously formed on either of the glass substrate and the semiconductor element. After being formed and attached to each other by compression, the semiconductor device is characterized in that it is diced from the semiconductor wafer so as to coincide with the outer peripheral portion of the sealing dam.

Image Sensor Module, Wafer Level, Chip Scale Package, Sealing, Crimp Bonding

Description

Image Sensor Module Capable of Wafer Level-Chip Scale Package and Fabricating Method

The present invention relates to an image sensor module capable of a wafer level-chip scale package and a manufacturing method thereof, and more particularly, to an image sensor module capable of a full wafer level-chip scale package (WL-CSP) and a method of manufacturing the same. .

In the case of a general semiconductor device, that is, a chip, a package, usually called a plastic package, is widely used, and has a structure of completely sealing the semiconductor device using a sealing material such as an epoxy resin. On the other hand, in the case of an image sensor, it is impossible to use such a normal plastic package because light must reach at least the image sensing area of the device surface in order to sense the image.

Ceramic packages having glass covers are widely used as electronic packages for image sensors and photodetection semiconductor devices. However, the ceramic package has the advantages of being robust, but it is expensive and difficult to miniaturize. Due to these characteristics, many ceramic packages are used in products such as high-end digital cameras or camcorders that require high reliability and have relatively small size and price requirements. On the other hand, ceramic products are hard to find in applications where price competition and miniaturization are important, such as camera phones.

Generally, a package of a plastic leadless chip carrier (PLCC) type using an epoxy molding compound, a lead frame, and a glass cover has been widely used as a package for an image sensor. Such a package has the advantage of being inexpensive compared to the ceramic package, but has the disadvantage of being not as robust as the ceramic package and difficult to miniaturize like the ceramic package. For this reason, these packages have been widely applied in applications such as PC cameras, which require relatively small size and high price.

In addition, a package having a structure similar to that of a ceramic package has been proposed as a package for an image sensor using a relatively inexpensive plastic substrate instead of an expensive ceramic substrate, which is still difficult to miniaturize like a ceramic package. have.

The above-listed packages have in common that they are not easy to miniaturize, and with the rapid growth of the market requiring miniaturization such as camera phones, chip scale packages for low-cost small image sensors (hereinafter referred to as 'CSP') Interest in technology has been heightened.

A miniaturized CSP technology for image sensors has been proposed by Shell Case. The detailed description is described in US Pat. Nos. 5,716,759, 6,040,235 and 6,117,707. This CSP for image sensor has the advantage of having a smaller size compared to the PLCC package, but has a complex disadvantage in the construction and manufacturing process. This complexity tends to increase production yield loss and is therefore an important factor in mass production. As a result of this complexity and the accompanying loss of yield, there is a disadvantage that the manufacturing cost is high.

In addition, in the conventional CSP package method, good and defective devices on the image sensor wafer go through all the processes required for packaging together. When the yield of the image sensor wafer is low, it is a very unproductive method, thereby reducing the package price. It is a factor that greatly increases. For example, if the yield of an image sensor wafer is 80% in one case and 40% in half the yield, the package price is doubled. This is a common problem in wafer level packaging where all processes are performed in the wafer state. Due to the disadvantages pointed out above, this conventional package method is not applied in spite of the advantages of miniaturization.

On the other hand, when dust particles are generally introduced into the image sensor package and fixed to the image sensing area of the image sensor, repetitive defects may be caused in the captured image. Even if they are not stuck in the image sensing area, the dust molecules moving in them are non-repetitive but unacceptable because they can cause defects. If the image sensing area of the image sensor is contaminated, a defect is caused for the same reason. Therefore, image sensor packaging should minimize the ingress or contamination of dust particles into the package during the manufacturing process. This is why the image sensor packaging manufacturing line is managed with higher cleanliness than other standard packaging manufacturing lines. In addition, for the same reason, the image sensor package should be sufficiently sealed so that dust particles cannot be introduced even after packaging.

The above-described image sensor packages have a device which can prevent the inflow of dust particles for this reason. For example, in the case of a ceramic package, the glass cover is bonded to the ceramic substrate to form a cavity in the package, and thereafter, it is possible to prevent the inflow of dust particles into the interior.

Inflow of water into the image sensing area is known to degrade color filters or micro lenses on the image sensor chip. Of course, this deterioration due to moisture takes a long time to appear as a deterioration of the image quality, which is generally not a problem. There is a need for a package structure that can be minimized.

One method for sealing image sensing regions in package structures with flip chip solder joints has been proposed by IMEC vzw. The detailed description is described in US Pat. No. 6,566,745.

The package described in US Pat. No. 6,566,745 uses a flip chip solder joint to electrically connect the image sensor chip and the terminals of the chip to a glass substrate, and form solder balls connected to the solder joint by electrical wiring at the periphery of the package. And a solder sealing ring in the form of a closed loop to seal the image sensing area formed inside the terminal of the chip, and added to the outer shell of the solder sealing ring. Epoxy sealing is formed.

The sealing formed as a hermetically sealed structure by metal bonding is called a hermetic sealing, and the term hermetic means a sealing that can inhibit moisture penetration. On the contrary, the term non-hermetic sealing is used, which means a seal which can penetrate moisture by diffusion, and is formed when a seal is formed using a resin such as epoxy.

In order to form the sealing structure of US Pat. No. 6,566,745, it is necessary to first fuse while maintaining a vacuum. In general, when flip chip solder is fused, the flip chip solder bumps of the chip collaps while being fused to the substrate. That is, the height of the solder bumps is lowered the height of the solder joint after fusion to the terminal of the substrate. For example, a solder bump with a height of 50 μm may form a solder joint with a height of 30 μm after fusion. Of course, the degree of collapsing depends on the size of the terminal to be fused.

The solder sealing ring proposed in US Pat. No. 6,566,745 has a closed loop shape, unlike solder bumps. Therefore, at the time of film fusion, a cavity is formed that surrounds the image sensing area.If this process is not performed under vacuum, the collapsing of the flip chip solder bump and the solder sealing ring is disturbed due to the air pressure trapped in the cavity. do. In practice, very complex phenomena occur. As a result, when this collapsing is disturbed, a poor bonding occurs during solder fusion, resulting in a decrease in yield. Therefore, this technique requires solder fusion or a similar method while maintaining a vacuum.

In addition, during soldering, a material called flux is used for the solder joint, which serves to remove the oxide layer of the joint before welding and to prevent oxidation during welding. By the way, the solvent in the flux vaporizes during the reflow process (this is called outgassing), and this vaporized solvent is trapped in the cavity if there is no passage to release, and eventually sticks to it. It will contaminate the inside of the cavity. Therefore, in order to use the sealing technique proposed in the US patent, a fluxless soldering technique using no flux is required.

A technique commonly used for solder fusion, called surface mounting, uses a method of passing a product to be solder fused through equipment such as a belt oven. On the other hand, the method of solder welding while maintaining the vacuum has not been developed for the commercialized equipment for mass production, and even if developed, the unit equipment price is much more expensive than the general belt oven, and the productivity is large. As it is expected to be lowered, there is a problem that greatly increases the manufacturing cost of the package. Of course, there is another factor in the increase in manufacturing costs, which requires the use of flux-free soldering techniques.

Korean Patent No. 498708 has a high sealing reliability at low cost in consideration of the problems of the hermetic sealing structure of US Pat. No. 6,566,745, and a sealing structure by solder sealing rings can be formed using the infrastructure currently in use. There is proposed a package for a semiconductor device having a sealing property that can be superior to the existing epoxy sealing structure.

The electronic package for a semiconductor device of the Korean Patent No. 498708 includes (a) a plurality of input / output terminals, a plurality of flip chip solder bump pads for forming flip chip solder joints on the plurality of input / output terminals, and a sealing area requiring sealing. A semiconductor device chip including a first solder sealing ring pad surrounding the sealing region; (b) a second solder formed on the substrate in a structure surrounding the substrate disposed to face the semiconductor device chip and the sealing area of the substrate facing the sealing area of the semiconductor device chip corresponding to the first solder sealing ring pad; Sealing ring pads, a plurality of metal wiring layers formed on a substrate around the second solder sealing ring pads, and a plurality of flip chip solder bump pads on the semiconductor device chip, and used for electrical connection with the semiconductor device chip. The plurality of first contact terminals, a plurality of second contact terminals for electrically connecting to the outside, and a plurality of metal wires for interconnecting the plurality of first and second contact terminals. A substrate assembly comprising at least one passivation layer formed over the metallization layer; (c) a plurality of flip chip solder joints for electrically connecting the plurality of flip chip solder bump pads and the plurality of first contact terminals; (d) a solder sealing ring fused to the first and second solder sealing ring pads to surround the sealing area of the semiconductor device, and having an air passage through which air can be released during welding of the solder; have.

The electronic package also includes a polymer seal for sealing the air passage to enhance sealing properties.

The above-mentioned conventional electronic package solves the problems of the solder fusion equipment of the hermetic sealing using the solder and the fluxless soldering process and at the same time provides the first and second solders with a non-hermetic sealing having a sealing effect close to the hermetic sealing. A solder sealing ring is fused to the sealing ring pad to surround the sealing region of the semiconductor device, and has a solder passage having an air passage through which air is released when the solder is welded, and a polymer sealing for sealing the passage.

In particular, the electronic package proposes a structure in which a solder sealing ring is formed to have a tunnel-type air passage and a low viscosity epoxy is dispensed in a narrow air passage portion to seal it.

As a result, in the electronic package, when the epoxy is dispensed to the periphery of the image sensor chip in the absence of a structure such as a solder sealing ring, the surface tension and the surface tension at the same time when dispensing a general epoxy sealing material having a low viscosity Due to the resin bleed that the epoxy flows between the image sensor chip and the substrate, the central image sensing area is easily solved by the epoxy and the productivity problem.

The electronic package for semiconductor device of the Korean Patent No. 498708 forms a plurality of flip chip solder bumps while forming a solder sealing ring on a solder sealing ring pad of a semiconductor wafer when assembling / connecting an image sensing semiconductor device and a unit substrate assembly. A plurality of semiconductor wafers are formed with a plurality of flip chip solder bumps formed in a pad, and access openings for contact terminals to which the flip chip solder bumps are attached to by a plurality of passivation layers formed on the plurality of metal wiring layers in the unit substrate assembly. The semiconductor device die of the die is separated (diced), and each semiconductor device die is placed on a unit substrate, and the solder sealing ring of each die is coupled to the first access opening by a pick-flip-place operation, and a plurality of flip chip solder bumps are removed. After joining to a plurality of first contact terminals, it is heated by reflow soldering to solder solder rings and a plurality of plugs. There was fused the chip solder bumps.

As described above, the electronic package of patent 498708 separates a plurality of semiconductor element dies from a semiconductor wafer rather than a dicing process for separating an assembly in a final process after all processes are processed at the wafer level. ), Each semiconductor element die is separately assembled on the unit substrate by a pick-flip-place operation, resulting in a problem of low productivity.

In addition, in Patent No. 487908, each semiconductor device die is individually assembled on a unit substrate by a pick-flip-place operation using flip chip mounting equipment, thereby providing access openings for contact terminals to which flip chip solder bumps are attached. It must be defined by multiple passivation layers to prevent the flip chip solder bumps from connecting to other parts. However, assembling the semiconductor device dies individually may cause a problem in that the connection accuracy of each terminal may be degraded at high speed.

Furthermore, Patent No. 487708 has a process of assembling each semiconductor device die on a unit substrate and a separate reflow soldering process for bonding solder to the sealing ring pads, which does not attempt to simplify the process and increases manufacturing costs. It is a factor. In addition, the sealing structure using the solder sealing ring is applicable only when sufficient space is secured between the image sensing area requiring sealing and the plurality of input / output terminals, otherwise it cannot be applied.

In addition, in Patent No. 498708, at the wafer level, the semiconductor wafer and the glass wafer do not form a sealing dam at the same time as the contact terminals are connected, and after assembly of the respective semiconductor device dies on the unit substrate, the solder sealing ring is fused. The sealing structure is completed through a two-step process including a reflow soldering process of joining a semiconductor element die on a unit substrate and a process of dispensing and sealing a low viscosity epoxy in the tunnel-type air passage portion provided in the solder sealing ring. However, there is a problem that the process is not simplified.

Furthermore, in Patent No. 487708, a plurality of semiconductor device dies are separated (diced) from a semiconductor wafer prior to the final process, and each semiconductor device die is individually assembled on a unit substrate by a pick-flip-place operation and subsequent processes. Going on. Therefore, it is difficult to introduce a process for minimizing the thickness of the finished package assembled by removing the unnecessary thickness of the semiconductor wafer and the glass substrate during the assembly process, as a result there is a problem that can not minimize the thickness.

On the other hand, Korean Patent Laid-Open No. 2006-97193 discloses a sealing dam and a bump on a semiconductor device and a glass substrate, respectively, and then thermosets such as epoxy to prevent exposure of the dam and the bump before dicing in a bonded state. The peripheral part is molded with resin. Therefore, in order to perform this manufacturing process at the wafer level, a procedure of forming through-lines necessary for epoxy molding between glass substrates is required in advance.

In addition, although the dam formation and the epoxy molding are sequentially performed in the prior art, a structure for performing a necessary function by only one of the dam formation and the epoxy molding is preferable.

Accordingly, the present invention is conceived in view of the problems of the prior art, the object of which is that the chip scale packaging (CSP) is processed wafers all processes at the wafer level, the wafer is a dicing process for separating the assembly in the final process The present invention provides an image sensor module and a method of manufacturing the same having excellent assembly productivity as packaging is performed by a level chip scale packaging (WLCSP) method.

Another object of the present invention is to eliminate the reflow soldering process by interconnecting the connection terminals by heat-compressing the semiconductor wafer and the glass wafer at the wafer level, and at the same time, conventionally using a flip chip mounting apparatus for each semiconductor element die on a unit substrate. To provide an image sensor module with high assembly productivity that can solve the problem of connection accuracy of each terminal by pick-flip-place operation and a long process time due to individual assembly, and a manufacturing method thereof. have.

Another object of the present invention is to complete the package assembled by removing the unnecessary thickness of the semiconductor wafer and the glass wafer before the dicing process as the dicing process for separating the assembly in the final process after processing all processes at the wafer level It is to provide an image sensor module and a method of manufacturing the same that can minimize the thickness of the.

Another object of the present invention is to provide an image sensor module and a method for manufacturing the same, which can simplify the assembly process because the semiconductor wafer and the glass wafer are bonded at the same time as the contact terminals of the sealing dams at the wafer level. have.

Another object of the present invention is to form a sealing dam on a glass wafer by hot embossing or photolithography, and then at the wafer level, the semiconductor wafer and the glass wafer are connected to the sealing terminal at the same time as the connection of the sealing dam. The present invention provides a method of manufacturing an image sensor module that can eliminate the dispensing process using a low viscosity epoxy that can cause a resin bleed problem.

Another object of the present invention is to provide an image sensor module having a structure capable of simultaneously sealing a bump for contact terminal connection with a sealing function for an image detection area by a sealing dam, and a manufacturing method thereof.

In order to achieve the above object, an image sensor module according to an aspect of the present invention comprises a glass substrate; An image sensing semiconductor device spaced apart from the glass substrate and formed to face each other, an image detection region formed on a central surface thereof, and a plurality of bump pads disposed on a periphery thereof; A plurality of wires extending outwardly from positions corresponding to the plurality of bump pads on the glass substrate, respectively; A plurality of solder bumps formed on the plurality of wires at positions corresponding to the plurality of bump pads, respectively, to couple the wires of the glass substrate to the semiconductor elements; And a sealing dam surrounding the outer side of the image detection region between the glass substrate and the semiconductor element in a closed loop shape to seal the image detection region, wherein the sealing dam is previously formed on either of the glass substrate and the semiconductor element. After being formed and attached to each other by compression, the semiconductor device is characterized in that it is diced from the semiconductor wafer so as to coincide with the outer peripheral portion of the sealing dam.

According to another aspect of the present invention, an image sensor module includes a glass substrate; An image sensing semiconductor device spaced apart from the glass substrate and formed to face each other, an image detection region formed on a central surface thereof, and a plurality of bump pads disposed on a periphery thereof; And a sealing dam surrounding the outer side of the image detection region between the glass substrate and the semiconductor element in a closed loop shape to seal the image detection region, wherein the sealing dam is previously formed on either of the glass substrate and the semiconductor element. After being formed and attached by mutual compression, the glass substrate is characterized in that it is diced from the glass wafer to match the outer peripheral portion of the sealing dam.

The image sensor module may further include a plurality of solder bumps respectively formed on the plurality of bump pads to couple the semiconductor device and the FPCB.

The plurality of wires may include a first metal film serving as an adhesive layer and a second metal film having excellent conductivity formed on the first metal film, and the solder bumps may include a wetting layer for solder and a lead-free solder.

In addition, the sealing dam is preferably made of a thermosetting resin or photocurable resin.

In this case, the sealing dam may be disposed between the image detection region and the plurality of bump pads of the semiconductor device, or may be disposed to surround the plurality of bump pads and the plurality of bumps from the outside of the image detection region.

The method of manufacturing the image sensor module includes preparing a semiconductor wafer having a plurality of image sensing semiconductor elements each having an image detection region formed on a central surface thereof and a plurality of bump pads disposed on a peripheral portion thereof; Preparing a glass wafer having a plurality of unit glass substrates; Forming a plurality of wirings extending outwardly from positions corresponding to the plurality of bump pads, respectively, on the plurality of unit glass substrates; Selectively forming a plurality of solder bumps at positions corresponding to the plurality of bump pads, respectively, on the plurality of wires; Forming a plurality of dust sealing dams in a closed loop shape on any one of the unit glass substrate and the semiconductor element when the unit glass substrate and the semiconductor element are bonded to each other; Aligning a glass wafer against the semiconductor wafer such that the plurality of solder bumps coincide with the plurality of bump pads, and then compressing and bonding the glass wafers; And dicing the semiconductor wafer and the glass wafer, respectively, to separate a plurality of image sensor modules each having a semiconductor device coupled to a unit glass substrate.

The forming of the plurality of wires may include forming a photoresist pattern on a glass wafer, the photoresist pattern forming a complementary pattern for the plurality of wires; Forming a wiring metal layer on an entire surface of the glass wafer on which the photoresist pattern is formed; And removing the photoresist pattern by a lift-off method to leave only the metal layer formed directly on the unit glass substrate as a wiring.

The forming of the plurality of solder bumps may include forming a photoresist pattern on the glass wafer, the photoresist pattern having a plurality of contact windows, respectively, on the plurality of wires, the contact pads having positions corresponding to the plurality of bump pads, respectively; Selectively forming a plurality of solder bumps on the plurality of wires through the plurality of contact windows by electroplating; Planarizing an upper portion of the glass wafer to expose a tip of the solder bump while matching the heights of the plurality of solder bumps; And removing the photoresist pattern.

Furthermore, the plurality of wirings are interconnected by plating electrode lines, and the plating electrode lines are preferably used as cathode electrodes when forming solder bumps by electroplating. In this case, the plurality of solder bumps may consist of a wetting layer for the solder and a lead-free solder.

Meanwhile, the forming of the plurality of dust sealing dams may be performed for each of the unit glass substrates of the glass wafer by a hot embossing method using a thermosetting polymer resin or a UV imprinting lithography method using a photocurable polymer resin. .

In this case, the forming of the plurality of dust sealing dams by the hot embossing method may include forming a thermosetting polymer resin layer on a glass wafer on which a plurality of wirings and a plurality of solder bumps are formed per unit glass substrate; Aligning and heating and pressing a dam-forming stamp having a complementary recess for the plurality of dust sealing dams on the glass wafer having the thermosetting polymer resin layer formed thereon; And separating the dam forming stamp from the glass wafer and ashing a portion of the thermosetting polymer resin layer compressed to expose the solder bumps, a portion of the wiring, and a glass substrate.

The forming of the plurality of dust sealing dams by the UV imprinting lithography method may include forming a photocurable polymer resin layer on a glass wafer on which a plurality of wires and a plurality of solder bumps are formed per unit glass substrate. ; Arranging and pressing a dam-forming stamp formed of a transparent material on the glass wafer having the photocurable polymer resin layer formed on a lower surface thereof with complementary recesses for the plurality of dust sealing dams; Curing the photocurable polymer resin layer by irradiating ultraviolet rays while pressing the photocurable polymer resin layer with the dam forming stamp; And separating the dam forming stamp from the glass wafer and ashing a portion of the photocurable polymer resin layer compressed to expose the solder bumps, a portion of the wiring, and a glass substrate.

Further, the forming of the plurality of dust sealing dams may be formed for each of the plurality of unit glass substrates of the glass wafer by a photolithography method using a photocurable polymer resin.

The method of manufacturing the image sensor module may further include polishing the glass wafer and the semiconductor wafer to a predetermined thickness after the step of aligning the glass wafer to the semiconductor wafer and then pressing and bonding the glass wafer.

The separating of the plurality of image sensor modules may include dicing each semiconductor element from the semiconductor wafer to coincide with an outer circumferential portion of a sealing dam, and dicing a plurality of unit glass substrates along the plating electrode lines of the glass wafer. It may consist of steps.

The image sensor module manufacturing method may further include bonding a flexible film member to a plurality of exposed wires by separating the plurality of image sensor modules.

In this case, it is preferable that the flexible film member has a through hole corresponding to the semiconductor element, and includes a plurality of bonding pads corresponding to a plurality of wirings exposed around the through hole.

The press bonding may include aligning a glass wafer against the semiconductor wafer such that the plurality of solder bumps coincide with the plurality of bump pads; And melting and bonding the plurality of solder bumps to the plurality of bump pads, respectively, by heating and compressing the glass wafer and the semiconductor wafer, and bonding the front ends of the plurality of dust sealing dams to opposite sides of the unit glass substrate or the semiconductor device. It may include.

According to another aspect of the present invention, there is provided a method of manufacturing an image sensor module, comprising: preparing a semiconductor wafer having a plurality of image sensing semiconductor elements each having an image detection region formed on a central surface thereof and a plurality of bump pads disposed on a periphery thereof; Forming a plurality of solder bumps on the plurality of bump pads, respectively; Preparing a glass wafer having a plurality of unit glass substrates; Forming a plurality of closed-loop dust sealing dams on the unit glass substrate to seal the image detection region when the unit glass substrate and the semiconductor device are bonded to each other; Aligning and pressing the glass wafer so as to face the semiconductor wafer such that each of the plurality of dust sealing dams surrounds a corresponding image detection area; And dicing the semiconductor wafer and the glass wafer, respectively, to separate a plurality of image sensor modules each having a unit glass substrate coupled to a semiconductor device.

The separating of the plurality of image sensor modules may include dicing each semiconductor element from the semiconductor wafer, and dicing a unit glass substrate from a glass wafer to coincide with an outer circumferential portion of the sealing dam. .

In addition, the forming of the plurality of dust sealing dams may be performed by any one of a hot embossing method, a UV imprinting lithography method, and a photolithography method.

The present invention may further include bonding the flexible film member to a plurality of solder bumps after separating the plurality of image sensor modules.

On the other hand, according to another feature of the invention, the present invention is a glass wafer having a plurality of unit glass substrate; A semiconductor wafer spaced apart from the glass wafer, the semiconductor wafer including a plurality of image sensing semiconductor elements each having an image detection region formed on a surface of a central portion thereof and a plurality of bump pads disposed on a periphery thereof; A plurality of wires extending outwardly from positions corresponding to the plurality of bump pads, respectively, on the glass substrates; A plurality of solder bumps formed on the plurality of wires at positions corresponding to the plurality of bump pads, respectively, to couple the wires of the glass substrate to the semiconductor elements; And a plurality of sealing dams enclosed in a closed loop shape to include solder bumps and an outer side of the image detection area between the opposing glass substrate and the semiconductor device to seal the respective image detection areas. Each of the dams is provided in advance in any one of the corresponding glass substrate and the semiconductor device, and provides an image sensor module assembly, characterized in that attached by mutual compression.

According to another feature of the invention, the present invention is a glass wafer having a plurality of glass substrates; A semiconductor wafer formed so as to face away from the glass wafer and having a plurality of image sensing semiconductor elements having an image detection region formed on a surface of each central portion and having a plurality of bump pads disposed at a peripheral portion thereof; And a plurality of sealing dams surrounding the outer side of the image detection area between the glass substrate and the semiconductor element in a closed loop shape to seal the respective image detection areas, wherein each of the plurality of sealing dams corresponds to a corresponding glass. Provided is an image sensor module assembly, which is formed in advance on any one of a substrate and a semiconductor device and then attached by mutual compression.

As described above, in the present invention, the chip scale packaging (CSP) is processed in a wafer level chip scale packaging (WLCSP) method in which a dicing process for separating an assembly in a final process after processing all processes at the wafer level is performed. As a result, the assembly productivity is excellent, and slimming can be achieved.

In addition, the present invention eliminates the reflow soldering process by interconnecting the connection terminals by heat-compressing the semiconductor wafer and the glass wafer at the wafer level, while simultaneously picking each semiconductor device die onto the unit substrate using flip chip mounting equipment. It is possible to solve the problem that the connection accuracy of each terminal due to the flip-place operation and the process time due to the individual assembly are increased.

Furthermore, in the present invention, since the dicing process for separating the assembly in the final process after processing all processes at the wafer level, the thickness of the finished package assembled by removing the unnecessary thickness of the semiconductor wafer and the glass wafer before the dicing process Can be minimized.

In the present invention, since the semiconductor wafer and the glass wafer are bonded at the same time as the contact terminals and the sealing dams are connected at the wafer level, the assembly process can be simplified.

Furthermore, in the present invention, since the sealing dam is formed on the glass wafer by hot embossing or photolithography, the semiconductor wafer and the glass wafer are connected at the wafer level at the same time as the contact terminal and the sealing dam is formed. It is possible to eliminate the dispensing process using low viscosity epoxy which can cause resin bleed problems.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of an image sensor module according to the present invention. As shown, the image sensor module 100 of the present invention comprises a glass substrate 110 made of a transparent insulating material, for example, glass; An image sensing semiconductor device 210 formed to face the glass substrate 110 at a predetermined distance, and having an image detection area 220 formed on a central surface thereof, and having a plurality of bump pads 215 disposed on a periphery thereof; A plurality of wires 132 formed on the glass substrate 110 and extending outwardly from positions corresponding to the plurality of bump pads 215, respectively; A plurality of solder bumps are formed on the plurality of wirings 132 at positions corresponding to the plurality of bump pads 215, respectively, to couple the wiring 132 of the glass substrate 110 to the semiconductor device 210. 142); And a ring-shaped sealing dam 172 surrounding the outer side of the image detection region 220 between the glass substrate 110 and the semiconductor element 210 to seal the image detection region 220.

The image sensing semiconductor device 210 may use a photo sensor or a photo detector, for example, a CMOS image sensor (CIS) manufactured by various types of technologies such as a CCD or a CMOS.

In the image sensor module 100 according to the present invention, a wafer level-chip scale package (WL-CSP) may be formed. In this case, the chip scale packaging (CSP) may process all processes at the wafer level and then the final process. As the packaging is done in a full wafer level chip scale packaging (WL-CSP) method in which a dicing process is performed to separate the assembly from the assembly, the assembly productivity is excellent and the slimming can be achieved.

The image sensor module according to the present invention configured as described above will be described in detail below by explaining a manufacturing method thereof.

2A to 2C are cross-sectional views illustrating a process of forming wirings on a unit glass substrate, respectively, and FIG. 3A is a plan view of a glass wafer for explaining a process of forming wirings on a unit glass substrate. 3B is an enlarged plan view showing plating electrode lines when wiring is formed on the unit glass substrate by an electroplating method, and FIG. 3C is a plan view of the unit glass substrate on which the wiring is formed.

Referring to FIG. 2A, after the photoresist is coated on the transparent insulating glass substrate 110, the photoresist pattern 120 spaced a predetermined distance by photolithography is formed. The photoresist pattern 120 forms a complementary pattern for the plurality of wirings 132 to be formed in a subsequent process. That is, the photoresist pattern 120 serves as a mold for forming the wiring formed of the metal layer without undergoing a separate etching process in a subsequent process. In this case, for example, a negative photoresist such as 6000PY may be used as the material of the photoresist pattern 120.

Thereafter, as shown in FIG. 2B, the wiring metal layer 130 is deposited on the entire surface of the glass substrate 110 on which the photoresist pattern 120 is formed by sputtering. The wiring metal layer 130 is first formed to a thickness of 300 kPa using Cr having excellent adhesion to the glass substrate 110 as an adhesive layer, and then to a thickness of 1000 to 2000 kPa using Au having excellent conductivity. Form. The wiring metal layer 130 may use other well-known wiring metals.

Subsequently, as shown in FIG. 2C, by removing the photoresist pattern 120 in a lift-off manner, the wiring metal layer 130 formed on the photoresist pattern 120 is also removed to remove the glass substrate ( A plurality of wires 132 are left in desired portions on the 110. Removing the photoresist pattern 120 in the lift-off manner may be removed using ashing or a solvent.

As shown in FIGS. 3B and 3C, the plurality of wires 132 are formed at positions corresponding to the plurality of bump pads 215 of the semiconductor device 210 for image sensing, respectively, to form the glass substrate 110. A first region 132a having a small size in which a plurality of solder bumps 142 joining the wiring 132 and the semiconductor element 210 are formed, and are formed to extend outwardly from the first region 132a The large sized second region 132b used to connect the FPCB connected as an interface for connecting the image sensor module 100 to an external device.

3A is a plan view of a glass wafer 105 for explaining a process of forming the wiring 132 on the unit glass substrate 110 as shown in FIGS. 2A to 2C. For example, a plurality of unit glass substrates 110 are included. In the present invention, all processing is performed at the wafer level until the dicing process of dividing the glass wafer 105 including the plurality of unit glass substrates 110 into the unit glass substrates 110 is performed.

FIG. 3B is an enlarged view of a unit glass substrate in FIG. 3A, which illustrates a plating electrode line used to form solder bumps on an interconnect by an electroplating method, and FIG. 3C illustrates a unit glass substrate on which a plurality of interconnects 132 are formed. A plan view of 110 shows a state of dicing along the plating electrode line.

In the present invention, as described later, the solder bumps are formed on the respective wirings 132 using an electroplating method. Accordingly, as shown in FIG. 3B, the plurality of wires 132 are connected to each other by the plating electrode lines 134 orthogonal to each other.

The plurality of wirings 132 and the plating electrode lines 134 are used as a seed layer for electroplating, that is, a cathode electrode, which is performed in a subsequent process.

4A to 4D are cross-sectional views illustrating the process of forming solder bumps on the unit glass substrate according to the present invention, respectively, and the process of forming the solder bumps will be described below.

First, referring to FIG. 4A, the wiring 132 is formed such that one contact window 124 is formed in each of the first regions 132a of the plurality of wirings 132 corresponding to the plurality of bump pads 215. A photoresist is coated on the formed glass substrate 110 and a photoresist pattern 122 for a mold is formed by a photolithography process. As the photoresist, a negative photoresist for plating of JSP company is used, and the photoresist pattern 122 for mold has a thickness of 30 μm or more.

Referring to FIG. 4B, each of the plurality of wirings 132 and the plating electrode lines 134 is soldered to the contact window 124 by electroplating using a seed layer for electroplating, that is, a cathode electrode. The bump 142 is formed.

The solder bump 142 may first be electrodeposited Cu to a thickness of 23 μm using a metal material which may be used as a conventional electrode material, and then lead-free solder having a melting point of 138 ° C., for example, 58 wt% Electrodeposit Bi-42wt% Sn to 4μm thickness. In this case, Cu serves as a wetting layer for the solder, and the lead-free solder material is preferably a soldering material such as Si-Ag, Si-Au, Sn-Ag, Sn-Au, or Sn, in addition to Bi-Sn.

Subsequently, as shown in FIG. 4C, the sum of the heights of the wiring 132 and the solder bumps 142 is set to a desired size, that is, 25 μm, and the upper end of the solder bumps 142 is exposed using the CMP method. The upper portion of the glass substrate 110 is planarized.

Thereafter, when the flattened mold photoresist pattern 122a is removed using ashing or a solvent, a solder bump 142 is formed as shown in FIG. 4D.

FIG. 5 is a plan view illustrating the unit glass substrate 110 on which the wiring 132 and the solder bumps 142 illustrated in FIG. 4D are formed.

In the present invention, when forming a dust sealing dam on a glass substrate, each semiconductor element die is assembled on a unit substrate commonly used in the prior art, and then a solder sealing ring is fused to bond the semiconductor element die to the unit substrate, Instead of employing a process of dispensing and sealing a low viscosity epoxy, a curable resin, for example, a photoresist, is formed in advance on a glass substrate by hot embossing.

In the present invention, as described below, the photoresist is pre-formed on the glass substrate 110 by hot embossing to prevent ring contamination of the image detection region 220 of the semiconductor device 210. The dam 172 can be formed.

6A to 6D are cross-sectional views illustrating a process of manufacturing a dam forming stamp used when forming a dust sealing dam by a hot embossing method according to an embodiment of the present invention. 7A to 7D are cross sectional views illustrating a process of forming a dust sealing dam on a glass substrate according to an embodiment of the present invention, respectively. FIG. 8 is a plan view of a unit glass substrate in which a dust sealing dam shown in FIG. 7D is formed.

6A to 6D, a process of manufacturing a dam forming stamp used when forming a dust sealing dam by a hot embossing method according to an embodiment of the present invention will be described.

First, referring to FIG. 6A, a silicon substrate 300 is prepared. In the present invention, since the hot embossing is made at the wafer level, the dam forming stamp used therein is also manufactured by using a silicon wafer to be pressed to a plurality of unit glass substrates at a wafer size, but for convenience of description, a single unit corresponding to the unit glass substrate is provided. An example of a silicon substrate will be described.

A photoresist pattern having the same size and shape (that is, a pattern) as the dust sealing dam 172 to be coated on the silicon substrate 300 and formed on the glass substrate 110 by a photolithography process. 302 is formed to obtain a stamp mold. As the photoresist, Japanese photovoltaic negative photoresist is used, and the photoresist pattern 302 preferably has a thickness of 25 μm.

Instead of the photoresist used as the stamp mold, a polymer made of any one selected from polyimide and epoxy may be laminated and used on a silicon wafer.

Thereafter, as shown in FIG. 6B, a seed metal layer 304 necessary for forming a dam forming stamp made of metal on the front surface of the photoresist pattern 302 by electroplating is formed by sputtering. The seed metal layer 304 is preferably made of a highly durable metal material, for example, Ni, and has a thickness of about 1000 mm 3.

Subsequently, when the seed metal layer 304 is used as a cathode for electroplating, and formed to a thickness of about 300 μm using Ni or PDMS (polydimethylsiloxane) by an electroplating method, it is obtained as shown in FIG. 6C.

Thereafter, as shown in FIG. 6D, the dam forming stamp 310 made of Ni is separated from the mold by melting the silicon substrate 300 and the photoresist pattern 302 by using TMAH or KOH solution.

 The dam forming stamp 310 has a recess 315 having the same size and shape (ie, pattern) as that of the photoresist pattern 302, that is, the dust sealing dam 172. That is, the pattern of the recess 315 has the same band shape as the dust sealing dam 172 shown in FIG. 8.

Hereinafter, a process of forming a dam for dust sealing on a glass substrate using the dam forming stamp 310 obtained in FIG. 6D will be described with reference to FIGS. 7A to 7D.

Referring to FIG. 7A, a photoresist layer is formed by applying a thermosetting polymer resin (for example, a photoresist) to the entire surface of the glass substrate 110 on which the wiring 132 and the solder bumps 142 obtained in FIG. 4D are formed. Form 170. For example, the photoresist layer 170 may have a thickness of about 30 μm.

Thereafter, as shown in FIG. 7B, the glass substrate 110 on which the dam forming stamp 310 and the photoresist layer 170 are formed is aligned.

In this state, as shown in FIG. 7C, the dam-forming stamp 310 is pre-heated at a temperature of 150 to 170 ° C. to pressurize the glass substrate 110 with a force of at least 5 kN and hot emboss. When the photoresist layer 170 is pressed by the dam forming stamp 310, the photoresist layer 170 is compressed while being patterned in the same shape as the recess 315 of the dam forming stamp 310.

Thereafter, the dam forming stamp 310 is released from the glass substrate 110 and the surface of the solder bump 142 is exposed so that the unit glass substrate 110, the wiring 132, and the solder bumps ( By removing the photoresist remaining on the upper surface of the 142 by an ashing process, the dust sealing dam 172 having the same height as that of the solder bump and having a ring shape (ie, a closed loop shape) as shown in FIG. 7D. Complete At this time, the dust sealing dam 172 preferably has a thickness of about 25 μm.

In this case, the dust sealing dam 172 formed by the recess 315 is obtained as shown in FIG. 8, and the pattern of the dust sealing dam 172 surrounds a part of the wiring 132 and the solder bump 142. Has a structure.

In addition, in the present invention, when forming the dust sealing dam, as shown in FIG. 9A, in addition to the hot embossing method, the photoresist may be patterned by a photolithography method to form the dust sealing dam 174.

This structure is a region in which a dust sealing dam can be formed between the central region of the glass substrate 110 corresponding to the image detection region 220 of the semiconductor element 210 and the inner ends of the plurality of wirings 132. Applicable when it is secured as in 9b.

In the method of forming the dust sealing dam 174, a photoresist is formed on the front surface of the glass substrate 110 on which the wiring 132 and the solder bump 142 are formed, which is the same as the height of the solder bump 142. After the coating is applied to a thickness of 25 μm to form a photoresist layer, the photoresist layer may be etched by a well-known patterning method to form a square inside the plurality of wirings 132. FIG. 9B is a plan view of the unit glass substrate on which the dust sealing dam shown in FIG. 9A is formed.

In this case, instead of forming the liquid photoresist on the glass substrate 110 by a spin coating method, it is also possible to use a dry film.

In addition, the formation position of the dust sealing dam 174 is not only between the central region of the glass substrate 110 and the inner ends of the plurality of wirings 132, but also a part of the wiring 132 and the solder bumps as shown in FIG. 8. It is also possible to form the structure surrounding the 142.

The above method for forming a dust sealing dam by the hot embossing method uses a thermosetting polymer resin as the dam forming material and forms the dam forming stamp with a non-transparent material, but as described below, the polymerization reaction is performed by ultraviolet rays. The photocurable polymer resin may be used, and the substrate or the stamp may be formed by a transparent material, and may be formed by UV imprinting lithography that allows ultraviolet rays to be transmitted.

10A and 10B are cross-sectional views illustrating the principle of a dust sealing dam forming method using UV imprints, respectively.

That is, as shown in FIG. 10A, a photocurable polymer, eg, a photo, is formed on the front surface of the glass substrate 110 on which the wiring 132 and the solder bumps 142 are formed. After applying the resist layer 170a to a thickness of about 25 μm, the patterned photoresist is cured by irradiating with UV in a state in which a dam-forming stamp 320 made of a transparent material, for example, glass is pressed, and the dam is formed. When the forming stamp 320 is separated, the dust sealing dam 176 is obtained. 10A and 10B have been described with the wiring 132 and the solder bumps 142 omitted for convenience of description.

The above UV imprinting lithography method is described in more detail below.

A commercially available negative photoresist (negative type PR), which is a photocurable polymer, is uniformly coated on the substrate 110 by a spin coating method and then soft baked to form a photoresist layer 170a.

Subsequently, after the dam-forming stamp 320 formed with the grooves 315 corresponding to the shape of the dust sealing dam is formed in advance at a predetermined interval with glass, it is pressed onto the substrate in a state heated to a low temperature range of normal temperature to 80 degrees. As shown in FIG. 10B, the photoresist fills the recesses 315 of the dam forming stamp 320 and forms the photoresist layer 170a into a dam shape.

Subsequently, in the state where the photoresist layer 170a is pressed with the dam formation stamp 320, exposure, that is, ultraviolet rays, is irradiated. When the ultraviolet light is irradiated, the exposed portion of the negative photoresist layer 170a is cured. Thereafter, the dam forming stamp 320 is separated and a portion of the photoresist is removed by the ashing process to obtain a desired ring-shaped dust sealing dam 176.

Compared to the hot embossing method, since the UV imprinting lithography method is capable of exposing the resin to ultraviolet rays as the stamp is formed of a transparent material, the heating process is not required or is heated to a low temperature, thereby simplifying the processing process.

In the present invention, as described above, the dust sealing dam is previously formed on the glass substrate 110 by hot embossing, UV imprint lithography, or photolithography using a thermosetting or photocurable resin to detect an image of the semiconductor device 210. It is possible to form a dust sealing dam without causing a contamination problem in the region 220.

In the present invention, a glass substrate (ie, a glass wafer) is used to perform all pretreatment processes required for packaging, but any process is performed in advance on a semiconductor wafer in which a plurality of image sensing semiconductor elements 210 are integrated. I didn't lose. This provides the advantage of blocking the possibility of contamination on the semiconductor wafer in advance.

11A to 11C are cross-sectional views illustrating a bonding and dicing process of a glass wafer and a semiconductor wafer according to an embodiment of the present invention, respectively.

In the present invention, as shown in FIG. 11A, all processes necessary for packaging an image sensing semiconductor element chip (die) are performed on a glass wafer at the wafer level, and wafer bonding with the semiconductor wafer is performed. That is, a plurality of solders formed on the glass wafer 105 by aligning and matching the glass wafer 105 and the semiconductor wafer 205 on which the pretreatment process is performed, and then pressing at 50 to 500 N at a temperature of 150 to 180 ° C. The bumps 142 are bonded to the plurality of bump pads 215 of the semiconductor wafer 205, respectively, and the front ends of the plurality of dust sealing dams 172 are bonded to respective opposite surfaces of the semiconductor wafer 205.

When the wafer bonding (bonding) is performed, each of the dust sealing dams 172 forming an annular loop shape suitable for enclosing the ring shape, that is, the shape of the image detection region 220, is the unit glass substrate 110. ) To seal the image detection region 220 of the semiconductor device 210, that is, to hermetic sealing, and the Bi-Sn solder attached to the tip of the solder bump 142 is rippled. It is reflowed to have an effect of melt bonding the solder bumps 142 to the bump pads 215.

Thereafter, as illustrated in FIG. 11B, the glass wafer 105 and the semiconductor wafer 205 are polished to 200 μm so as to minimize the respective thicknesses of the glass wafer 105 and the semiconductor wafer 205, respectively.

Subsequently, as shown in FIG. 11C, the glass wafer 105 is half dicing along the plating electrode line 134, and in the case of the semiconductor wafer 205, the dust sealing dam 172 is used. Half dicing along a dicing key 117, which coincides with the outer periphery, yields a plurality of image sensor modules 100a, 100b, 100c.

In this case, the dicing key 117 is set so as to coincide with the outer circumferential portion of the dust sealing dam 172 with respect to the semiconductor wafer 205. It is to connect the FPCB used for.

As described above, in the present invention, a sealing dam is formed on a glass substrate (glass wafer) in advance by hot embossing, UV imprint lithography, or photolithography, and then the semiconductor wafer and the glass wafer at the wafer level. Since the bonding dam is made at the same time as the connection of each contact terminal when the compression bonding is made, it is possible to eliminate the dispensing process using a low viscosity epoxy that can cause the resin bleed problem as in the prior art .

On the other hand, in the above embodiment, after the sealing dam is formed in advance on the glass substrate (glass wafer), when the semiconductor wafer and the glass wafer are pressed by bonding at the wafer level, the bonding dam is simultaneously connected with each contact terminal. The manufacturing of the image sensor module was made through the assembly process.

However, the present invention is not limited to this, and as described below, after the sealing dam is formed in advance on the semiconductor wafer, the bonding between the semiconductor wafer and the glass wafer may be performed at the wafer level.

12A and 12B are plan views illustrating a CIS semiconductor device and a unit glass substrate before assembly into an image sensor module according to another embodiment of the present invention, respectively.

First, a process of forming the wiring 132 and the solder bumps 142 is performed on the glass substrate 110 (that is, the glass wafer), as shown in FIG. 12B, and the dam 172 for dust sealing is formed. The forming process does not proceed.

Instead, for the semiconductor element 210 (i.e., semiconductor wafer), for example, an image detection region 220 is formed at the center of each semiconductor element 210 of the wafer from a CMOS image sensor (CIS) manufacturer, and the peripheral portion thereof. After purchasing a semiconductor wafer having a plurality of bump pads 215 electrically connected to a plurality of cells of the image detection area 220, the dust sealing for enclosing the image detection area 220 in the center as shown in FIG. 12A. The dam 172 is formed by the photolithography method mentioned above.

Thereafter, as shown in FIGS. 11A to 11C, the semiconductor wafer and the glass wafer are pressed and bonded at the wafer level, and the dicing process is separated to obtain a plurality of image sensor modules 100a, 100b, and 100c.

As described above, in the present invention, the chip scale packaging (CSP) is processed in a wafer level chip scale packaging (WLCSP) method in which a dicing process for separating an assembly in a final process after processing all processes at the wafer level is performed. As a result, the assembly productivity is excellent, and slimming can be achieved.

In addition, the present invention eliminates the reflow soldering process by interconnecting the connection terminals by compression bonding the semiconductor wafer 205 and the glass wafer 105 at the wafer level, while simultaneously flipping each semiconductor element die on the unit substrate. Pick-flip-place operation using chip mounting equipment solves the problem of the connection accuracy of each terminal assembling individually and the process time due to individual assembly.

Furthermore, in the present invention, after processing all processes for the thick film semiconductor wafer 205 and the glass wafer 105 at the wafer level, the dicing process for separating the assembly in the final process is performed before the semiconductor dicing process Unnecessary thicknesses of the wafer 205 and the glass wafer 105 can be removed to easily thin the film, thereby easily minimizing the thickness of the assembled package finished product.

In the present invention, since the semiconductor wafer 205 and the glass wafer 105 are bonded to the sealing terminal 172 at the same time as the contact terminals, the assembling process can be simplified.

Furthermore, in the present invention, after the sealing dam is formed in advance on the glass wafer 105 by hot embossing, UV imprint lithography, or photolithography, the semiconductor wafer 205 and the glass wafer ( Since 105 is connected to the sealing dam 172 at the same time as the connection of the contact terminal, it is possible to eliminate the dispensing process using a low viscosity epoxy which may cause a resin bleed problem in the prior art.

An application method for configuring a camera module using the image sensor module of the present invention manufactured as described above will be described below.

13A to 13D are cross-sectional views illustrating camera modules according to the first to fourth embodiments manufactured using the image sensor module of the present invention, respectively.

As shown in FIG. 13A, the camera module according to the first exemplary embodiment of the present invention first includes a flexible film member, for example, an FPCB, for connecting the image sensor module 100 to an external circuit or an external device (eg, a mobile communication terminal). (Flexible PCB) 502 is used.

The FPCB 502 has a through hole 508 corresponding to the semiconductor element 210 at one end thereof, and a plurality of bonding pads connected to a plurality of wires embedded in a film around the through hole 508. (Not shown) has a structure in which a connector (not shown) is connected to the other end of the FPCB 502.

The plurality of bonding pads of the FPCB 502 are arranged to form a pattern corresponding to the exposed plurality of wires 132 of the image sensor module 100, and the electroplating method is performed on the plurality of bonding pads. Solder bumps 506 are formed, respectively.

In this case, a supporting plate 504 for supporting the FPCB 502 is attached to the lower portion of the FPCB 502, and a through hole corresponding to the through hole 508 of the FPCB 502 is formed.

In this state, the solder bumps 506 of the FPCB 502 are bonded to the exposed plurality of wires 132 of the image sensor module 100, and the upper side of the image sensor module 100, for example, a support ( 504, the lens assembly 400 is assembled.

The lens assembly 400 has a structure supported by the lens housing 402 such that the lens 406 is movable in the axial direction by the lens support 404. It is possible to use any well-known structure.

In this case, the lens assembly 400 is attached to the support plate 504 as shown, as well as the top of the glass wafer 105 using the pick-and-place equipment before dicing is performed. It may also be attached to the glass substrate 110 after being attached to the surface or dicing.

In the camera module according to the first embodiment of the present invention assembled as described above, an FPCB 502 coupled to the image sensor module 100 has a through hole 508 corresponding to the semiconductor element 210 at one end thereof. Solder bumps 506 are formed on the plurality of bonding pads disposed around the through-holes 508, so that the wiring of the image sensor module 100 can be performed without requiring an additional process to the image sensor module 100. 132) is easily combined with a compact structure.

The camera module according to the second embodiment of the present invention shown in FIG. 13B firstly connects the image sensor module 100 to an external device (for example, a mobile communication terminal). An anisotropic conductive film; 502a).

Similarly to the first embodiment, the anisotropic conductive film 502a is formed with a through hole 508 corresponding to the semiconductor element 210 at one end thereof, and is provided with a plurality of bonding pads disposed around the through hole 508. The conductive balls of the anisotropic conductive film 502a are formed.

In this case, a support plate 504 for supporting the anisotropic conductive film 502a is attached to the lower portion of the anisotropic conductive film 502a, and the through hole corresponding to the through hole 508 of the anisotropic conductive film 502a is formed. Formed.

In this state, when the bonding bonding of the anisotropic conductive film 502a to the bonding pads of the anisotropic conductive film 502a is connected to the exposed plurality of wires 132 of the image sensor module 100, the conductive balls are broken and the plurality of wires 132 and the film ( The bonding pad of 502a is connected, and then the lens assembly 400 is assembled onto the image sensor module 100.

In this case, as shown in the same manner as in the first embodiment, the lens assembly 400 is attached to the support plate 504 by the lens housing 402 and using pick-and-place equipment before dicing is performed. It is also possible to attach to the top surface of the glass wafer 105 or to the glass substrate 110 after dicing is performed.

The camera module according to the second embodiment of the present invention assembled as described above may be easily coupled with the wiring 132 of the image sensor module 100 without requiring an additional process for the image sensor module 100. .

The camera module according to the third embodiment of the present invention illustrated in FIG. 13C uses a general FPCB 502 for connecting the image sensor module 100 to an external device (eg, a mobile communication terminal).

Unlike the first embodiment, the FPCB 502 is attached to the lower surface of the semiconductor element 210 without forming a through hole 508 corresponding to the semiconductor element 210 at one end thereof, and is connected to the image sensor module 100. Wire bonding 506b is formed between the exposed plurality of wires 132 and the plurality of bonding pads of the FPCB 502.

Meanwhile, in the camera module according to the fourth embodiment of the present invention, as shown in FIG. 13D, only the sealing dam 172 is formed between the semiconductor element 210 and the glass substrate 110 as the image sensor module 100d. . In this case, since the size of the glass substrate 110 is the same as that of the sealing dam 172, the glass substrate 110 is made small and has a size smaller than that of the semiconductor device 210.

Therefore, the connection from the semiconductor element 210 to an external circuit or an external device (for example, a mobile communication terminal) forms solder bumps 142a on the plurality of bump pads 215 of the semiconductor element 210 and the FPCB (Flexible). Direct bonding with the PCB 502).

The manufacturing process of the camera module according to the fourth embodiment will be described in more detail below.

First, the sealing dam 172 is only formed on the glass substrate 110 by the above-described hot embossing method, UV imprint lithography method, or photolithography method, and then by compression bonding with the semiconductor element 210. An internal space surrounding the image detection region 220 is set between the glass substrate 110 and the semiconductor device 210 in a hermetic sealing state. This process can be done at the wafer level.

Thereafter, CMP polishing is performed to minimize the thickness of the glass wafer 105 and the semiconductor wafer 205 as shown in FIG. 11B, and the size of the glass substrate 110 is the same as that of the sealing dam 172. As a result, the plurality of bump pads 215 connected to the image detection region 220 of the semiconductor device 210 are exposed separately.

Subsequently, solder bumps 142a are formed on the exposed bump pads 215 of the semiconductor device 210 using solder balls, and the FPCBs 502 are directly bonded to the solder bumps 142a.

In this case, the FPCB 502 has a through hole 508a corresponding to the glass substrate 110 at one end thereof, and a plurality of bondings connected to a plurality of wires embedded in the film around the through hole 508a. Pads (not shown) are disposed.

In addition, a support plate 504 for supporting the FPCB 502 is attached to the lower portion of the FPCB 502, and the support plate 504 is formed with the same through hole as the through hole 508a of the FPCB 502. .

In this state, when the lens assembly 400 is assembled to the support plate 504, a camera module is obtained.

Also, in this case, the lens assembly 400 is attached to the support plate 504 as well as the lens housing 402 as shown in the first embodiment, as well as pick-and-place equipment before dicing is performed. It is also possible to attach to the upper surface of the glass wafer 105 by using or to be attached on the glass substrate 110 after dicing is made.

In the fourth embodiment, the sealing dam 172 is pre-formed on the glass substrate 110 and then compressed to the semiconductor device 210. However, the present invention is formed in the semiconductor device 210 by photolithography. After that, it is also possible to attach to the glass substrate 110 by mutual compression.

The image sensor module 100d used in the camera module of the fourth embodiment is a wafer level chip in which a chip scale packaging (CSP) processes all processes at the wafer level and a dicing process for separating an assembly in a final process is performed. As the packaging is made by the scale packaging (WLCSP) method, the assembly productivity is excellent and the slimming can be achieved.

In addition, the present invention eliminates the reflow soldering process by thermally compressing the semiconductor wafer and the glass wafer at the wafer level, and solves various problems in the conventional assembly of each semiconductor device die on the unit substrate.

Furthermore, in the present invention, the semiconductor dam and the glass wafer are bonded at the wafer level without causing a resin bleed problem, so that the sealing dam is bonded, so that the assembly process can be simplified. In addition, when the sealing dam is disposed to surround the plurality of bump pads and the plurality of bumps from the outside of the image detection area, a separate epoxy molding for protecting the separate bumps may be removed, thereby simplifying the process.

In the present invention, a simple process based on a simple structure and wafer level provides electrical and physical interconnection between the glass substrate and the semiconductor device and sealing of the image detection area, resulting in a very slim and packaged chip scale. The result is obtained.

An image sensor module, an image sensor module assembly, and a method of manufacturing the same capable of a wafer level-chip scale package (WLCSP) according to the present invention can be used in the field of photodetection semiconductors, in particular camera modules.

The present invention is applicable to areas where an image sensor such as a camcorder, a digital still camera, a PC camera, a mobile phone terminal camera, a PDA and a handheld camera, a security camera, a toy, an automobile device, a biometric, or the like is used.

1 is a cross-sectional view of an image sensor module according to the present invention.

2A to 2C are cross-sectional views for explaining a step of forming wiring on a unit glass substrate according to the present invention, respectively.

3A is a plan view of a glass wafer for explaining a step of forming wiring on a unit glass substrate.

FIG. 3B is an enlarged plan view of a unit glass substrate in FIG. 3A and is an enlarged plan view illustrating plating electrode lines when solder bumps are formed on an interconnect by an electroplating method.

3C is a plan view of a unit glass substrate on which wiring is formed.

4A to 4D are cross-sectional views illustrating a process of forming solder bumps on a unit glass substrate according to the present invention, respectively.

FIG. 5 is a plan view of a unit glass substrate on which wiring and solder bumps shown in FIG. 4D are formed.

6A to 6D are cross-sectional views illustrating a process of manufacturing a dam forming stamp used when forming a dust sealing dam by a hot embossing method according to an embodiment of the present invention.

7A to 7D are cross-sectional views illustrating a process of forming a dust sealing dam on a unit glass substrate according to an embodiment of the present invention, respectively.

FIG. 8 is a plan view of a unit glass substrate in which a dust sealing dam shown in FIG. 7D is formed.

9A is a cross-sectional view illustrating a process of forming a dust sealing dam on a unit glass substrate according to another embodiment of the present invention.

FIG. 9B is a plan view of the unit glass substrate on which the dust sealing dam shown in FIG. 9A is formed.

10A and 10B are cross-sectional views illustrating a method of forming a dust sealing dam using UV imprints, respectively.

11A to 11C are cross-sectional views illustrating a bonding and dicing process of a glass wafer and a CIS semiconductor wafer according to an embodiment of the present invention, respectively.

12A and 12B are plan views illustrating a CIS semiconductor device and a unit glass substrate before assembly into an image sensor module according to another embodiment of the present invention, respectively.

13A to 13D are cross-sectional views illustrating camera modules according to the first to fourth embodiments manufactured using the image sensor module of the present invention, respectively.

<Codes and explanations of the main parts of the drawings>

100-100d: image sensor module 105: glass wafer

110: glass substrate 120,122,122a, 302: photoresist pattern

124: contact window 130, 304: metal layer

132: wiring 132a: first region

132b: second region 134: plating electrode line

142,142a: solder bump 117: dicing key

170, 170a: photoresist layer 205: semiconductor wafer

210: semiconductor device for image sensing 215: bump pad

220: image detection area 300: silicon substrate

310,320: dam formation stamp 315: groove

400: lens assembly 402: lens housing

404: lens support 406: lens

502: FPCB 502a: ACF

504: support plate 506: solder bump

506a: wire bonding 508,508a: through hole

Claims (27)

Glass substrate 110; An image sensing semiconductor device (210) formed to face the glass substrate and facing away from the glass substrate and having an image detection region formed on a central surface thereof, and having a plurality of bump pads (215) disposed at a periphery thereof; A plurality of wires 132 extending outwardly from positions corresponding to the plurality of bump pads on the glass substrate, respectively; A plurality of solder bumps 142 formed on the plurality of wires at positions corresponding to the plurality of bump pads, respectively, for coupling the wires of the glass substrate and the semiconductor elements; And Sealing dams 172 and 174 surrounding the outer side of the image detection region 220 between the glass substrate and the semiconductor element in a closed loop shape to seal the image detection region, The plurality of wires may include a first metal film serving as an adhesive layer and a second metal film having excellent conductivity formed on the first metal film. The solder bumps consist of a wetting layer to the solder and lead-free solder, The sealing dam is previously formed on any one of the glass substrate and the semiconductor element, and then attached by mutual compression, and the semiconductor element is diced from the semiconductor wafer 205 to coincide with the outer circumferential portion of the sealing dam. Sensor module. delete delete delete The image sensor module of claim 1, wherein the sealing dam is made of a thermosetting resin or a photocurable resin. The image sensor module of claim 1, wherein the sealing dam is disposed between the image detection region and a plurality of bump pads of a semiconductor device. The image sensor module of claim 1, wherein the sealing dam is arranged to surround the plurality of bump pads and the plurality of bumps from the outside of the image detection area. Preparing a semiconductor wafer 205 having a plurality of image sensing semiconductor elements 210 each having an image detection region 220 formed on a central surface thereof and a plurality of bump pads 215 disposed on a periphery thereof; Preparing a glass wafer 105 having a plurality of unit glass substrates 110; Forming a plurality of wires 132 extending outwardly from positions corresponding to the plurality of bump pads, respectively, on the plurality of unit glass substrates; Selectively forming a plurality of solder bumps 142 at positions corresponding to the plurality of bump pads, respectively, on the plurality of wires; Forming a plurality of dust sealing dams (172,174) in a closed loop shape on any one of the unit glass substrate and the semiconductor element when the unit glass substrate and the semiconductor element are bonded to each other; Aligning a glass wafer against the semiconductor wafer such that the plurality of solder bumps coincide with the plurality of bump pads, and then compressing and bonding the glass wafers; Polishing the glass wafer and the semiconductor wafer to a predetermined thickness after the step of aligning the glass wafers against the semiconductor wafer and then pressing bonding them; And Dicing the semiconductor wafer 205 and the glass wafer 105 to separate the plurality of image sensor modules 100-100c having the semiconductor device 210 coupled to the unit glass substrate 110, respectively. Method of manufacturing an image sensor module, characterized in that. The method of claim 8, wherein the forming of the plurality of wires comprises: Forming a photoresist pattern on the glass wafer, the photoresist pattern forming a complementary pattern for the plurality of wirings; Forming a wiring metal layer on an entire surface of the glass wafer on which the photoresist pattern is formed; And And removing only the photoresist pattern by a lift-off method and leaving only the metal layer formed directly on each unit glass substrate as a wiring.  The method of claim 8, wherein the forming of the plurality of solder bumps comprises: Forming photoresist patterns on the glass wafer, each photoresist pattern having a plurality of contact windows at positions corresponding to the plurality of bump pads respectively on the plurality of wires; Selectively forming a plurality of solder bumps on the plurality of wires through the plurality of contact windows by electroplating; Planarizing an upper portion of the glass wafer to expose a tip of the solder bump while matching the heights of the plurality of solder bumps; And And removing the photoresist pattern.  The method of claim 10, wherein the plurality of wires are interconnected by plating electrode lines, and the plating electrode lines are used as cathode electrodes when the solder bumps are formed by electroplating.  The method of claim 10, wherein the plurality of solder bumps comprise a wetting layer for the solder and a lead-free solder. The method of claim 8, wherein the forming of the plurality of dust sealing dams A method of manufacturing an image sensor module, characterized in that it is formed for each of a plurality of unit glass substrates of a glass wafer by a hot embossing method using a thermosetting polymer resin or a UV imprinting lithography method using a photocurable polymer resin. The method of claim 13, wherein the forming of the plurality of dust sealing dams by the hot embossing method comprises: Forming a thermosetting polymer resin layer on the glass wafer on which a plurality of wirings and a plurality of solder bumps are formed for each of the plurality of unit glass substrates; Aligning and heating and pressing a dam-forming stamp having a complementary recess for the plurality of dust sealing dams on the glass wafer having the thermosetting polymer resin layer formed thereon; And Separating the dam forming stamp from the glass wafer and ashing a portion of the thermosetting polymer resin layer compressed to expose the solder bumps, a portion of the wiring, and a glass substrate. The method of claim 13, wherein the forming of the plurality of dust sealing dams by the UV imprinting lithography method comprises: Forming a photocurable polymer resin layer on the glass wafer on which a plurality of wirings and a plurality of solder bumps are formed for each of the plurality of unit glass substrates; Arranging and pressing a dam-forming stamp formed of a transparent material on the glass wafer having the photocurable polymer resin layer formed on a lower surface thereof with complementary recesses for the plurality of dust sealing dams; Curing the photocurable polymer resin layer by irradiating ultraviolet rays while pressing the photocurable polymer resin layer with the dam forming stamp; And Separating the dam forming stamp from the glass wafer and ashing a portion of the photocurable polymer resin layer pressed to expose the solder bumps, a portion of the wiring, and a glass substrate. The method of claim 8, wherein the forming of the plurality of dust sealing dams is performed for each unit glass substrate of the glass wafer by a photolithography method using a photocurable polymer resin. delete The method of claim 8, wherein the separating of the plurality of image sensor modules comprises: And dicing each semiconductor element from the semiconductor wafer so as to coincide with an outer circumferential portion of the sealing dam, and dicing a plurality of unit glass substrates along the plating electrode line of the glass wafer. Manufacturing method. 19. The method of claim 18, further comprising bonding a flexible film member to a plurality of exposed wires as the plurality of image sensor modules are separated. 20. The image sensor module of claim 19, wherein the flexible film member has a through hole corresponding to a semiconductor element, and a plurality of bonding pads corresponding to a plurality of wires exposed around the through hole. Manufacturing method. The method of claim 8, wherein the bonding of the glass wafer to the semiconductor wafer so that the plurality of solder bumps coincide with the plurality of bump pads, Aligning a glass wafer against the semiconductor wafer such that the plurality of solder bumps coincide with the plurality of bump pads; And Heating and compressing the glass wafer and the semiconductor wafer to melt-bond a plurality of solder bumps to the plurality of bump pads, respectively, and attaching front ends of the plurality of dust sealing dams to opposing surfaces of the unit glass substrate or the semiconductor device. Image sensor module manufacturing method characterized in that. Preparing a semiconductor wafer 205 having a plurality of image sensing semiconductor elements 210 each having an image detection region 220 formed on a central surface thereof and a plurality of bump pads 215 disposed on a periphery thereof; Forming a plurality of solder bumps (142a) on the plurality of bump pads, respectively; Preparing a glass wafer 105 having a plurality of unit glass substrates 110; Forming a plurality of dust sealing dams (172) in a closed loop shape on the unit glass substrate to seal the image detection region when the unit glass substrate and the semiconductor device are bonded to each other; Aligning and pressing the glass wafer so as to face the semiconductor wafer such that each of the plurality of dust sealing dams surrounds a corresponding image detection area; And Dicing the semiconductor wafer and the glass wafer to separate the plurality of image sensor modules 100d having unit glass substrates coupled to semiconductor devices, respectively. And forming the plurality of dust sealing dams (172) by any one of a hot embossing method, a UV imprinting lithography method, and a photolithography method. 23. The method of claim 22, wherein separating the plurality of image sensor modules comprises Dicing each semiconductor element from the semiconductor wafer, and dicing the unit glass substrate from the glass wafer to coincide with the outer circumferential portion of the sealing dam. delete 23. The method of claim 22, further comprising bonding a flexible film member to the plurality of solder bumps after separating the plurality of image sensor modules. delete delete

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