KR100955639B1 - Epitaxially coated semiconductor wafer and device and method for producing an epitaxially coated semiconductor wafer - Google Patents

Abstract

The present invention provides a method for manufacturing an epitaxially coated semiconductor wafer, wherein a gaseous material is placed such that the semiconductor wafer is positioned on the ring such that its backside faces the bottom of the susceptor having a gas permeable structure but is not in contact with the susceptor. Gas diffusion transfers from the region on the back side of the semiconductor wafer to the region on the back side of the susceptor, furthermore the semiconductor wafer contacts the ring only at the edge region of its back side, and by photoelastic stress measurement ("SIRD") Susceptors having a gas permeable structure and by applying an epitaxial layer on their polished facades by chemical vapor deposition at a temperature of 800 ° C. to 1200 ° C. in an epitaxial reactor so that no measurable stress occurs in the semiconductor wafer And disposed on the susceptor and acting as a thermal buffer between the susceptor and the supported semiconductor wafer. The plurality includes at least one of its polished surfaces, each supporting one of the semiconductor wafers prepared on the apparatus for supporting the semiconductor wafers during the deposition of a layer on the front face of the semiconductor wafer by chemical vapor deposition in an epitaxial reactor. A method for producing an epitaxially coated semiconductor wafer wherein a semiconductor wafer of is prepared and is coated successively separately.

Epitaxial coated semiconductor wafers, susceptors, rings, photoelastic stress measurements, epitaxial layers

Description

Epitaxially coated semiconductor wafers and epitaxially coated semiconductor wafers {{ITITAXIALLY COATED SEMICONDUCTOR WAFER AND DEVICE AND METHOD FOR PRODUCING AN EPITAXIALLY COATED SEMICONDUCTOR WAFER}

The present invention relates to a semiconductor wafer having a front side coated by chemical vapor deposition (CVD) and a method of manufacturing the semiconductor wafer. The invention also relates to an apparatus for supporting a semiconductor wafer during deposition of a layer on the front side of the semiconductor wafer by chemical vapor deposition (CVD).

During chemical vapor deposition, in particular the deposition of an epitaxial layer on a polished semiconductor wafer, two phenomena, in particular known under the terms "autodoping" and "halo", can occur.

In “auto doping”, the dopant is passed from the backside of the semiconductor wafer through the gas phase to the deposition gas, which is supplied onto the front of the semiconductor wafer. This dopant is then incorporated into the epitaxial layer mainly in the edge region of the front face of the semiconductor wafer, thus resulting in a somewhat noticeable undesirable radial deviation in the resistivity of the epitaxial layer.

"Halo" refers to the scattered light effect caused by the light scattering structure on the back side of the semiconductor wafer, and can be observed by illuminating a collimated light beam on the back side of the semiconductor wafer. This structure marks the transition on the surface of the back side of the semiconductor wafer in which the region with the native oxide layer is adjacent to the region where the oxide layer is absent or no longer present. These transitions occur upon removal of the native oxide layer during pretreatment in a hydrogen atmosphere (“pre-bake”) before the actual epitaxial deposition is incomplete. One possibility for quantifying this effect is, for example, KLA Tencor of so-called DNN ["DarkField Narrow Normal"] or DWN ["DarkField Wide Normal"]. It consists of scattered light measurement of haze (opacity, opacity) by the SP1 light scatterometer from the company.

To avoid the "auto doping" problem, US 6,129,047 proposes to provide a slit at the bottom of the recess ("pocket") of the susceptor holding the semiconductor wafer, which slit is on the outer edge of the bottom. Are arranged. Dopants that diffuse from the backside of the semiconductor wafer can be removed from the reactor without previously reaching the front of the semiconductor wafer by the flushing gas supplied on the backside of the wafer through slits in the susceptor.

According to US 6,596,095 B2 there is a small bore at the bottom of the susceptor for the same purpose. Here too, the dopant diffused from the back surface of the semiconductor wafer is transported and removed by supplying the flushing gas passing therethrough. These means are also effective for "halo" formation because they facilitate removal in the native oxide layer, which transports gaseous reaction products produced by dissolving the native oxides likewise through flow through the flushing gas and bottom through which flow passes. Because it becomes.

DE 1 032 884 2 discloses susceptors having a gas permeable structure having a porosity of at least 15% and a density of 0.5 g / cm ³ to 1.5 g / cm ³ . By using such a porous susceptor, the gaseous reaction product formed during the pretreatment by dissolving the native oxide layer and the dopant diffused from the semiconductor wafer to be coated can be discharged through the pores of the susceptor to the back of the susceptor, and by the flushing gas flow Can be taken out of the reactor. The use of the described susceptor also avoids the undesirable nanotopography effect on the backside of the semiconductor wafer that occurs in the case of susceptors with holes. The holes in the susceptor affect the temperature fields on the front and back of the semiconductor wafer to be coated, which leads to different local deposition rates and finally the nanotopography effect. The term nanotopography refers to a height deviation in the nanometer range measured over the lateral range of 0.5 mm to 10 mm.

Another problem in epitaxial coating of semiconductor wafers is that they involve stresses in epitaxially coated semiconductor wafers that can lead to dislocations and slips.

On the one hand, a number of methods are known for identifying slips in semiconductor wafers by visual inspection by collimating light, by devices for inspecting the surface of the semiconductor wafer, or by devices suitable for determining nanotopography.

However, the most sensitive method in this context is SIRD ("scanning infrared depolarization") because not only slip but also photoelastic stress can be measured by SIRD. SIRD methods for identifying stress fields, slips, slip lines, epitaxial defects based on the optical birefringence introduced are described, for example, in US Pat. No. 6,825,487 B2.

The thermally induced stress in the epitaxially coated semiconductor wafer is determined by epitaxial coating of the semiconductor wafer by reducing the temperature during the pretreatment step by adding hydrogen chloride (baking) and hydrogen chloride to the hydrogen atmosphere (HCL etching) and during the actual coating step. Can be avoided.

However, lower coating temperatures result in increased occurrence of undesirable crystal defects such as deposition defects or general epitaxial defects known by the terms "hillocks", "mounds" or "pits". Induce. At very low temperatures, polycrystalline growth may even occur. Another disadvantage is the degradation of the local planarization of the semiconductor wafer as well as the internal edge roll-off of the epitaxial layer (geometric shape, SFQR). Growth rate is further reduced at lower deposition temperatures, which makes the process less economical.

Thus, the reduction in pretreatment and deposition temperature is unacceptable due to the associated disadvantages.

The prior art does not present any solution approach to the reduction of stress, dislocations and slips in epitaxially coated semiconductor wafers due to the high pretreatment and deposition temperatures which are clearly necessary as described above.

Accordingly, it is an object of the present invention to provide a stress free epitaxially coated semiconductor wafer having good locality flatness as well as good edge roll off values while avoiding undesirable crystal defects, back halo, autodoping and nanotopography effects. .

This object is achieved by the present invention.

The present invention is an apparatus for supporting a semiconductor wafer during deposition of a layer on the front of the semiconductor wafer by chemical vapor deposition in an epitaxial reactor, the susceptor having a gas permeable structure and disposed on and supported by the susceptor A device comprising a ring acting as a thermal buffer between semiconductor wafers.

The susceptor preferably has a porosity (pore volume / total volume) of at least 15% and a density of 0.5 g / cm ³ to 1.5 g / cm ³ .

The required porosity and density of the susceptor can be obtained by suitable compression of the fiber or particles during the manufacture of the susceptor.

The susceptor preferably consists of graphite or graphite fibers.

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The device according to the invention comprises a ring disposed on the susceptor, which ring is preferably selected in terms of its thickness and in terms of its material properties to act as a thermal buffer between the susceptor and the supported semiconductor wafer. do.

The ring preferably has an inner diameter smaller than the diameter of the semiconductor wafer to be accommodated.

The outer diameter of the ring is preferably larger than the diameter of the semiconductor wafer to be accommodated, preferably corresponding to the diameter of the susceptor.

Particularly preferred is the outer diameter of the ring several mm larger than the diameter of the susceptor.

The ring is preferably at least 0.5 mm thick, particularly preferably 0.5 mm to 1.5 mm thick, even more preferably 1 mm thick.

The ring furthermore preferably also has an annular recess for receiving the semiconductor wafer.

The annular recess preferably has a depth of 0.3 mm to 0.7 mm, particularly preferably 0.5 mm, and a width of 3 mm to 15 mm, particularly preferably 6 mm.

The ring is preferably a ring of silicon carbide.

Preference is also given to the use of graphite rings coated with silicon carbide.

The ring is preferably made of a material having a thermal conductivity at 1000 ° C. of 5 W / mK to 100 W / mK, particularly preferably 5 W / mK to 50 W / mK, even more preferably 10 W / mK to 30 W / mK.

The apparatus according to the invention is preferably used in a single wafer reactor.

Particular preference is given to use in a single wafer reactor from ASM and Applied Materials (AMAT Centura Epi).

The apparatus according to the invention is preferably configured to accommodate semiconductor wafers with diameters of 150 mm, 200 mm, 300 mm and 450 mm.

SUMMARY OF THE INVENTION An object of the present invention is a method for manufacturing an epitaxially coated semiconductor wafer, wherein the semiconductor wafer is positioned on a ring such that its backside faces the bottom of a susceptor having a gas permeable structure but is not in contact with the susceptor. The material is transferred from the region on the back side of the semiconductor wafer to the region on the back side of the susceptor by gas diffusion, furthermore the semiconductor wafer contacts the ring only at the edge region of its back side, and the photoelastic stress measurement ("SIRD") By applying an epitaxial layer on their polished facades by chemical vapor deposition at a temperature of 800 ° C. to 1200 ° C. in an epitaxial reactor so that no measurable stress occurs on the semiconductor wafer, and having a gas permeable structure A thermal buffer between the susceptor and the semiconductor wafer disposed on and supported by the susceptor A method for producing an epitaxially coated semiconductor wafer, wherein each of the prepared semiconductor wafers is supported on an apparatus comprising a ring which acts on each other so that at least a plurality of semiconductor wafers polished at the front thereof are prepared and individually coated successively. Is also accomplished by.

In the method according to the invention, a plurality of semiconductor wafers, initially polished at least in front thereof, are initially prepared.

To this end, a single crystal, formed according to the prior art, preferably by means of a crucible obtained according to Czochralski, preferably has a wire saw with free abrasive ("slurry") or bonded abrasive (diamond wire). Sliced into a plurality of semiconductor wafers by known slicing methods.

Mechanical machining steps such as, for example, sequential single-sided grinding, simultaneous double-sided grinding (DDG) or lapping are also performed. Edges of semiconductor wafers, including any existing mechanical marking, such as notches or flats, are also generally machined ("edge notch grinding").

Also provided are chemical treatment steps, including washing and etching steps.

After the grinding, cleaning and etching steps, according to the prior art, the surface of the semiconductor wafer is preferably flattened by stock polishing. It is preferably " floating freely " between the lower polishing plate and the upper polishing plate covered by a polishing cloth while the semiconductor wafer at the end is loosely placed on a thin toothed disk and on the front and back surfaces. It is performed by double side polishing (DSP) which is polished at the same time.

The front face of the prepared semiconductor wafer is further preferably polished without stripes by a flexible polishing cloth, for example by an alkali polishing sol. In the art, this step is often referred to as CMP polishing ("chemical mechanical polishing").

After polishing, the semiconductor wafer is preferably subjected to hydrophilic cleaning and drying according to the prior art.

The epitaxial layer is then deposited on the polished front side of the semiconductor wafer prepared in a single wafer reactor.

In this case, the semiconductor wafer is not located directly on the susceptor, but on a ring disposed on the susceptor, so that the backside of the semiconductor wafer faces the bottom of the susceptor.

The bottom of the susceptor has a gas permeable structure.

The susceptor preferably has a porosity (pore volume / total volume) of at least 15% and a density of 0.5 g / cm ³ to 1.5 g / cm ³ .

The ring is located on this susceptor. Thus, the ring is not connected with the susceptor.

The ring is preferably selected in terms of its thickness and in terms of its material properties to act as a thermal buffer between the susceptor and the supported semiconductor wafer.

The ring is preferably at least 0.5 mm thick, particularly preferably 0.5 mm to 1.5 mm thick, even more preferably 1 mm thick.

The ring further preferably has an annular recess for receiving a semiconductor wafer.

The annular recess preferably has a depth of 0.3 mm to 0.7 mm, particularly preferably 0.5 mm, and a width of 3 mm to 15 mm, particularly preferably 6 mm.

The ring is preferably a ring of silicon carbide.

Preference is also given to the use of graphite rings coated with silicon carbide.

The ring is preferably made of a material having a thermal conductivity at 1000 ° C. of 5 W / mK to 100 W / mK, particularly preferably 5 W / mK to 50 W / mK, even more preferably 10 W / mK to 30 W / mK.

The epitaxial reactor is preferably a single wafer reactor, particularly preferably a single wafer reactor from ASM or AMAT Centura Epi.

The prepared semiconductor wafers preferably have diameters of 150 mm, 200 mm, 300 mm and 450 mm.

The inventors have also found that the effect of the susceptor described previously in the prior art with gas permeable structures (felt, pores, holes, slits, bores) on the properties of the backside of the semiconductor wafer with respect to halo and nanotopography also provides It has been found that it is maintained in the method according to the invention even when located on the ring and not directly on the susceptor.

This can be observed in advance during the pretreatment of the semiconductor wafer when the semiconductor wafer to be epitaxially coated is generally preheated in a hydrogen atmosphere and exposed to a flushing gas to remove the native oxide layer.

In addition to the gaseous reaction product formed when dissolving the oxide layer, the dopant diffused from the semiconductor wafer is discharged to the back of the susceptor through the gas permeable structure of the susceptor, ie by gas diffusion through the pores or openings of the susceptor where the flushing gas Is taken out of the reactor stream.

After the oxide layer is removed, an etchant, preferably hydrogen chloride, is added to the flushing gas to planarize the surface of the front face of the semiconductor wafer before depositing the epitaxial layer.

To deposit the epitaxial layer, the semiconductor wafer to be epitaxially coated is brought to the deposition temperature and the front side of the semiconductor wafer is in contact with the deposition gas, and the backside of the semiconductor wafer is preferably continuously exposed to the effect of the flushing gas.

Deposition gases include compounds that provide a material that forms a layer after they have been chemically separated. These materials preferably include dopants such as silicon, germanium and boron.

Particular preference is given to deposition gases consisting of trichlorosilane, hydrogen and diborane.

After the epitaxial layer is deposited, the epitaxially coated semiconductor wafer is cooled, for example, in the flow of hydrogen supplied through the reactor.

The effect of the ring located on the susceptor is that the semiconductor wafer does not contact the susceptor and therefore does not contain any stress points on its surface. Thus, a semiconductor wafer is stress free, ie it has no mechanical stress on its surface.

The ring made of silicon carbide further serves to form a kind of insulating or thermal buffer between the semiconductor wafer and the susceptor. This effect is that no thermally induced stress, which can induce dislocations and slips, occurs even at the support points at the edges.

For example, SIRD Metrology System from PVA TePla or SIRD-300 from JenaWave is suitable for the determination of stress. The sensitivity of Tepla's SIRD device is 6 kPa. Thus, stress-free semiconductor wafers within the scope of the present invention are intended to mean semiconductor wafers having no stress greater than 6 kPa. Both the front and back sides of the semiconductor wafer and also the edge regions can be studied with these SIRD measurement tools. There is no edge exclusion, for example as in the case of geometric measurement tools. Thus, unless otherwise indicated, data relating to stresses in semiconductor wafers studied by SIRD relate to the front and back and edge regions (without edge exclusion) of the semiconductor wafer, respectively.

Silicon carbide is also particularly suitable as ring material because it is hard and solid but not brittle (such as quartz, for example), and because it is relatively inexpensive and more readily processable. Silicon carbide is opaque (cloudy) and therefore does not induce light guiding effects.

The single wafer reactor used is heated from the top and bottom by an IR lamp.

This effect is that the semiconductor wafer is at a higher temperature than the susceptor during the pretreatment and coating steps when using conventional susceptors. Thus, thermally induced stresses occur at the point of contact with the susceptor, which in the worst case can induce dislocations and slip of the semiconductor wafer.

However, in the case of a susceptor having a ring, in particular a ring of silicon carbide, the temperature of the ring has a temperature value higher than the temperature of the susceptor and close to the temperature of the semiconductor wafer. Therefore, thermal stress occurring in the prior art can be avoided.

This effect also occurs when the temperature of the semiconductor wafer is lower than the temperature of the susceptor, such as when cooling the semiconductor wafer after the deposition process. Here too, the ring acts as a kind of thermal buffer.

Another advantage of the method according to the invention and the device according to the invention is that the ring can be machined very accurately, especially with regard to its dimensions and its roughness. Thus, the adaptation of the device according to the invention to the semiconductor wafer can be improved, which can also make it possible to avoid the mechanical stress field at the support point of the semiconductor wafer.

According to the invention, the ring is located directly on the susceptor. However, it is not desirable to maintain the ring on the susceptor surface by a few millimeters above the alternative, ie by the spacer, because gas diffused from the heavily doped semiconductor wafer on the back side laterally exits the ring and Thus the "auto doping" effect can be reduced, on the other hand the thermal equilibrium effect can nevertheless be reduced due to the increased distance of the ring (and thus the semiconductor wafer) from the susceptor and in terms of thermal induced stress and slip This is because the sensitivity at can be increased. Since the deposition gas may further enter between the ring and the susceptor, the wafer backside may also be coated, which is undesirable.

Conversely, in the method according to the invention, since the deposition gas cannot enter between the susceptor and the semiconductor wafer and thus cannot reach the backside of the semiconductor wafer, the ring is firmly positioned so that any backside deposition is avoided.

The semiconductor wafer to be epitaxially coated is preferably a wafer of single crystal silicon on which an epitaxial silicon layer is applied.

The semiconductor wafer to be epitaxially coated is preferably polished on its front face.

Preferably, the semiconductor wafer to be epitaxially coated is etched and polished on its backside.

Preferably, the semiconductor wafer to be epitaxially coated has a diameter of 150 mm, 200 mm, 300 mm or 450 mm.

Another advantage of the method according to the invention is that the process window can be extended in relation to the deposition temperature.

In general, p− silicon wafers (silicon wafers with low doping levels) are more sensitive to stress than p + silicon wafers with higher doping levels.

Thus, the temperature for depositing the epitaxial layer on the p + silicon wafer can be chosen higher compared to the p− silicon wafer.

Typical deposition temperatures according to the prior art (single wafer reactor) are as follows.

p− / p + (lightly doped epitaxial layer on heavily doped silicon wafer): 1120 ° C. to 1150 ° C.

p- / p- (lightly doped epitaxial layer on lightly doped silicon wafer): 1080 ° C to 1120 ° C.

Conversely, in the process according to the invention, the temperature range can preferably be increased by about 20 ° C. to 30 ° C. (ie up to 1180 ° C. for p− / p + and up to 1150 ° C. for p− / p−). ), A stress free epitaxially coated silicon wafer is obtained according to SIRD with reduced defects and increased geometry compared to the prior art.

Therefore, the deposition temperature in the scope of the present invention is preferably selected as follows.

In silicon wafers with high doping levels (p +), epitaxial deposition is performed at temperatures of 1140 ° C to 1180 ° C.

In silicon wafers with a low doping level (p−), deposition is performed at temperatures of 1100 ° C. to 1150 ° C.

Another advantage of the elevated deposition temperature is that the edge roll of the polished semiconductor wafer is because the layer thickness profile of the epitaxial layer at the edge of the semiconductor wafer is increased by the elevated deposition temperature and the edge roll off can be compensated thereby. Off can be improved accordingly.

The method described in accordance with the present invention is a semiconductor wafer comprising a front side and a back side, further comprising a stress-free epitaxial layer according to the photoelastic stress measurement ("SIRD") at the front side, further having an area of 2 mm x 2 mm. Semiconductor wafers with nanotopography on the back expressed as PV height deviations (= peak to valley) of greater than or equal to 2 nm and less than or equal to 5 nm based on a square measurement window and back "halo" represented as haze of greater than or equal to 0.1 ppm and less than or equal to 5 ppm It is suitable for manufacturing.

The semiconductor wafer according to the present invention does not have a stress due to the specification by SIRD.

It furthermore has good nanotopography and haze values on its backside.

The semiconductor wafer according to the invention on the one hand does not have a stress point on its surface and is thus stress-free, ie there is no mechanical or thermally induced stress on its surface.

By using a ring of silicon carbide in the method according to the invention which can be treated very well as described above (particularly in relation to its roughness), the semiconductor wafer on the susceptor (in the prior art) The mechanical stress field (at the point of support) can further be avoided.

Thus, the semiconductor wafer according to the invention is preferably free of any stresses due to the characterization by photoelastic stress measurement (SIRD) in the edge region as well as both its front and back surfaces.

Crystal defects called LPDs (“light spot defects”) due to the measurement method used can be detected by light scattering as LLS (“local light scatterers”) by surface inspection tools, for example KLA Tencor Surfscan SP1. Common structural epitaxial defects and epi lamination defects, hillock or pits.

The study of the semiconductor wafer according to the present invention shows the following results, which were respectively measured in the dark field, the tilt mode (DWO, DNO) (the tilt angle of the laser of SP1).

Combined size group 50% of wafer 97.7% of wafers ≥50nm ≤2 defect ≤8 fault ≥90nm 0 defect ≤4 defect ≥120nm 0 defect ≤3 defect ≥200nm 0 defect ≤2 defect

For a yield of ≧ 97.7% (economically acceptable ≧ 90%), this means 8 LLS defects ≧ 50 nm, 4 LLS defects ≧ 90 nm, 3 LLS defects ≧ 120 nm, 2 LLS defects ≧ 200 nm.

For the local planarization of the semiconductor wafer according to the present invention, the following results were found.

The semiconductor wafer preferably has a maximum local planarization value SFQR _max of 0.025 μm or more and 0.04 μm or less.

The maximum local planarization value (SFQR _max ) of 0.025 μm to 0.04 μm is preferably at least 99 of the subregions of the two-dimensional grid of the measurement window having a size of 26 × 8 mm ² on the front side of the coated semiconductor wafer and an edge exclusion of 2 mm. Based on%.

Comparison with a semiconductor wafer epitaxially coated on a standard susceptor (according to the prior art, ie without a ring support) represents a significant improvement by the semiconductor wafer according to the invention. Under the same process conditions, but comparative tests by using standard susceptors instead of the device according to the invention provide a maximum local planarization value (SFQR _max ) of 0.045 μm to 0.08 μm for epitaxially coated semiconductor wafers.

The semiconductor wafer according to the invention furthermore preferably has an R 3 O − of −10 nm to +10 nm corresponding to the deviation measured at a distance of 1 mm from the edge of the silicon wafer of the average cross section determined by thickness measurement from the baseline determined by regression. Has a 1mm parameter. This is an edge roll off parameter.

The epitaxially coated semiconductor wafer preferably has an R3O-1 mm parameter of -5 nm to +5 nm.

A negative R3O-1mm value corresponds to roll-up, ie in this case the edge rolloff of the semiconductor wafer is overcompensated by epitaxial coating.

A method for measuring edge roll off of silicon wafers is described in Jpn. J. Appl. Phys. Vol. 38 (1999), pages 38-39. Edge roll-off parameters related to the thickness of the silicon wafer are, for example, KLA by initially calculating 360 radial cross sections at intervals of 1 ° of the entire image (topography, "wafer map") starting at the center of the wafer. It can be determined by the NanoPro NP1 topography measurement system from Tencor. The cross section is typically divided into four sectors S2 to S5 (90 ° sectors each) and all 90 radial cross sections are averaged for each sector. In an area with a distance of R-5mm to R-35mm from the edge of the wafer, a third order suitable baseline (“best fit”) is calculated. Finally, the quadratic symmetry of the edge roll-off is averaged (by averaging over all radial thickness cross-sections) and, for example, with the baseline determined by the regression at a distance of R-1 mm from the edge of the wafer. Obtained by determining the deviation between the averaged radial cross sections.

The deviation between the average radial cross section and the baseline per sector (individual track) may also be considered as an alternative to obtain a roll off value for each sector. In the scope of the present invention, an average roll off value is considered.

The semiconductor wafer according to the present invention more preferably has resistance uniformity in the epitaxial layer of ± 2% or more and ± 5% or less.

The μPCD lifetime is preferably 2500 kPa to 3000 kPa. This is a minority carrier or recombination lifetime (μPCD = micro photoconductive attenuation) and is determined by measurement of phototechnical excitation and subsequent attenuation curves.

The semiconductor wafer is preferably a semiconductor wafer polished on the front face and has an epitaxial layer on the polished front face.

Preferably, the semiconductor wafer is etched and polished on its backside.

Preferably, the semiconductor wafer has a diameter of 150 mm, 200 mm, 300 mm or 450 mm.

The epitaxially coated semiconductor wafer is preferably a wafer of single crystal silicon on which an epitaxial silicon layer is applied.

According to the present invention, there is provided a stress free epitaxially coated semiconductor wafer having good localized flatness as well as good edge roll off values while avoiding undesirable crystal defects, back halo, autodoping and nanotopography effects.

The invention will be explained below with reference to the drawings.

1 schematically shows the structure of a device according to the invention. Ring 2 is disposed on susceptor 1. The ring 2 and susceptor 1 are sized to receive the substrate 3. The ring 2 includes a recess 2a in the edge region to receive the substrate 3.

2 shows the results of SIRD measurements of epitaxially coated semiconductor wafers according to the prior art. Here, the local stress field may appear at the surface of the semiconductor wafer with a stress difference of up to 600 kPa. The stress field may also appear at the edges, which corresponds to stress differences of 13 kPa to 45 kPa.

The interface pattern indicates that there is no thickness variation in the wafer. "Fringes" are created by interference of normal and abnormal rays, each having a different propagation velocity.

3 shows the results of SIRD measurements on semiconductor wafers according to the present invention. The semiconductor wafer does not have any stress field measurable by SIRD on both the surface and the edge.

Support points of the semiconductor wafer on the support device of the SIRD measurement tool may appear at the edges. Thus, they are not due to the method according to the invention, i.e. they do not correspond to the stress field as in the prior art which can result from the support point of the semiconductor wafer on the susceptor. No stress field can be detected by SIRD. Therefore, the semiconductor wafer does not have a stress field having a stress difference of 6 kPa or more.

Finally, FIG. 4 shows the meaning of the support points visualized in FIG. 3. Three support points may appear, which are generated by the semiconductor wafer supported on the support device of the SIRD tool. Other points may further appear, which may be due to mechanical markings such as notches or flats, or laser markings.

These support points and the mechanical markings that can be provided can appear in any SIRD measurement on the semiconductor wafer. However, they are not critical stress fields that can be detected quantitatively by SIRD.

1 shows an apparatus according to the invention.

2 is a diagram showing a result of a SIRD measurement (prior art).

3 shows the results of SIRD measurements of semiconductor wafers according to the present invention;

Fig. 4 is a diagram for explaining the meaning of the supporting point visualized at the edge in SIRD measurement.

<Explanation of symbols for the main parts of the drawings>

1: susceptor

2: ring

2a: recessed

3: substrate

Claims (21)

delete delete delete delete delete delete delete delete delete delete delete A method for manufacturing an epitaxially coated semiconductor wafer, From the region on the backside of the semiconductor wafer by gas diffusion the gaseous material is positioned so that the backside of the semiconductor wafer faces the bottom of the susceptor having a gas permeable structure but is not in contact with the susceptor. Is transferred through the susceptor to the area on the back side of the susceptor, furthermore the semiconductor wafer is in contact with the ring only at the edge area of its back side, and furthermore the stress measurable by photoelastic stress measurement ("SIRD") One of the semiconductor wafers prepared on the apparatus for supporting the semiconductor wafer by applying an epitaxial layer on their polished front surface by chemical vapor deposition at a temperature of 800 ° C to 1200 ° C in an epitaxial reactor so as not to A plurality of semiconductor ways, each of which is polished at least in front thereof Are prepared and coated separately as a continuous, The apparatus for supporting the semiconductor wafer includes a susceptor having a gas permeable structure and a ring disposed on the susceptor to act as a thermal buffer between the susceptor and the supported semiconductor wafer, the susceptor being graphite Or made of graphite fiber, wherein the ring disposed on the susceptor is made of silicon carbide. 13. The method of claim 12, wherein the prepared semiconductor wafer is a wafer of single crystal silicon. The method of claim 12, wherein a deposition temperature of 1140 ° C. to 1180 ° C. is selected for epitaxial coating of the p + doped silicon wafer. The method of claim 12, wherein a deposition temperature of 1100 ° C. to 1150 ° C. is selected for epitaxial coating of the p-doped silicon wafer. A semiconductor wafer comprising a front face and a back face, further comprising a stress free epitaxial layer according to the photoelastic stress measurement ("SIRD") on the front face of the semiconductor wafer, and further based on a square measurement window having an area of 2 mm x 2 mm. A semiconductor wafer having a nanotopography on the back side of the semiconductor wafer expressed as PV height deviation (= peak to valley) of 2 nm or more and 5 nm or less and a backside "halo" expressed as a haze of 0.1 ppm or more and 5 ppm or less. 17. An edge roll-off parameter of -10 nm to +10 nm corresponding to a deviation measured at a distance of 1 mm from an edge of a silicon wafer of an average cross section determined by thickness measurement from a baseline determined by regression. Semiconductor wafer. The semiconductor wafer according to claim 16, wherein a maximum local planarization value (SFQR _max ) of 0.025 μm or more and 0.04 μm or less. The semiconductor wafer according to claim 16, wherein the semiconductor wafer has resistance uniformity of the epitaxial layer of ± 2% or more and ± 5% or less. The semiconductor wafer of claim 16, wherein the semiconductor wafer has a recombination lifetime by μPCD of 2500 kV to 3000 kV. 17. The semiconductor wafer according to claim 16, wherein the epitaxial silicon layer having a diameter of 150 mm, 200 mm, 300 mm or 450 mm is a wafer of single crystal silicon, which is applied on top.

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