KR100943139B1 - Voltage supplier for bitline sensing of non volatile memory device - Google Patents

Abstract

The bit line sensing unit of the present invention is a temperature voltage output unit for supplying a temperature voltage that increases in proportion to the magnitude of the external temperature, a comparison unit for comparing the magnitude of the temperature voltage and the reference voltage, and the output voltage of the comparison unit And a pull-up part for supplying a high voltage which increases proportionally, and a voltage divider for distributing the high voltage to supply a first voltage and a second voltage to an output terminal.

In addition, the bit line sensing unit of the present invention, a temperature voltage output unit for supplying a temperature voltage that decreases in proportion to the magnitude of the external temperature, a comparison unit for comparing the magnitude of the temperature voltage and the reference voltage, the magnitude of the output voltage of the comparison unit A pull-up part for supplying power voltages having different levels according to the power supply, a pull-up part for supplying a high voltage which decreases in proportion to the magnitude of the output voltage of the comparator, and supplying the first voltage and the second voltage to the output terminal by dividing the high voltage. It characterized in that it comprises a voltage divider.

Threshold Voltage, Temperature, Sensing Voltage

Description

Voltage supplier for bitline sensing of non volatile memory device

The present invention relates to a bit line sensing voltage supply unit of a nonvolatile memory device.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory cell is an electric program / eraseable device that performs program and erase operations by changing a threshold voltage of a cell while electrons are moved by a strong electric field applied to a thin oxide film.

The nonvolatile memory device typically includes a memory cell array having cells in which data is stored in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in a specific cell. . The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling the connection of the specific bit line and the sensing node.

The read operation / verify operation of the nonvolatile memory device determines whether the threshold voltage of the cell to be read is greater than or equal to the read voltage / verify voltage. To this end, a process of precharging the bit line to a high level is required. A bit line sensing unit, a sensing node precharge unit, and the like, which selectively connect the bit line and the sensing node, are used. Next, the voltage level of the bit line is different depending on whether or not a specific cell is programmed. In this case, the difference can be measured using the bit line sensing unit. However, since the bit line sensing unit includes an NMOS transistor, the threshold voltage value of the transistor may be different according to temperature, and thus the read / verify result is different according to the temperature change.

The problem to be solved by the present invention according to the above problem is to apply a voltage applied to the bit line sensing unit differently according to the temperature change, to improve the problem appearing during the read / verify operation according to the temperature change.

The bit line sensing unit of the present invention for solving the above-mentioned problem, a temperature voltage output unit for supplying a temperature voltage that increases in proportion to the magnitude of the external temperature, a comparison unit for comparing the magnitude of the temperature voltage and the reference voltage, and And a pull-up part for supplying a high voltage increasing in proportion to the magnitude of the output voltage of the comparator, and a voltage divider for distributing the high voltage to supply the first voltage and the second voltage to the output terminal.

In addition, the bit line sensing unit of the present invention, a temperature voltage output unit for supplying a temperature voltage that decreases in proportion to the magnitude of the external temperature, a comparison unit for comparing the magnitude of the temperature voltage and the reference voltage, the magnitude of the output voltage of the comparison unit A pull-up part for supplying power voltages having different levels according to the power supply, a pull-up part for supplying a high voltage which decreases in proportion to the magnitude of the output voltage of the comparator, and supplying the first voltage and the second voltage to the output terminal by dividing the high voltage. It characterized in that it comprises a voltage divider.

In addition, the nonvolatile memory device of the present invention includes a bit line sensing unit for selectively connecting a sensing node and a bit line according to a bit line sensing signal, and a bit line sensing for changing a voltage level of the bit line sensing signal in proportion to a temperature change. It characterized in that it comprises a voltage supply.

According to the above-described configuration of the present invention, when the temperature is higher than room temperature, a bit line sensing voltage higher than room temperature may be applied, and when the temperature is lower than room temperature, bit line sensing voltage lower than room temperature may be applied. In this way, by applying different bit line sensing voltages in consideration of the temperature change, a problem in the read / verify operation according to the temperature change can be solved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

FIG. 1A is a diagram illustrating a nonvolatile memory device applied to the present invention, and FIG. 1B is a diagram for describing a concept of a conventional read / verify operation of the nonvolatile memory device.

The nonvolatile memory device 100 includes a cell string 110, a bit line sensing unit 120, a sensing node precharge unit 130, and a bit line sensing voltage supply unit 140.

The cell string 110 may include a plurality of memory cells MC0 to MCn connected in series, a drain select transistor DST to selectively connect the memory cell MCn to the bit line sensing unit 120, and the memory. And a source select transistor SST for selectively connecting the cell MC0 to ground.

The bit line sensing unit 120 selectively connects the sensing node SO and the cell string according to the bit line sensing signal PBSENSE. To this end, it includes an NMOS transistor (N120) connected between the sensing node and the cell string. In particular, by adjusting the voltage level of the bit line sensing signal (PBSENSE), it is possible to read whether a specific cell is programmed above the read voltage or the verify voltage (Vread, Vver).

The sensing node precharge unit 130 applies a power supply voltage VDD to the sensing node according to the sensing node precharge signal PRECHb. To this end, it includes a PMOS transistor (P130) connected between the power supply voltage terminal and the sensing node.

The bit line sensing voltage supply unit 140 supplies a bit line sensing voltage PBSENSE that varies differently according to temperature change. The detailed configuration will be described later.

The principle of the read operation / verification operation will be described with reference to FIG. 1B.

(1) T1 section

First, the sensing node SO is precharged to a high level by applying a low level sensing node precharge signal PRECHb. In addition, the bit line sensing signal PBSENSE of the first voltage V1 is applied to precharge the bit line VBL to the high level V1 -Vth.

(2) T2 section

Next, the application of the bit line sensing signal PBSENSE is stopped so that the voltage level of the bit line is maintained or discharged according to the state of the cell to be read. To this end, a pass voltage Vpass is applied to word lines of cells other than the cell to be read to turn on all of the corresponding cells. In addition, a read voltage or a verify voltage Vread or Vver is applied to the word line of the cell to be read. If the threshold voltage of the cell to be read is greater than the read voltage or the verify voltages Vread and Vver, the cell is not turned on and maintains the precharged high level voltages V1 -Vth. However, if the threshold voltage of the cell to be read is less than the read voltage or the verification voltage (Vread, Vver), the cell is turned on and the precharged voltage is discharged to ground through the cell string.

(3) T3 section

Next, the bit line sensing signal PBSENSE of the second voltage V2 is applied to sense the voltage level of the bit line VBL. Meanwhile, at this time, the sensing node is stopped by floating the sensing node precharge operation.

If the voltage level of the bit line is discharged because the threshold voltage of the read target cell is lower than the read voltage or the verify voltage Vread and Vver, the NMOS is applied according to the application of the bit line sensing signal PBSENSE of the second voltage V2. The transistor N120 is turned on so that the sensing node SO is also discharged to the low level. This is because the difference between the gate voltage V2 and the source voltage 0V of the NMOS transistor N120 is greater than the threshold voltage Vth.

On the other hand, if the threshold voltage of the read target cell is higher than the read voltage or the verify voltages Vread and Vver, and the voltage level of the bit line is maintained at the high level (V1-Vth), the bit line of the second voltage V2. Even when the sensing signal PBSENSE is applied, the NMOS transistor N120 is turned off so that the sensing node SO is discharged to a low level. This is because the difference between the gate voltage V2 and the source voltages V1-Vth of the NMOS transistor N120 is smaller than the threshold voltage Vth. In this case, the second voltage V2 and the first voltage V1 are set such that a difference between the gate voltage V2 and the source voltages V1 -Vth is smaller than the threshold voltage Vth.

In this case, the voltage level VBL of the bit line may be different according to the temperature change, and thus the results of the read operation and the verify operation may be different.

FIG. 2 is a diagram illustrating a problem caused by temperature change in a read / verify operation of a conventional nonvolatile memory device.

That is, when the same bit line sensing voltage is applied to the gate, the lower the temperature, the greater the amount of charge Cbl precharged to the bit line. Accordingly, even when the threshold voltage is lower than the read voltage / verify voltage, the degree of discharge is higher than the voltage obtained by subtracting the threshold voltage from the second voltage V2, so that the cell is not read to the erased cell. In the case of high temperature, the amount of charges Cbl precharged to the bit line is small, so that cells when the threshold voltage is higher than the read voltage / verify voltage may be read into the erased cell.

3 is a graph illustrating a change in cell current according to temperature change.

The X axis represents the voltage applied to the gate of the NMOS transistor N120, and the Y axis represents the bit line current Idsat flowing through the NMOS transistor N120. It can be seen that the characteristics are different from the ZTC (zero temperature coefficient, 1.05V). That is, when a gate voltage lower than ZTC is applied, the bit line current Idsat value increases as the temperature increases, whereas when a gate voltage higher than ZTC is applied, the bit line current value Idsat increases as the temperature is lower. It shows increasing characteristics. Typically, since the first voltage V1 applied in the read / verify operation is 1.8 V and larger than ZTC, the characteristic that the bit line current value increases as the temperature is lower becomes a problem in the read / verify operation.

4 is a graph illustrating a change in temperature of a bit line current value appearing when a specific voltage is applied to the bit line sensing unit.

When the first voltage V1 of 1.8V is applied to the bit line sensing unit, the bit line current Idsat increases as the temperature is lowered. That is, 119 uA at low temperature (-40 degreeC), 104 uA at normal temperature (25 degreeC), and 91.2 uA at high temperature (90 degreeC) can be seen that a flow. In summary, when the same gate voltage is applied to the bit line sensing unit 120, the bit line current Idsat increases as the temperature decreases. Therefore, there is a need to reduce this change tendency. On the other hand, the numerical value is only for explaining the tendency of the change in the current value with the temperature change, it does not limit the scope of the present invention.

5 is a graph showing characteristics to be used in the present invention in order to minimize the change in temperature of the bit line current value.

It is not to apply the same voltage irrespective of temperature, but to minimize the change in temperature of the bit line current value by applying different gate voltages depending on the temperature. Using the characteristics of the graphs of FIGS. 3 and 4, it can be seen that in order to supply the same bit line current according to temperature, a higher gate voltage should be applied as the external temperature increases. For example, when 1.7V at low temperature (-40 ° C), 1.8V at room temperature (25 ° C) and 1.9V at high temperature (90 ° C) are applied as the gate voltage, the same value of bit line current Idsat You can see the flow.

Therefore, the present invention is to solve the problem of the read / verify operation according to the temperature change by applying the gate voltage increases with the increase in the external temperature.

6 is a circuit diagram illustrating a bit line sensing voltage supply unit of a nonvolatile memory device according to an exemplary embodiment of the present invention.

The bit line sensing voltage supply unit 600 includes a temperature voltage output unit 610, a comparison unit 620, a pull-up unit 630, a voltage divider unit 640, a first voltage V1 supply unit 650, and a second unit. The voltage V2 supply unit 660, a programming voltage supply unit 670, and an erasing voltage supply unit 680 are included.

The temperature voltage output unit 610 may include a pull-up device P612 for supplying a power voltage according to a control signal CON, a first resistor RA and a diode connection connected in series between the pull-up device P612 and a ground terminal. And a first NMOS transistor N610, a second resistor RB and a second NMOS transistor N612 connected in series between the pull-up element P612 and the ground terminal. In this case, the gate of the NMOS transistor N612 is connected to the connection node N1 of the first resistor RA and the NMOS transistor N610. Meanwhile, the temperature sensitivity of the first NMOS transistor N610 is set to be greater than that of the second NMOS transistor N612. This can be adjusted by changing the channel width of each NMOS transistor.

When the temperature is high, that is, when the temperature is higher than room temperature, the threshold voltage Vth of the diode-connected first NMOS transistor N610 is decreased, and thus the voltage of the connection node N1 is decreased. As the gate voltage N1 of the second NMOS transistor N612 decreases, the temperature voltage Vtemp output from the connection node of the second NMOS transistor N612 and the second resistor RB increases.

When the temperature is lower, that is, when the temperature is lower than room temperature, the threshold voltage Vth of the diode-connected first NMOS transistor N610 increases, so that the voltage of the connection node N1 increases. As the gate voltage N1 of the second NMOS transistor N612 increases, the temperature voltage Vtemp output from the connection node of the second NMOS transistor N612 and the second resistor RB decreases. In summary, the temperature voltage output unit Vtemp outputs the temperature voltage Vtemp that changes in proportion to the temperature increase.

The comparator 620 controls the magnitude of the voltage output by the pull-up unit 630 by comparing the temperature voltage Vtemp and the reference voltage Vref output from the voltage divider 640. The comparison unit 620 is configured in the form of a differential amplifier.

The driving device N626 for applying a ground voltage to the node N3 according to the enable signal EN, the first NMOS transistor N622 connected to a source of the node N3 and turned on according to the temperature voltage Vtemp. And a second NMOS transistor N624 connected to a source of the node N3 and turned on according to a reference voltage Vref, a first voltage connected between a power supply voltage VDD terminal and a drain of the first NMOS transistor. A PMOS transistor P622 includes a second PMOS transistor P624 connected between the power supply voltage VDD terminal and the drain of the second NMOS transistor. In this case, gates of the first and second PMOS transistors are connected to drain terminals of the first NMOS transistor. The output voltage Vout is a voltage applied to the connection node N2 of the second PMOS transistor P624 and the second NMOS transistor N624. Therefore, the comparison unit 620 outputs a high level output voltage Vout when the temperature voltage Vtemp is greater than the reference voltage Vref, and when the temperature voltage Vtemp is smaller than the reference voltage Vref. Output the low level output voltage (Vout).

The pull-up unit 630 includes an NMOS transistor N630 that is turned on in response to the output voltage of the comparator 620 and is connected between a power supply voltage terminal and the voltage divider 640.

The voltage divider 640 includes first to fourth resistors R1, R2, R3, and R4 connected in series between the pull-up unit 630 and a ground terminal. The voltage applied to the connection node of the first resistor R1 and the second resistor R2 is used as the first voltage V1 and the voltage applied to the connection node of the third resistor R3 and the fourth resistor R4. This second voltage V2 is used. Meanwhile, a voltage applied to the connection node of the second resistor R2 and the third resistor R3 is used as the reference voltage Vref applied to the comparator 620. The magnitudes of the first voltage V1 and the second voltage V2 may be adjusted by adjusting the sizes of the resistors R1 to R4. The level of the first and second voltages and the reference voltage are different depending on the magnitude of the voltage supplied from the pull-up unit 630.

Now, the relationship between the change of the temperature voltage Vtemp according to the temperature and the magnitude change of the first voltage V1 and the second voltage V2 will be described.

When the temperature is high and the temperature voltage Vtemp is high, the current I1 flowing through the first NMOS transistor N622 increases. Due to the characteristics of the differential amplifier, the output voltage Vout is increased to increase the voltage delivered to the pull-up unit 630, thereby increasing the levels of the first and second voltages and the reference voltage Vref. The level of the first and second voltages is increased by a feedback operation until the level of the reference voltage Vref is approximately equal to the temperature voltage.

On the other hand, when the temperature is low and the temperature voltage Vtemp is low, the current I1 flowing through the first NMOS transistor N622 is reduced. Due to the characteristics of the differential amplifier, the output voltage Vout is decreased, so that the voltage transmitted to the pull-up unit 630 is reduced, and thus the levels of the first and second voltages and the reference voltage Vref are reduced. The level of the first and second voltages is decreased by a feedback operation until the level of the reference voltage Vref is approximately equal to the temperature voltage.

In summary, the first and second voltages increase at high temperatures, and the first and second voltages decrease at low temperatures. For example, when the first voltage V1 is 1.8V and the second voltage V2 is 1.35V at room temperature, the first voltage V1 is 1.9V and the second voltage V2 is at high temperature. At a low temperature of 1.45V, the first voltage V1 is set to 1.7V and the second voltage V2 is set to 1.25V.

The first voltage supply unit 650 includes a transfer gate T650 for transmitting the first voltage V1 to an output terminal. The transfer gate T650 supplies the first voltage V1 to an output terminal in response to the first voltage supply signal TRANS_V1.

Similarly, the second voltage supply unit 660 includes a transfer gate T660 that transfers the second voltage V2 to an output terminal. The transfer gate T660 supplies the second voltage V2 to the output terminal in response to the second voltage supply signal TRANS_V2.

The programming voltage supply unit 670 includes a PMOS transistor P670 that transfers a power supply voltage VDD to an output terminal. The PMOS transistor P670 transfers a power supply voltage to an output terminal in response to the program signal PGM. During the program operation, the bit line sensing unit N120 is turned on completely so that data applied to the sensing node is transferred to each bit line well.

The voltage supply unit 670 may include an NMOS transistor N680 for transmitting a ground voltage to an output terminal. The NMOS transistor N680 transfers a ground voltage to an output terminal in response to an erase signal ERASE. This is to block the bit line and the sensing node during the erase operation.

7 is a circuit diagram illustrating a bit line sensing voltage supply unit of a nonvolatile memory device according to still another embodiment of the present invention.

The bit line sensing voltage supply unit 700 includes a temperature voltage output unit 710, a comparator 720, a pull-up unit 730, a voltage divider 740, a first voltage V1 supply unit 750, and a second unit. The voltage V2 supply unit 760, a programming voltage supply unit 770, and an erasing voltage supply unit 780 are included.

The overall configuration is similar to the bit line sensing voltage supply unit 680 of FIG. 6, but the configuration of the temperature voltage output unit 710 and the pull-up unit 730 is different. For the sake of simplicity, only the differences will be explained.

The temperature voltage output unit 710 is a pull-up device P712 for supplying a power voltage according to a control signal CON, a resistor RA connected in series between the pull-up device P712 and a ground terminal, and a diode-connected NMOS. The transistor N710 is included. In this case, the voltage applied to the connection node of the resistor RA and the NMOS transistor N710 is used as the temperature voltage Vtemp.

When the temperature is high, that is, when the temperature is higher than room temperature, the threshold voltage Vth of the diode-connected NMOS transistor N710 is reduced, so that the temperature voltage Vtemp is also reduced.

When the temperature is low, that is, when the temperature is lower than room temperature, the threshold voltage Vth of the diode-connected NMOS transistor N710 increases, so that the temperature voltage Vtemp also increases.

That is, compared with the embodiment of FIG. 6, it can be seen that the change direction of the temperature voltage Vtemp according to the temperature change is different.

On the other hand, the pull-up unit 730 includes a PMOS transistor (P730) is turned on in response to the output voltage of the comparator 720 and connected between a power supply voltage terminal and the voltage divider (740). Unlike the embodiment of FIG. 6, as the PMOS transistor P730 is used in the pull-up unit, as the output voltage of the comparator 720 is lower, the level of the supply voltage of the pull-up unit 730 is increased.

Now, the relationship between the change of the temperature voltage Vtemp according to the temperature and the magnitude change of the first voltage V1 and the second voltage V2 will be described.

When the temperature is low and the temperature voltage Vtemp is high, the current I1 flowing through the first NMOS transistor N722 increases. Due to the characteristics of the differential amplifier, the output voltage Vout is increased, so that the voltage delivered to the pull-up unit 730 is increased, thereby reducing the levels of the first and second voltages and the reference voltage Vref. The level of the first and second voltages is decreased by a feedback operation until the level of the reference voltage Vref is approximately equal to the temperature voltage.

On the other hand, when the temperature is high and the temperature voltage Vtemp is low, the current I1 flowing through the first NMOS transistor N722 is reduced. Due to the characteristics of the differential amplifier, the output voltage Vout decreases, so that the voltage delivered to the pull-up unit 730 decreases, thereby increasing the levels of the first and second voltages and the reference voltage Vref. The level of the first and second voltages is increased by a feedback operation until the level of the reference voltage Vref is approximately equal to the temperature voltage.

The configuration of the temperature voltage output unit 710 and the pull-up unit 730 is different from the embodiment of FIG. 6, and the direction of change of the first and second voltages according to the temperature change is the same.

That is, the first and second voltages increase at high temperatures, and the first and second voltages decrease at low temperatures.

Meanwhile, the present invention can be applied not only to the structure in which the bit line sensing unit is separately connected between the bit line selecting unit and the sensing node, but also to the case where the bit line selecting unit includes the function of the bit line sensing unit.

8A and 8B illustrate the configuration of a bit line selecting unit and a bit line sensing unit to which the present invention is applied. Details of the configuration correspond to techniques known to those skilled in the art.

8A illustrates a structure in which the bit line selection unit 810 and the bit line sensing unit 820 are separated, and the present invention is applied in the form of a bit line sensing voltage PBSENSE. 8B illustrates that the NMOS transistors N834 and N836 included in the bit line selector 830 operate as bit line sensing units. In this case, the applied bit line selection voltages BSLe and BSLo are different from each other depending on whether they are even bit line sensing or odd bit line sensing, and a voltage having the same shape as the bit line sensing voltage PBSENSE described above is applied. . Therefore, the present invention can be applied to a structure as shown in FIG. 8B.

FIG. 1A is a diagram illustrating a nonvolatile memory device applied to the present invention, and FIG. 1B is a diagram for describing a concept of a conventional read / verify operation of the nonvolatile memory device.

FIG. 2 is a diagram illustrating a problem caused by temperature change in a read / verify operation of a conventional nonvolatile memory device.

3 is a graph illustrating a change in cell current according to temperature change.

4 is a graph illustrating a change in temperature of a bit line current value appearing when a specific voltage is applied to the bit line sensing unit.

5 is a graph showing characteristics to be used in the present invention in order to minimize the change in temperature of the bit line current value.

6 is a circuit diagram illustrating a bit line sensing voltage supply unit of a nonvolatile memory device according to an exemplary embodiment of the present invention.

7 is a circuit diagram illustrating a bit line sensing voltage supply unit of a nonvolatile memory device according to still another embodiment of the present invention.

8A and 8B illustrate the configuration of a bit line selecting unit and a bit line sensing unit to which the present invention is applied.

Description of the main parts of the drawing

610, 710: temperature voltage output unit 620, 720: comparison unit

630, 730: power supply voltage supply unit 640, 740: voltage distribution

650, 750: first voltage supply 660, 760: second voltage supply

670, 770: voltage supply part in programming 680, 780: voltage supply part in erasing

Claims (21)

A temperature voltage output unit for supplying a temperature voltage increasing in proportion to the magnitude of the external temperature; A comparison unit comparing the magnitudes of the temperature voltages and the reference voltages; A pull-up unit for supplying a high voltage which is increased in proportion to the magnitude of the output voltage of the comparison unit; And a voltage divider for distributing the high voltage to supply a first voltage and a second voltage to an output terminal of the bit line sensing voltage supply unit of the nonvolatile memory device. According to claim 1, wherein the temperature voltage output unit and a pull-up element for supplying a power supply voltage in accordance with a control signal; A first resistor and a diode-connected first NMOS transistor connected in series between the pull-up element and the ground terminal; A second resistor and a second NMOS transistor connected in series between the pull-up element and the ground terminal, And a gate of a second NMOS transistor is connected to a connection node of the first resistor and the first NMOS transistor. The bit line sensing voltage of the nonvolatile memory device of claim 2, wherein the temperature voltage output from the connection node of the second resistor and the second NMOS transistor increases with increasing temperature and decreases with decreasing temperature. Supply department. The method of claim 1, wherein the comparison unit outputs a high level output voltage when the temperature voltage is greater than the reference voltage, And outputting a low level output voltage when the temperature voltage is less than a reference voltage. The bit line sensing voltage of the nonvolatile memory device of claim 1, wherein the pull-up part comprises an NMOS transistor that is turned on in response to an output voltage of the comparator and is connected between a power supply voltage terminal and the voltage divider. Supply department. The method of claim 1, wherein the pull-up unit supplies a high voltage of the first level to the voltage distribution unit as the output voltage of the comparison unit increases, And supplying a high voltage having a second level lower than the first level to the voltage divider as the output voltage of the comparator decreases. The bit line sensing voltage supply unit of claim 1, wherein the first voltage and the second voltage increase in proportion to an increase in temperature. A temperature voltage output unit for supplying a temperature voltage that decreases in proportion to the magnitude of the external temperature; A comparison unit comparing the magnitudes of the temperature voltages and the reference voltages; A pull-up unit for supplying power voltages having different levels according to the magnitude of the output voltage of the comparison unit; A pull-up unit for supplying a high voltage which decreases in proportion to the magnitude of the output voltage of the comparison unit; And a voltage divider for distributing the high voltage to supply a first voltage and a second voltage to an output terminal of the bit line sensing voltage supply unit of the nonvolatile memory device. The apparatus of claim 8, wherein the temperature voltage output unit comprises: a pull-up element configured to supply a power voltage according to a control signal; And a resistor connected in series between the pull-up element and the ground terminal, and a diode-connected NMOS transistor. The bit line sensing voltage supply unit of claim 9, wherein the temperature voltage output from the connection node of the resistor and the NMOS transistor decreases with increasing temperature and increases with decreasing temperature. The method of claim 8, wherein the comparison unit outputs a high level output voltage when the temperature voltage is greater than the reference voltage, And outputting a low level output voltage when the temperature voltage is less than a reference voltage. The bit line sensing voltage of the nonvolatile memory device of claim 8, wherein the pull-up part comprises a PMOS transistor that is turned on in response to an output voltage of the comparator and is connected between a power supply voltage terminal and the voltage divider. Supply department. The method of claim 8, wherein the pull-up unit supplies a high voltage of the first level to the voltage distribution unit in accordance with the increase in the output voltage of the comparison unit, And supplying a high voltage having a second level higher than the first level to the voltage divider as the output voltage of the comparator decreases. The bit line sensing voltage supply unit of claim 8, wherein the first voltage and the second voltage increase in proportion to an increase in temperature. The bit line sensing voltage supply unit of claim 1 or 8, further comprising a programming voltage supply unit configured to supply a power supply voltage to the output terminal in response to a program signal. The bit line sensing voltage supply unit of claim 1, further comprising an erase voltage supply unit supplying a ground voltage to the output terminal in response to an erase signal. The apparatus of claim 1 or 8, further comprising: a first voltage supply unit configured to supply the first voltage to the output terminal in response to a first voltage supply signal; And a second voltage supply unit configured to supply the second voltage to the output terminal in response to a second voltage supply signal. A bit line sensing unit for selectively connecting the sensing node and the bit line according to the bit line sensing signal; And a bit line sensing voltage supply unit configured to change a voltage level of the bit line sensing signal in proportion to a temperature change. 19. The nonvolatile memory device of claim 18, wherein the bit line sensing voltage supply unit increases the voltage of the bit line sensing signal in proportion to an increase in temperature. 19. The method of claim 18, wherein the bit line sensing voltage supply unit is a temperature voltage output unit for supplying a temperature voltage that increases in proportion to the magnitude of the external temperature; A comparison unit comparing the magnitudes of the temperature voltages and the reference voltages; A pull-up unit for supplying a high voltage which is increased in proportion to the magnitude of the output voltage of the comparison unit; And a voltage divider configured to distribute the high voltage to supply a first voltage and a second voltage to an output terminal. 19. The apparatus of claim 18, wherein the bit line sensing voltage supply part comprises a temperature voltage output part supplying a temperature voltage which decreases in proportion to the magnitude of an external temperature; A comparison unit comparing the magnitudes of the temperature voltages and the reference voltages; A pull-up unit for supplying power voltages having different levels according to the magnitude of the output voltage of the comparison unit; A pull-up unit for supplying a high voltage which decreases in proportion to the magnitude of the output voltage of the comparison unit; And a voltage divider configured to distribute the high voltage to supply a first voltage and a second voltage to an output terminal.

Images