KR100816159B1 - Regulator for non volatile memory device - Google Patents

Abstract

A regulator for a nonvolatile memory device is provided to decrease variation width of a threshold voltage according to external voltage variation by changing circuit configuration to reflect the external voltage variation on a first voltage. A reference voltage generation circuit(310) generates a reference voltage by receiving a power supply voltage. A non-inverting amplifying circuit(320) generates a first and a second voltage in response to the reference voltage. A first switching device transfers the first voltage to an output port in response to a first control signal. A second switching device transfers the second voltage to the output port in response to a second control signal. A first voltage control circuit(R6) decreases the first voltage in proportion to a power supply voltage value in response to the first control signal.

Description

Regulator for non volatile memory device

1 is a circuit diagram illustrating a page buffer of a flash memory device to which the present invention is applied.

FIG. 2 is a waveform diagram illustrating a read operation of the page buffer of FIG. 1.

3 is a circuit diagram illustrating a regulator according to an embodiment of the present invention.

FIG. 4 is a simplified circuit diagram of FIG. 3 to obtain a relationship of voltage V1.

Description of the main parts of the drawing

100: page buffer

110: bit line selector

120: register

122: latch

310: band gap circuit

320: non-inverting amplifier

322: OP amplifier

The present invention relates to a regulator for supplying a specific voltage to a page buffer included in a nonvolatile memory device. More particularly, the present invention relates to reducing a change in the threshold voltage of a specific cell in an operation of reading a specific cell of the memory device. It is about a regulator.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function that requires rewriting data at regular intervals. The NAND-type flash memory of the nonvolatile memory device uses a page buffer to store a large amount of information in a short time and to verify normal program and erase. Conventional page buffers consist of a single register to temporarily store data, but recently, dual registers are used to increase the speed of data programs.

Meanwhile, technologies for storing a plurality of bits of data in one memory cell have been studied to improve the degree of integration of a memory device. For example, in the past, data of '0' and '1' were separately stored based on two threshold voltages for one cell, but according to the recent multi-level cell technology, '00' is based on four threshold voltages. Data such as', '01', '10' and '11' can be stored in one cell.

However, in order to apply the multi-level cell technology as described above, the variation of the threshold voltage value of each level should be small, and in particular, the variation of the threshold voltage value due to the change of the external environment should be minimized.

In a typical pager buffer, a first voltage for precharging a specific bit line and a second voltage for sensing a voltage level of a specific bit line are sequentially sequentially sensed to detect a state value in a read operation of a specific cell. In this case, the difference between the first voltage and the second voltage is maintained in the same value despite the change in the external power supply voltage, there is a problem that the threshold voltage value fluctuates.

In order to solve the above problems, the present invention is a non-volatile to reduce the fluctuation range of the threshold voltage value according to the external voltage change by modifying the circuit configuration so that the change value is also reflected in the first voltage when the external power supply voltage changes It is an object to provide a regulator for a memory device.

The regulator of the present invention for achieving the above object is a reference voltage generator for receiving a power supply voltage value to generate a reference voltage; A non-inverting amplifier configured to generate first and second voltages respectively in response to the reference voltage; A first switching element transferring the first voltage to an output terminal in response to a first control signal; A second switching element configured to transfer the second voltage to the output terminal in response to a second control signal, and a first voltage controller configured to decrease the first voltage value in proportion to a power supply voltage value in response to the first control signal; It is characterized by including.

Before describing the present invention, a read operation performed in the page buffer of the flash memory device to which the present invention is applied will be briefly described.

1 is a circuit diagram illustrating a page buffer 100 of a flash memory device to which the present invention is applied. The page buffer 100 may include a bit line selection unit 110 that selectively connects the bit line BLe and the bit line BLO with the sensing line SO, and the bit line BLe or BLo through the sensing line SO. And a register unit 120 for detecting data of the s) and storing the data.

The bit line selector 110 includes NMOS transistors N3 and N4 connected between the bit lines BLe and BLo and the sense line SO. In response to the bit line selection signal BSLe or BSLo, the NMOS transistor N3 or N4 is turned on to connect the bit line BLe or BLo and the sense line SO.

In addition, the bit line selector 110 includes NMOS transistors N1 and N2 connected in series between the bit line BLe and the bit line BLO. In response to the discharge signal DISCHe or DISCHo, the NMOS transistor N1 or N2 is turned on so that the verify signal VIRPWR is applied to the bit line BLe or BLo.

The register unit 120 includes a sense line SO and a latch 122 that temporarily stores data. A detailed configuration thereof will be described below.

The PMOS transistor P1 controlled by the precharge signal PRECHb is connected between the power supply terminal Vcc and the sense line SO. In response to the precharge signal PRECHb, the PMOS transistor P1 is turned on so that the power supply voltage Vcc is applied to the bit line BLe or BLo through the sensing line SO.

On the other hand, the latch 122 includes two inverters IV2 and IV3 connected in series with each other, and the output terminal QA of the inverter IV2 becomes the output terminal of the latch 122, and The output terminal QB becomes the input terminal of the latch 122.

An NMOS transistor N8 controlled by the reset signal RESET is connected between the ground terminal and the output terminal QA of the latch 122. In response to the reset signal RESET, the NMOS transistor N8 is turned on so that the ground power supply GND is applied to the output terminal QA, and a low level signal is applied to the output terminal QA so that the latch 122 is initialized. do. The inverter IV1 and the NMOS transistor N5 are connected in series between the input terminal QB and the sense line SO, and the NMOS transistor N5 is turned on in response to the program signal PGM to turn on the input terminal QB. And sense line SO are connected. The NMOS transistor N6 and the NMOS transistor N7 are connected in series between the input terminal QB and the ground terminal GND. The NMOS transistor N6 is turned on in response to the sense line SO potential, the NMOS transistor N7 is turned on in response to the read signal READ, and the ground power source GND is applied to the input terminal QB. Thus, the potential of the input terminal QB is changed.

FIG. 2 is a waveform diagram illustrating a read operation of the page buffer of FIG. 1.

 1) T1 section: Initialization section of latch

Discharge signals DISCHe and DISCHo are applied to the gates of the NMOS transistors N1 or N2 of the bit line selector 110 at a high level so that the NMOS transistors N1 and N2 are turned on, and the verification signal VIRPWR is turned on. It is applied to the bit lines BLe and BLo through the turned-on transistors N1 and N2. Since the verification signal VIRPWR maintains a voltage of 0V during the read operation, a voltage of 0V is applied to the bit lines BLe and BLo. On the other hand, the reset signal RESET is applied to the gate of the NMOS transistor N8 of the register unit 120 to turn on the NMOS transistor N8. Therefore, the ground power source GND is applied to the output terminal QA, and the output node QA of the latch 122 is initialized to the low level.

 2) T2 section: Bit line precharge section

The discharge signal signal DISCHe is applied to the gate of the NMOS transistor N1 of the bit line selector 110 at a low level so that the NMOS transistor N1 is turned off and a voltage of 0V is applied to the bit line BLe. Maintaining verification signal VIRPWR is blocked. The precharge signal PRECHb is applied to the gate of the PMOS transistor P1 at a low level to turn on the PMOS transistor P1. Therefore, the power supply voltage Vcc is applied to the sense line SO and maintained at the high level. Thereafter, the bit line selection signal BSLe is applied to the gate of the NMOS transistor N3 of the bit line selection unit 110 at a potential of the first voltage V1, and the bit line selection signal is applied to the gate of the NMOS transistor N4. When BSLo is applied at a low level, voltages V1 -Vt obtained by subtracting the threshold voltage of the first voltage V1 and the NMOS transistor N3 are applied to the bit line BLe.

 3) T3 section: cell evaluation

As the bit line select signal BSLe is applied to the gate of the NMOS transistor N3 of the bit line selector 110 at a low level, the potential of the bit line BLe is turned off as the NMOS transistor N3 is turned off. It is changed by the state of the memory cell connected to BLe). Therefore, when the memory cell is a program cell, the bit line (BLe) potential is maintained at the potential of (V1-Vt), and when the erase cell is the erase cell, the bit line (BLe) potential is gradually decreased at (V1-Vt) to maintain the low level Done.

 4) T4 section: Bitline Valuation

The precharge signal PRECHb is applied to the gate of the PMOS transistor P1 at a high level before the bit line selection signal BLSe is applied to the gate of the NMOS transistor N3 of the bit line selector 110 at a high level. The PMOS transistor P1 is turned off. The bit line selection signal BLSe is applied to the gate of the NMOS transistor N3 at the potential of the second voltage V2, so that the NMOS transistor N3 is turned on. In this case, the second voltage V2 has a voltage value such that the voltage level of the bit line can be applied to the sensing line SO, and typically has a smaller value than the first voltage V1.

In this case, when the memory cell is a program cell, the bit line BLe potential maintains the potential of (V1-Vt), and the potential of the sense line SO maintains the high level. However, when the memory cell is an erase cell, the potential of the bit line BLe gradually decreases to maintain a low level, and the potential of the sense line SO maintains a low level. Thereafter, the high level read signal READ is applied to the NMOS transistor N7, and the NMOS transistor N6 is driven by the potential of the sense line SO. Therefore, data is stored in the latch 122 according to the potential of the sense line SO.

In the read operation as described above, the change of the threshold voltage of the cell according to the voltages V1 and V2 applied to the bit line selection signal BLSe is described first. The difference between V1 and V2, that is, the value of (V1-V2) As the value becomes smaller, the threshold voltage of the cell detected by the page buffer increases. Second, as the power supply voltage Vcc increases, the threshold voltage of the cell detected by the page buffer tends to decrease. Conversely, when the power supply voltage Vcc decreases, the threshold voltage of the cells detected by the page buffer tends to increase. There is this.

The regulator is configured so that the V1 voltage is affected by the change in the power supply voltage Vcc. When the power supply voltage Vcc is increased, the V1 voltage is decreased so that the threshold voltage decrease of the cell due to the increase in the power supply voltage Vcc is achieved. In addition, the increase in the threshold voltages of the cells due to the decrease in the value of (V1-V2) cancels each other so as to minimize the threshold voltage fluctuation caused by the fluctuation of the power supply voltage Vcc.

3 is a circuit diagram illustrating a regulator according to an embodiment of the present invention.

The regulator is controlled by the non-inverting amplifier 320 including the bandgap circuit 310, the OP amplifier 322 and the variable resistors R1, R2, R3, R4, and R5, and the precharge signal V _PRE . NMOS transistors 331 and 335, an NMOS transistor 333 controlled by a sensing signal V _SEN , and a variable resistor R6 for voltage distribution.

The band gap circuit 310 is a reference voltage generator that generates a reference voltage Vref that does not affect the variation of the power supply voltage Vcc and thus the ratio of the OP amplifier 322 included in the non-inverting amplifier 320. Input it to the reverse terminal (+).

The non-inverting amplifier 320 generates first and second voltages respectively in response to a reference voltage. The variable resistors R1, R2 and R3 connected in series of the non-inverting amplifier 320 are feedback resistors and are connected between the output terminal Vout and the inverting terminal (-) of the OP amplifier 322. The inverting terminal (-) of the OP amplifier 322 is grounded through the variable resistors R4 and R5. The voltage at the connection point between the variable resistor R3 and the variable resistor R4 is input to the inverting terminal (−), and the reference voltage Vref of the band gap circuit 310 is input to the non-inverting terminal (+).

The variable resistors R1, R2, and R3 not only serve as feedback resistors, but also perform voltage distribution with respect to the output voltage Vout of the OP amplifier 322. According to the result of the voltage distribution, the voltage V1 of the connection node of the variable resistor R1 and the variable resistor R2 becomes a first voltage applied to a section for precharging the bit line as the bit line selection signal BLSe. The voltage V2 of the connection node between the variable resistor R2 and the variable resistor R3 becomes a second voltage applied to the section for sensing the bit line.

The NMOS transistor 331 is turned on by the voltage V _PRE which becomes a high level in a period (T2 of FIG. 2) that precharges a specific bit line during a read operation of the page buffer included in the nonvolatile memory device. Therefore, the voltage V1 is used as the bit line selection signal BSLe or BSLo. In addition, when the NMOS transistor 335 is turned on, the power supply voltage Vcc is included in the voltage V1. The specific formula will be described later.

The NMOS transistor 333 is turned on by a high voltage V _SEN during a page buffer read operation included in the nonvolatile memory device (T4 in FIG. 2) during sensing of a voltage level of a specific bit line. Therefore, the voltage V2 is used as the bit line selection signal BSLe or BSLo.

The output terminal BSLe or BSLo connected to the NMOS transistor 331 and the NMOS transistor 333 is connected to a control gate of a specific bit line select transistor N3 or N4 included in the page buffer 100.

Meanwhile, the NMOS transistors 331, 333, and 335 may be replaced with PMOS transistors that are turned on when a low level is applied to a gate. In this case, the voltage V _PRE or V _SEN ) is replaced by a signal having a low level value in the precharge period or the sensing period, respectively.

In order to control the first voltage, a power supply voltage Vcc, a variable resistor R6, and an NMOS transistor 335 are connected to configure a first voltage controller. The power supply voltage Vcc is connected to the connection node of the variable resistor R4 and the variable resistor R5 through the variable resistor R6 and the NMOS transistor 335. According to the configuration as described above, the NMOS transistor 335 is turned on in the precharge period, the power supply voltage (Vcc) affects the magnitude of the voltage (V1). In the sensing period, since the NMOS transistor 335 is turned off, the size of the voltage V2 is not affected.

In summary, the regulator generates a voltage V1 applied as the bit line selection signal in the precharge period and a voltage V2 applied as the bit line selection signal in the sensing period during the read operation of the page buffer, in particular, the voltage V1. ) Is a power supply voltage (Vcc) component in the voltage (V1) when the NMOS transistor 335 is turned on.

FIG. 4 is a simplified circuit diagram of FIG. 3 to obtain a relationship of voltage V1.

According to the assumption that the OP amplifier 322 is an ideal OP amplifier, since the voltages of the non-inverting terminal and the inverting terminal are the same, Equation 1 is established.

Further, when Kirchhoff's law is applied to a node to which the variable resistors R6 and R4 and R5 are connected, Equation 2 is established.

On the other hand, in the ideal OP amplifier, the current input to the non-inverting terminal and the inverting terminal is 0, so Equation 3 is established.

By solving the above equations, the equation for voltage V1 can be obtained.

According to the result, when the power supply voltage Vcc increases, the voltage V1 decreases, and when the power supply voltage Vcc decreases, the voltage V1 increases.

According to the configuration of the present invention described above, when the power supply voltage Vcc is increased, the voltage V1 applied as the bit line selection signal in the precharge period is decreased, and the threshold voltage decrease of the cell due to the increase in the power supply voltage Vcc The increase in the threshold voltages of the cells due to the decrease of the (V1-V2) values is canceled with each other, thereby minimizing the threshold voltage variation due to the change in the power supply voltage Vcc. As the threshold voltage fluctuation due to the fluctuation of the external power supply voltage Vcc is minimized, the sensing margin can be increased, and the reliability of data stored in the cell is also improved.

Claims (6)

A reference voltage generator configured to receive a power supply voltage and generate a reference voltage; A non-inverting amplifier configured to generate first and second voltages respectively in response to the reference voltage; A first switching element transferring the first voltage to an output terminal in response to a first control signal; A second switching element transferring the second voltage to the output terminal in response to a second control signal; A first voltage controller which reduces the first voltage in proportion to a power supply voltage value in response to the first control signal Regulator for a nonvolatile memory device comprising a. The regulator of claim 1, wherein the reference voltage generator comprises a band gap circuit configured to receive the power supply voltage, generate a reference voltage, and transmit the reference voltage to the non-inverting amplifier. According to claim 1, wherein the non-inverting amplification unit An op amp having an inverting and non-inverting input terminal and inputting the reference voltage to a non-inverting input terminal; A first resistor connected between an output terminal of the OP amplifier and a first node to which the first voltage is output; A second resistor connected between the first node and a second node at which the second voltage is output; A third resistor connected between the second node and the inverting input terminal of the OP amplifier; And a fourth and a fifth resistor connected between the inverting input terminal of the op amp and ground. 4. The regulator of claim 1 or 3, wherein the first switching element comprises a transistor connected between the first node and the output terminal and turned on in response to the first control signal. 4. The regulator of claim 1 or 3, wherein the second switching element comprises a transistor connected between the second node and the output terminal and turned on in response to the second control signal. The method of claim 3, wherein the first voltage control unit A sixth resistor connected to the power supply voltage source; A transistor connected between the connection node of the fourth and fifth resistors and the sixth resistor and turned on in response to the first control signal; Regulator for a nonvolatile memory device comprising a.

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