KR100673704B1 - Page buffer of flash memory device - Google Patents

Abstract

The present invention relates to a page buffer of a flash memory device, and the present invention relates to a page buffer of a flash memory device. 'When stuck fail occurs and replaced by the redundancy cell, regardless of the pass signal generation operation, it prevents the fail state during program and copyback operation, and simultaneously validates 2KB using the node value of the latch of the cache register during the erase verify operation. A page buffer of a flash memory device capable of shortening verification time is disclosed.

NAND Flash, Page Buffer, Validation Operation

Description

Page buffer of flash memory device

1 is a configuration diagram of a page buffer for explaining a verification operation using a conventional page buffer.

2 is a circuit diagram illustrating a connection structure of a plurality of page buffer detection signal terminals.

3 is a detailed circuit diagram of a page buffer for explaining the page buffer according to the present invention.

4 is a circuit diagram illustrating a verification signal generator in a program verify operation.

5 is a circuit diagram illustrating a verification signal generator in an erase verify operation.

Description of the main parts of the drawing

10, 110: memory cell array 21, 120: verification signal supply unit

22, 130: bit line selector 23, 140: precharge unit

24, 150: main register 25, 160: cache register

26, 151: main latch 17, 161: cache latch

170: verification signal control unit

TECHNICAL FIELD The present invention relates to a page buffer of a flash memory device, and more particularly, to a page buffer that prevents a failing verify operation and reduces a verify time.

Recently, there is an increasing demand for semiconductor memory devices that can be electrically programmed and erased and that do not require a refresh function to rewrite data at regular intervals. In order to develop a large-capacity memory device capable of storing a larger amount of data, technical research on high integration of memory devices has been actively studied.

For high integration of memory cells, a NAND type flash memory device has been developed in which a plurality of memory cells are connected in series to form a string. The NAND type flash memory device is programmed and erased by injecting or extracting electrons into the floating gate of the NAND type flash memory device by a Fowler-Nordheim Tunneling method.

NAND-type flash memory devices use a page buffer to store large amounts of information in a short time and to verify normal program and erase. A typical page buffer is composed of a single register to temporarily store data, but recently, dual registers are used to increase the speed of data programs.

FIG. 1 is a configuration diagram of a page buffer having a dual register structure of a general NAND type flash memory device. The program register and the copy back operation are performed using the main register 24 and the cache register 25. Only the main register 24 is used to perform read and program erase verify operations. The operation of the page buffer in the program erase verification will be described briefly as follows.

The discharge signals DISCHe and DISCHo are applied to the verify signal supply unit 21, and a verify signal VIRPWR is applied to one bit line among the even and odd bit lines. The main register 24 includes a latch 26 in which the output node QA of the latch 26 is initialized in response to the reset signal RESET_L. When the precharge signal PRECHb is applied to the precharge unit 23 at the low level, the power supply voltage Vcc is applied to the sensing node SO to maintain the sensing node SO at the high level. Thereafter, the even bit line selection signal BSLe is applied to the bit line selection unit 22 at the potential of the first voltage V1, and the even bit line BLe is precharged to V1 -Vt. Thereafter, the even bit line selection signal BSLe is applied to the bit line selection unit 22 at a low level, and the cell is evaluated. The precharge signal PRECHb is applied to the precharge unit 23 at a high level so that the node applying the power supply voltage Vcc to the sensing node SO is cut off. At this time, the even bit line selection signal BSLe is applied to the bit line selection unit 22 at the potential of the second voltage V2. Thereafter, the read signal READ_L is applied to the main register 24, and the input node QAb and the output node QA of the latch 26 are caused by the sense node SO potential which changes according to the program or erase state of the cell. The potential of is changed. That is, in the case of a program cell, the sensing node SO maintains a high level potential, and in the case of an erase cell, the sensing node SO is discharged to a low level. Therefore, when the sensing node SO maintains the high level, the potential of the input node QAb becomes the low level, and the output node QA becomes the high level. The detection signal nWDO_L terminal is floated by the high level output node QA potential. On the other hand, when the sensing node SO maintains the low level, the potential of the input node QAb and the output node QA does not change, so the output node QA maintains the low level. The detection signal nWDO_L potential becomes high by the low level output node QA potential. Therefore, in the case of a program cell, the potential of the detection signal nWDO_L is floated, and in the case of an erase cell, the potential of the detection signal nWDO_L is high.

One page buffer configured as described above is connected to one bit line of a flash memory device. In addition, as illustrated in FIG. 2, the detection signal nodes nWDO_L of each page buffer are output in a group. That is, in the case of a flash memory device having 512 bit lines, 512 detection signal nodes nWDO_L from 512 page buffers are output as one line integrated. Therefore, since one bit of the detection signal nWDO is output for every 512 page buffers, a pass / fail bit is finally generated using the 16-bit detection signal nWDO. However, even when a bit line with a '0' stuck fail is replaced with a redundancy cell during program verification, the detection signal node nWDO is involved in a pass check, even if all other cells succeed in the program. As a result, a fail occurs. In addition, during erase verification, the data stored in the latch 26 of the main register 24 of the page buffer is read and all of the data are '0' (PASS) or at least one '1' value (Fail). Determine pass / fail. In this case, it takes 100ns to read one column (8bit or 16bit), so if one page consists of 2KB, it takes 200ms.

Therefore, the page buffer of the flash memory device according to the present invention connects the detection signal controller between the latch of the main register and the latch of the cache register to generate a pass signal when a zero zero stuck fail is generated and replaced by a redundancy cell during the program verify operation. It is to prevent fail status during program and copyback operation regardless of operation. In addition, during the erase verification operation, the verification time is reduced by simultaneously verifying 2KB using the node value of the latch of the cache register.

The page buffer of the flash memory device according to the present invention is connected to the even and odd bit lines of a memory cell array, and provides a verify signal supply unit for supplying a verify signal to the even and odd bit lines of the memory cell array by a discharge signal. A bit line selection unit connected between the verification signal supply unit and the sensing node to connect the bit line and the sensing node by a bit line selection signal, and a main register connected to the sensing node and the input / output terminal to temporarily store data; A cache register connected to the sensing node and an input / output terminal in parallel with the main register to temporarily store data, and a verification signal controller connected between the main register and the cache register to control detection signal generation during a verify operation; Include.

3 is a circuit diagram of a flash memory device according to an exemplary embodiment of the present invention. Hereinafter, the configuration of the flash memory device according to the exemplary embodiment of the present invention will be described in detail.

The verify signal supply unit 120 includes NMOS transistors N121 and N122 connected in series between the even bit line BLe and the odd bit line BLO. The NMOS transistors N121 and N122 are turned on in response to the discharge signals DISCHe and DISCHo so that the verify signal VIRPWR is applied to the bit lines BLe and BLo.

The bit line selector 130 includes NMOS transistors N131 and N132 connected between the bit lines BLe and BLo and the sensing node SO. The NMOS transistors N131 and N132 are turned on in response to the bit line selection signals BSLe and BSLo to connect the bit lines BLe and BLo and the sensing node SO.

The precharge unit 140 is connected between the power supply terminal Vcc and the sensing node SO and includes a PMOS transistor P141 connected between the power supply terminal Vcc and the sensing node SO. The PMOS transistor P301 is turned on in response to the precharge signal PRECHb to apply the power supply voltage Vcc to the sensing node SO.

The in register 150 is connected between the sensing node SO and the input / output terminal YA and includes a latch 161 for temporarily storing data. A detailed configuration thereof will be described below.

The NMOS transistor N151 and the NMOS transistor N152 are connected in series between the input node QAb and the ground terminal Vss. The NMOS transistor N151 is turned on in response to the sensing node SO potential, the NMOS transistor N152 is turned on in response to the read signal READ_L, and the ground power source Vss is applied to the input node QAb. Thus, the potential of the input node QAb is changed. The NMOS transistor N153 is connected between the input node QAb and the sensing node SO, and the NMOS transistor N153 is turned on in response to the copyback signal COPYBACK to turn on the input node QAb and the sensing node SO. Is connected. The inverter I151 and the NMOS transistor N154 are connected in series between the input node QAb and the sensing node SO, and in response to the program signal PROGRAM_L, the NMOS transistor N154 is turned on so that the input node QAb. And detection node (SO) are connected. The NMOS transistor N155 is connected between the input node QAb and the input / output terminal YA, and the NMOS transistor N155 is turned on in response to the data input signal DI_L to turn on the input node QAb and the input / output terminal YA. Is connected. The NMOS transistor N156 is connected between the output node QA and the input / output terminal YA, and the NMOS transistor N156 is turned on in response to the inversion data input signal nDI_L to turn on the input / output terminal YA and the output node QA. ) Is connected. The NMOS transistor N157 is connected between the node between the inverter I1511 and the NMOS transistor N154 and the input / output terminal YA, and the NMOS transistor N157 is turned on in response to the page buffer detection signal PBDO_L to input the node. The QAb and the input / output terminal YA are connected. The NMOS transistor N158 is connected between the output node QA and the ground terminal Vss, and the NMOS transistor N158 is turned on in response to the reset signal RESET_L so that the ground power supply Vss is connected to the output node QA. Is approved. Thus, the output node QA is at the low level and the latch 151 is initialized. The latch 151 has a structure in which two inverters are connected in parallel in a reverse direction.

The cache register 160 is connected between the sensing node SO and the input / output terminal in parallel with the main register 150. The detailed configuration is as follows.

The NMOS transistor N161 and the NMOS transistor N162 are connected in series between the input node QBb and the ground terminal Vss. The NMOS transistor N161 is turned on in response to the sensing node SO potential, the NMOS transistor N162 is turned on in response to the read signal READ_R, and the ground power source Vss is applied to the input node QBb. Thus, the potential of the input node QBb is changed. The inverter I161 and the NMOS transistor N163 are connected in series between the input node QBb and the sensing node SO, and the NMOS transistor N163 is turned on in response to the program signal PROGRAM_R to turn on the input node QBb. And detection node (SO) are connected. The NMOS transistor N165 is connected between the input node QAb and the input / output terminal YA, and the NMOS transistor N164 is turned on in response to the data input signal DI_R to turn on the input node QBb and the input / output terminal YA. Is connected. The NMOS transistor N165 is connected between the output node QB and the input / output terminal YA, and the NMOS transistor N165 is turned on in response to the inversion data input signal nDI_R so that the input / output terminal YA and the output node QA are turned on. ) Is connected. The NMOS transistor N166 is connected between the node between the inverter I161 and the NMOS transistor N163 and the input / output terminal YA, and the NMOS transistor N166 is turned on in response to the page buffer detection signal PBDO_R to input the node. (QBb) and the input / output terminal (YA) are connected. The NMOS transistor N167 is connected between the output node QB and the ground terminal Vss, and the NMOS transistor N167 is turned on in response to the reset signal RESET_R so that the ground power source Vss is turned on by the output node QB. Is applied. Accordingly, the output node QB goes low and the latch 161 is initialized. The latch 161 has a structure in which two inverters are connected in parallel in a reverse direction.

The verification signal controller 170 is connected to the node QA of the latch 151 of the main register 150 and the node QB of the latch 161 of the cache register 160, and the plurality of NMOS transistors N171. 173) and a plurality of PMOS transistors P171-173. NMOS transistor N171 and NMOS transistor N172 are connected in series between node QA of main register 150 and node QB of cache register 160. The NMOS transistor N171 is turned on in response to the main detection signal LEFT to apply the potential of the node QA to the verification signal controller 170. The NMOS transistor N172 is turned on in response to the cache detection signal RIGHT to apply the potential of the node QB to the verification signal controller 170. The PMOS transistor P171 and the PMOS transistor P173 are connected in series between the power supply voltage Vcc and the detection signal terminal nWDO. The PMOS transistor P171 is turned on in response to the redundancy signal RDIOEN, and the PMOS transistor P173 is turned on in accordance with the potential of the node QA applied by the NMOS transistor N171 to program detect the power supply voltage Vcc. Applied to the signal terminal nWDO. The PMOS transistor P172 and the NMOS transistor N173 are connected in series between the ground power supply Vss and the detection signal terminal nWDOe. The PMOS transistor P172 is turned on in response to the redundancy signal RDIOEN, and the NMOS transistor N173 is turned on in accordance with the potential of the node QB applied by the NMOS transistor N172 to erase the ground power supply Vss. Applied to the signal terminal (nWDOe).

The case where the even bit line BLe is selected for the verification operation of the page buffer of the flash memory device according to the present invention configured as described above will be described in detail as follows.

1) Initialization section of latch

When the discharge signals DISCHe and DISCHo are applied to the transistors N121 and N122 of the verification signal supply unit 120 at a high level, the NMOS transistors N121 and N122 are turned on. Therefore, the verify signal VIRPWR is applied to the bit lines BLe and BLo. During the read operation, since the verify signal VIRPWR maintains a voltage of 0V, a voltage of 0V is applied to the bit lines BLe and BLo. The reset signal RESET_L is applied to the NMOS transistor N158 of the main register 150 to turn on the NMOS transistor N158. Therefore, the ground power source Vss is applied to the node QA, and the node QA of the latch 151 is initialized to the low level. The reset signal RESET_R is applied to the NMOS transistor N167 of the cache register 160 to turn on the NMOS transistor N167. Therefore, the ground power source Vss is applied to the node QBb so that the node QB of the latch 161 is initialized to the high level.

2) Bit line precharge section

Verify that the even discharge signal DISCHe is applied to the NMOS transistor N121 of the verify signal supply unit 120 at a low level so that the NMOS transistor N121 is turned off and maintains a voltage of 0 V in the even bit line BLe. The signal VIRPWR is cut off. The low level precharge signal PRECHb is applied to the PMOS transistor P141 of the precharge unit 140 to turn on the PMOS transistor P141. Therefore, the power supply voltage Vcc is applied to the sensing node SO so that the sensing node SO maintains a high level. Thereafter, an even bit line selection signal BSLe is applied to the NMOS transistor N131 of the bit line selection unit 130 at a potential of the first voltage V1, and the odd bit line selection signal BSLo is applied to the NMOS transistor N132. Is applied at a low level, the voltages V1 -Vt obtained by subtracting the threshold voltage of the first voltage V1 and the NMOS transistor N131 are applied to the even bit line BLe.

3) Cell Evaluation

The bit line select signal BSLe is applied to the NMOS transistor N131 of the bit line selector 130 at a low level so that the even bit line BLe potential is changed by the state of the memory cell connected to the even bit line BLe. do. Therefore, when the memory cell is a program cell, the even bit line (BLe) potential maintains the potential of (V1-Vt), and in the case of an erase cell, the even bit line (BLe) potential decreases gradually from (V1-Vt) to a low level. Will be maintained.

4) Bitline Valuation

Before the even bit line select signal BLSe is applied to the NMOS transistor N131 of the bit line selector 130 to a high level, the precharge signal PRECHb is applied to the PMOS transistor P141 of the precharge unit 140. The PMOS transistor P141 is turned off by being applied at a high level. The even bit line selection signal BLSe is applied to the NMOS transistor N131 of the bit line selector 130 as a potential of the second voltage V2, thereby turning on the NMOS transistor N131. In this case, when the memory cell is a program cell, the bit line BLe potential maintains the potential of (V1-Vt), and the sense node SO potential maintains the high level. However, when the memory cell is an erase cell, the potential of the bit line BLe gradually decreases to maintain a low level, and the potential of the sensing node SO maintains a low level.

5) data latch

The read signal READ_L is applied to the NMOS transistor N152 of the main register 150 at a high level to turn on the NMOS transistor N152. Then, in the case of the program cell, the sensing node SO maintains a high level, and the NMOS transistor N151 is turned on in response to the sensing node SO of the high level, so that the ground power source Vss becomes a node of the latch 151. QAb). Thus, node QAb of latch 151 goes low and node QA goes high. In contrast, when the memory cell is an erase cell, the sensing node SO maintains a low level, and the NMOS transistor N306 is turned off in response to the sensing node SO of the low level. Therefore, even when the read signal READ_L is applied to the gate of the NMOS transistor N152 of the main register 151, the node QAb maintains a high level. As a result, the node QA also maintains a low level.

6) Detection signal generation

The main detection signal LEFT is applied to the verification signal controller 107 to turn on the NMOS transistor N171. Therefore, the potential of the node QA is applied to the PMOS transistor P173 and the NMOS transistor N173.

6-1) Program Verification

Since the potential of the node QA is at a high level, the PMOS transistor P173 is turned off. Therefore, the program detection terminal nWDO is in a floating state.

If a bit line with a '0' stuck fail is replaced with a redundancy cell during program verification, the potential of the node QA is at a low level. Thus, the PMOS transistor P173 is turned on. However, the PMOS transistor P171 is turned off by the redundancy signal RDIOEN. Therefore, the program detection terminal nWDO is in a floating state.

 4 is a circuit diagram of a program verification signal generator of a flash memory device. The program verification operation of the page buffer of the present invention will be described with reference to FIG. 3.

When the redundancy cell is replaced during the program verify operation, the program detection terminal nWDO is in a floating state. Therefore, in the floating state of the verify check signal CHECK and the program detection terminal nWDO, the logic gate verify signal WDO is generated by the NOR gate. Therefore, when a zero zero stuck fail occurs during the program verify operation and is replaced with a redundant cell, the fail state is prevented during the program and copyback operation regardless of the pass signal generation operation.

6-2) In the case of the erase verification operation

Since the potential of the node QA is at the low level, the NMOS transistor P173 is turned off. Therefore, the erase detection terminal nWDOe is in a floating state. However, when a failure occurs in one or more bits of the 512 bits, the NMOS transistor N173 is turned on so that the erase detection terminal nWDOe is connected to the ground power supply Vss to become the ground power supply Vss level.

 5 is a circuit diagram of an erase verification signal generator of a flash memory device. The erase verification operation of the page buffer of the present invention will be described with reference to FIG. 5.

When all cells are passed during the erase verify operation and the erase detection terminal nWDOe is in a floating state, a verification signal of logic high is generated by the NAND gate according to the floating state of the verify check signal CHECK and the erase detection terminal nWDO. WDOe) is generated. On the other hand, when one or more fail cells are generated and the erase detection terminal nWDOe is in the ground state, the detection signal WDOe of the logic low is generated by the NAND gate according to the floating state of the verify check signal CHECK and the erase detection terminal nWDO. ) Is generated. Accordingly, the verification time can be reduced to 100 ms by performing erase verification using the value of the node QA.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, a detection signal controller is connected between a latch of a main register and a latch of a cache register to generate a program and copy regardless of a pass signal generation operation when a zero zero stuck fail is generated and replaced by a redundancy cell. Fail state can be prevented during back operation. In the erase verify operation, the verification time can be shortened by simultaneously verifying 2KB using the node value of the latch of the cache register.

Claims (7)

A verify signal supply unit connected to the even and odd bit lines of a memory cell array and supplying a verify signal to the even and odd bit lines of the memory cell array by a discharge signal; A bit line selection unit connected between the verification signal supply unit and the sensing node to connect the bit line and the sensing node by a bit line selection signal; A main register connected to the sensing node and an input / output terminal for temporarily storing data; A cache register connected to the sense node and the input / output terminal in parallel with the main register to temporarily store data; And And a detection signal controller connected between the main register and the cache register to control detection signal generation during a verify operation. The method of claim 1, And the page buffer further comprises a precharge unit connected between a power supply terminal and the sensing node to maintain the predetermined potential by the precharge signal by a precharge signal. The method of claim 1, And the verify signal supply unit comprises a transistor configured to apply the verify signal to a bit line in response to the discharge signal. The method of claim 1, And the bit line selector comprises a transistor connecting the bit line and the sensing node in response to the bit line select signal. The method of claim 1, And the main register and the cache register each comprise two inverters connected in parallel in a reverse direction and each including a latch for storing data. The method of claim 5, wherein the verification signal controller A first switching unit controlling a program detection signal by a node potential of the latch of the main register or the cache register when all cells operate normally during a program verify operation; A second switching unit controlling the detection signal by the redundancy signal when the failed cell is replaced with the redundancy cell during the program verify operation; And And a third switching unit configured to control an erase detection signal by a node potential of the latch of the main register or the cache register when all cells operate normally during an erase verify operation. The method of claim 6, The verification signal controller may further include a switching unit configured to connect the verification signal controller to the main register and the cache register in response to a verification signal.

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