KR100769802B1 - Page buffer of flash memory device and method for programming using the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a page buffer of a flash memory device and a programming method using the same, wherein after inputting data to be programmed into an upper bit register, the lower bit data read from a memory cell is stored in the lower bit register and the lower bit data is programmed. Program time by eliminating the step of retransmitting from the lower bit register to the upper bit register by performing the verify operation in the middle of programming the data of the upper bit register to the memory cell and checking the program. It relates to a page buffer of a flash memory device and a programming method using the same.

Flash memory, multi-level cells, page buffers, programs

Description

Page buffer of flash memory device and method for programming using the same}

1 is a graph illustrating a relationship between data of a multi-level cell and a threshold voltage.

2 is a diagram illustrating a page buffer of a flash memory device having a conventional multi-level cell.

3 is a detailed circuit diagram of a page buffer of a flash memory device having a multi-level cell according to the present invention.

4A to 4C are timing diagrams of signals for explaining an operation of a higher bit data program using a page buffer of a flash memory device having a multi-level cell according to the present invention.

Description of the main parts of the drawing

10: page buffer 100: memory cell

110: verification signal supply unit 11, 120: bit line selection unit

12, 130: precharge unit 13, 140: upper bit register

14, 150: low bit register 15: data comparator

16: data transmission circuit 17: data path circuit

The present invention relates to a flash memory device, and more particularly, to a page buffer and a program operation method of a flash memory device having a multi-level cell.

Recently, there is an increasing demand for semiconductor memory devices that can be electrically programmed and erased and that do not require a refresh function to rewrite data at regular intervals. In order to develop a large-capacity memory device capable of storing more data, a technology for high integration of memory devices has been studied. Accordingly, researches on flash memory have been actively conducted. Flash memory is generally classified into NAND flash memory and NOR flash memory. NOR-type flash memory has a structure in which memory cells are independently connected to bit lines and word lines, and thus have excellent random access time characteristics. On the other hand, the NAND type flash memory has excellent characteristics in terms of integration since a plurality of memory cells are connected in series and only one contact is required per cell string. Therefore, a NAND type structure is mainly used for the highly integrated flash memory.

Recently, in order to further improve the density of such flash memories, researches on multiple bit cells capable of storing a plurality of data in one memory cell have been conducted. This type of memory cell is commonly referred to as a multi-level cell (MLC). In contrast, a single bit memory cell is referred to as a single level cell (SLC).

In general, the threshold voltages Vt of the multi-level cells MLC may be distributed to a plurality of voltage values. In more detail, since 2-bit data can be programmed in a multi-level cell (MLC), one multi-level cell (MLC) has four data, that is, [11], [10], [01]. It may store any one of the. In addition, the threshold voltage Vt of the multi-level cell MLC may be changed according to the stored data. For example, referring to FIG. 1, it is assumed that threshold voltages of a memory cell exist within a range of −2.0 V or less, 0.3 to 0.8 V, 1.3 V to 1.8 V, and 2.3 V to 2.8 V, respectively. 11] corresponds to the threshold voltage of the multi-level cell (MLC) storing the data [10] or less, and the threshold voltage of the multi-level cell (MLC) storing the data [10] corresponds to 0.3 ~ 0.8V, respectively. The threshold voltage of the multi-level cell (MLC) storing the data [01] is 1.3V ~ 1.8V, the threshold voltage of the multi-level cell (MLC) storing the data is 2.3V ~ 2.8V, respectively Corresponding.

Multi-level cells (MLCs) use page buffers for fast program and read operations.

2 is a block diagram of a page buffer of a flash memory device having a conventional multi-level cell, in which only blocks related to program operations are schematically illustrated.

Referring to FIG. 2, the page buffer 10 includes a bit line selector 11, a precharge unit 12, an upper bit register 13, a lower bit register 14, a data comparator 15, and a data transfer. Circuit 16 and data path circuit 17.

A program operation process executed by the page buffer 10 will be briefly described as follows. First, the upper bit register 13 and the lower bit register 14 are respectively initialized to the set initial values. In addition, input data D1 is stored in the upper bit register 13, and the data transfer circuit 16 indicates the input data D1 received from the upper bit register 13 by a dotted line 'D'. As such, transfer to the lower bit register 14. As a result, the lower bit register 14 stores the data D1. The data path circuit 17 outputs the data D1 received from the lower bit register 14 to the sensing node SO. At this time, one of the bit lines BLe and BLo is connected to the sensing node SO by the bit line selector 11. As a result, the input data D1 is programmed to the multi-level cell connected to the bit line BLe or BLo through the bit line BLe or BLo connected to the sensing node SO. Through the above-described process, a program operation of lower bit data in the multi-level cell is completed. In the process of programming upper bit data in the multi-level cell, as indicated by the dotted line 'D', after the input data D2 is stored in the upper bit register 13, the data transfer circuit 16 Is passed to the lower bit register 14. Thereafter, the lower bit data of the multi-level cell connected to the bit line BLe or BLo is read and stored in the lower bit register 14. Thereafter, the data inputted to the upper bit register 13 and the data stored in the lower bit register 14 are compared by the data comparator 15 so that the upper bit data is connected to the bit line BLe or BLo. To program. Therefore, there is a problem that the program transfer time is increased through several steps of the data transfer process, and the transistors required are increased.

Therefore, according to the present invention, after inputting the data to be programmed into the upper bit register of the page buffer, the lower bit data read from the memory cell is stored in the lower bit register, the data to be programmed is transferred to the lower bit register, and the data of the upper bit register is transferred. By verifying the program by performing a verify operation in the middle of programming to the memory cell, the program time is reduced by omitting the step of retransmitting from the lower bit register to the upper bit register.

In addition, it reduces the area occupied by the page buffer and reduces the amount of current consumed by reducing the transistors required for data transmission and the transistors required for initializing the registers and the transistors for comparing data.

A page buffer of a flash memory device according to the present invention is connected to the even and odd bit lines of a memory cell array having a multi-level cell to supply a verify signal to the even and odd bit lines of the memory cell array by a discharge signal. A verification signal supply unit configured to be connected between the verification signal supply unit and the sensing node to connect the bit line and the sensing node by a bit line selection signal, and higher bit data connected to the sensing node and the input / output terminal. And an upper bit register for programming upper bit data and a lower bit register connected to the sensing node and an input / output terminal in parallel with the upper bit register to control program progress during lower bit data reading and upper bit program operation. do.

A program method of a flash memory device according to the present invention is a method of controlling a program operation of a page buffer of a flash memory device including a plurality of multi-level cells connected to at least one pair of bit lines, in response to data input signals. Storing upper bit data in an upper bit register; transmitting and storing the upper bit data stored in the upper bit register to a lower bit register; and in response to bit line selection signals and verify voltage signals, Selecting one of a pair of bit lines, connecting the selected bit line to a sense node, programming the high bit data stored in the high bit register into the multi level cell, and the multi level cell. Reading the data of the data and storing the data in the lower bit register, and According to the data value stored in the low-order bit register group and a step of controlling the potential of the sense node re-performed, or to interrupt the program of the higher-bit data.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 is a page buffer circuit diagram of a flash memory device according to an exemplary embodiment.

The page buffer includes a verify signal supply unit 110, a bit line selector 120, a precharge unit 130, an upper bit register 140, and a lower bit register 150.

The verify signal supply unit 110 includes NMOS transistors N111 and N112 connected in series between the even bit line BLe and the odd bit line BLO. The NMOS transistors N111 and N112 are turned on in response to the verify voltage signals VBLe and VBLo, and the verify signal VIRPWR is applied to the bit lines BLe and BLo.

The bit line selector 120 includes NMOS transistors N121 and N122 connected between the bit lines BLe and BLo and the sensing node SO. In response to the bit line selection signals BLSHFe and BLSHFo, the NMOS transistors N121 and N122 are turned on to connect the bit lines BLe and BLo and the sensing node SO.

Free car portion 130 is composed of a power supply terminal (V _DD) and the sense node PMOS transistor (P131) connected between the connection between the (SO) and the power supply terminal (V _DD) and the sense node (SO). The PMOS transistor P131 is turned on in response to the precharge signal PRECHSO_N to apply the power supply voltage V _DD to the sensing node SO.

The upper bit register 140 includes an upper bit latch circuit 141 and a plurality of NMOS transistors N141 to N145. The upper bit latch circuit 141 consists of two inverters connected in parallel in a reverse direction to temporarily store input data. The NMOS transistor N143 is connected between the input / output terminal Q and the node QAb of the upper bit latch circuit 141 and turned on in response to the data input signal DI to connect the node QAb and the input / output terminal Q. Connect. The NMOS transistor N144 is connected between the input / output terminal Q and the node QA of the upper bit latch circuit 141 and is turned on in response to the inverted data input signal nDI so that the node QA and the input / output terminal Q are turned on. Connect it. The NMOS transistors N141 and N142 are connected in series between the node between the input / output terminal Q and the NMOS transistors N143 and N144 and the ground power supply Vss. The NMOS transistor N141 is turned on according to the potential of the sensing node SO, and the NMOS transistor N142 is turned on in response to the latch signal LATCH, so that the NMOS transistor N143 and the ground power source Vss and the node when the NMOS transistor N143 is turned on. Connect QAb).

The lower bit register 150 includes a lower bit latch circuit 151 and a plurality of NMOS transistors N151 to N156. The low bit latch circuit 151 consists of two inverters connected in reverse parallel to temporarily store input data. The NMOS transistors N151 and N152 are connected in series between the sense node SO and the ground power supply Vss. The NMOS transistor N151 is turned on according to the potential of the node QB, and the NMOS transistor N152 is turned on by the selection signal SELECT to connect or disconnect the sensing node SO and the ground power supply Vss. The NMOS transistors N153 and N155 are connected in series between the node QBb of the lower bit latch circuit 151 and the input / output terminal Q. The NMOS transistor N153 is turned on in response to the second lower bit signal, and the NMOS transistor N155 is turned on in response to the lower bit pass signal LSBPASS to connect the input / output terminal Q and the node QBb. The NMOS transistors N154 and N156 are connected in series between the node QB of the low bit latch circuit 151 and the ground power supply Vss. The NMOS transistor N154 is turned on in response to the first lower bit signal, and the NMOS transistor N156 is turned on according to the potential of the sensing node SO to connect the ground power source Vss and the node QB.

A process of reading data using the page buffer of the flash memory device configured as described above will now be described in detail.

For example, a process of reading data to a multi-level cell connected to an even bit line BLe will be described below.

1) Read low bit data

The low level precharge signal PRECHSO_N is applied to the precharge unit 130 to turn on the PMOS transistor P131. Therefore, the power supply voltage V _DD is applied to the sensing node SO, and the sensing node SO is precharged to a high level. Accordingly, the NMOS transistor N156 of the lower bit register 150 is turned on according to the potential of the high level sense node SO. In this case, the second lower bit signal LSB2 is applied to the lower bit register 150 to turn on the NMOS transistor N153. Therefore, the node QBb of the lower bit latch 151 and the ground power supply Vss are connected so that the potential of the node QBb becomes a low level and the potential of the node QB becomes a high level.

The low level precharge signal PRECHSO_N is applied to the precharge unit 130 to turn on the PMOS transistor P131. Therefore, the power supply voltage V _DD is applied to the sensing node SO, and the sensing node SO is precharged to a high level. Thereafter, an even bit line select signal BLSHFe is applied to the bit line selector 120 to turn on the NMOS transistor N121. Therefore, the sensing node SO is connected to the even bit line BLe. Thereafter, the first reference voltage REFL1 (−0.2 to 0.3V) of FIG. 1 is applied to the selected word lines WL0 to WL31 of the memory cell 100. As a result, the potential of the sensing node SO is maintained as it is or discharged to a low level according to the cell state of the connected memory cell array 100. If the data stored in the cell is '11', the potential of the sensing node SO is discharged to a low level. If the low bit data stored in the cell is '10', '00', or '01', the sensing node SO ) Is maintained at a high level. Thereafter, the first lower bit signal LSB1 is applied to the lower bit register 151 to turn on the NMOS transistor N154. Therefore, when the cell data is '10', '00', or '01', the NMOS transistor N156 is turned on by the potential of the sensing node SO so that the potential of the node QB of the lower bit latch 151 is low. It becomes a level. On the other hand, when the cell data is '11', the potential of the node QB is maintained at a high level.

Thereafter, the second reference voltage REFL1 (1.8 to 2.3V) of FIG. 1 is applied to the word lines WL0 to WL31. Thus, when the cell state is '10', the potential of the sensing node SO is maintained at a high level and discharged to a low level in the remaining states. At this time, the second lower bit signal LSB2 is applied to the NMOS transistor N153 so that the NMOS transistor N153 is turned on. For this reason, the potential change of the node QB according to the cell state is shown in Table 1 below.

Cell status 11 10 01 00 Node (QB) 0 0 One One

2) Read High Bit Data

The low level precharge signal PRECHSO_N is applied to the precharge unit 130 to turn on the PMOS transistor P131. Therefore, the power supply voltage V _DD is applied to the sensing node SO, and the sensing node SO is precharged to a high level. The NMOS transistor N141 is turned on by the potential of the sensing node SO. Thereafter, the latch signal LATCH is applied to the upper bit register 140 to turn on the NMOS transistor N142, and the inverted data input signal nDI is applied to turn on the NMOS transistor N144. Therefore, the potential of the node QA of the upper bit latch 141 becomes the low level, and the node QAb becomes the high level.

The low level precharge signal PRECHSO_N is applied to the precharge unit 130 to turn on the PMOS transistor P131. Therefore, the power supply voltage V _DD is applied to the sensing node SO, and the sensing node SO is precharged to a high level. Thereafter, an even bit line select signal BLSHFe is applied to the bit line selector 120 to turn on the NMOS transistor N121. Therefore, the sensing node SO is connected to the even bit line BLe. Thereafter, the third reference voltage REFLM 0.8 to 1.3V of FIG. 1 is applied to the selected word lines WL0 to WL31 of the memory cell 100. As a result, the potential of the sensing node SO is maintained as it is or discharged to a low level according to the cell state of the connected memory cell array 100. If the data stored in the cell is '11' or '10', the potential of the sensing node SO is discharged to the low level, and if the low bit data stored in the cell is '00' or '01', the sensing node SO ) Is maintained at a high level. Thereafter, the latch signal LATCH is applied to the upper bit register 140 to turn on the NMOS transistor N142. Therefore, when the cell data is '00' or '01', the NMOS transistor N141 is turned on by the potential of the sensing node SO so that the potential of the node QA of the upper bit latch 141 is at a high level. On the other hand, when the cell data is '11' or '10', the potential of the node QA maintains a low level.

 The potential change of the node QA according to the cell state is shown in Table 2 below.

Cell status 11 10 01 00 Node (QA) 0 0 One One

3) Low bit data program

The low level precharge signal PRECHSO_N is applied to the precharge unit 130 to turn on the PMOS transistor P131. Therefore, the power supply voltage V _DD is applied to the sensing node SO, and the sensing node SO is precharged to a high level. The NMOS transistor N141 is turned on by the potential of the sensing node SO. Thereafter, the latch signal LATCH is applied to the upper bit register 140 to turn on the NMOS transistor N142, and the inverted data input signal nDI is applied to turn on the NMOS transistor N144. Therefore, the potential of the node QA of the upper bit latch 141 becomes the low level, and the node QAb becomes the high level.

When the program data is '1', the data input signal DI is applied to turn on the NMOS transistor N143. Therefore, the node QAb and the input / output terminal Q are connected so that the potential of the node QAb becomes low level, and the node QA becomes high level. When the program data is '0', the inversion data input signal nDI is applied to turn on the NMOS transistor N144. Therefore, the node QA and the input / output terminal Q are connected so that the potential of the node QA becomes low level, and the node QAb becomes high level.

The low level precharge signal PRECHSO_N is applied to the precharge unit 130 to turn on the PMOS transistor P131. Therefore, the power supply voltage V _DD is applied to the sensing node SO, and the sensing node SO is precharged to a high level.

The verification voltage signals VBLe and VBLo are applied to the verification signal supply unit 110 at a high level to turn on the NMOS transistors N111 and N112. Therefore, the verify voltage VIRPWR is applied to the even bit line BLe and the odd bit line BLO, and the even bit line BLe and the odd bit line BLO are precharged to a high level. Thereafter, the verify voltage signal VBLe is applied at a low level to block the verify voltage VIRPWR applied to the even bit line BLe. The verify voltage signal VBLo is maintained at a high level so that the verify bit VIRPWR is continuously applied to the odd bit line BLo.

The even bit line selection signal BLSHFe is applied to the bit line selection unit 120 to turn on the NMOS transistor N121. Therefore, the even bit line BLe and the sensing node SO are connected. Thereafter, the program signal PROG is applied to the upper bit register 140 to turn on the NMOS transistor N145. Therefore, the sensing node SO and the node QA of the upper bit latch 141 are connected. According to the potential of the node QA, the potentials of the sensing node SO and the even bit line BLe are maintained as they are or discharged to a low level. Thereafter, a program voltage is applied to the word lines WL0 to WL31 of the memory cell 100 to program the lower bit data into the memory cell 100.

4A through 4C are timing diagrams of operation signals when higher bit data is programmed in a page buffer according to the present invention. A higher bit data program operation of the page buffer according to the present invention will be described in detail with reference to FIGS. 4A to 4C as follows.

4) High bit data program

4-1) Data input section

Referring to FIG. 4A, the PMOS transistor P131 is turned on by applying the low level precharge signal PRECHSO_N to the precharge unit 130. Therefore, the power supply voltage V _DD is applied to the sensing node SO, and the sensing node SO is precharged to a high level. Therefore, the NMOS transistor N141 of the upper bit register 140 is turned on according to the potential of the high level sense node SO. At this time, the latch signal LATCH is applied to the upper bit register 140 to turn on the NMOS transistor N142. When the input data is '1', the data input signal DI is applied to the upper bit register 140 to turn on the NMOS transistor N143. Accordingly, the node QAb of the upper bit latch 141 and the ground power supply Vss are connected so that the potential of the node QAb becomes low level, and the potential of the node QA becomes high level. On the other hand, when the input data is '0', the inversion data input signal nDI is applied to the upper bit register 140 and the NMOS transistor N144 is turned on. Accordingly, the node QA of the upper bit latch 141 and the ground power supply Vss are connected to each other so that the potential of the node QA becomes a low level and the potential of the node QAb becomes a high level.

4-2) Data Transmission Section

Referring to FIG. 4B, the low level precharge signal PRECHSO_N is applied to the precharge unit 130 to turn on the PMOS transistor P131. Therefore, the power supply voltage V _DD is applied to the sensing node SO, and the sensing node SO is precharged to a high level. Accordingly, the NMOS transistor N156 of the lower bit register 150 is turned on according to the potential of the high level sense node SO. At this time, the first lower bit signal LSB2 is applied to the lower bit register 150 to turn on the NMOS transistor N153. Therefore, the ground power supply Vss and the node QBb of the lower bit latch 151 are connected so that the potential of the node QBb becomes low level and the potential of the node QB becomes high level.

The low level precharge signal PRECHSO_N is applied to the precharge unit 130 to turn on the PMOS transistor P131. Therefore, the power supply voltage V _DD is applied to the sensing node SO, and the sensing node SO is precharged to a high level. Thereafter, the program signal PROG is applied to the upper bit register 140 to turn on the NMOS transistor N145. Therefore, the sensing node SO and the node QA are connected so that the potential of the sensing node SO is maintained at a high level or discharged to a low level according to the potential of the node QA. As a result, the NMOS transistor N156 of the lower bit register 150 is turned on or turned off according to the potential of the sensing node SO. Thereafter, the first lower bit signal LSB1 is applied to the lower bit register 150 to turn on the NMOS transistor N154. Therefore, when the potential of the node QA is at the high level, the NMOS transistor N156 is turned on according to the high level of the sensing node SO, and the node QB and the ground power source Vss are connected to each other so that the node QB is connected. The potential goes low. On the other hand, when the potential of the node QA is at the low level, the NMOS transistor N156 is turned off according to the low level of the sensing node SO potential so that the potential of the node QB is maintained at the high level.

4-3) Upper bit data program section

Referring to FIG. 4C, the PMOS transistor P131 is turned on by applying the low level precharge signal PRECHSO_N to the precharge unit 130. Therefore, the power supply voltage V _DD is applied to the sensing node SO, and the sensing node SO is precharged to a high level.

The verification voltage signals VBLe and VBLo are applied to the verification signal supply unit 110 at a high level to turn on the NMOS transistors N111 and N112. Therefore, the verify voltage VIRPWR is applied to the even bit line BLe and the odd bit line BLO, and the even bit line BLe and the odd bit line BLO are precharged to a high level. Thereafter, the verify voltage signal VBLe is applied at a low level to block the verify voltage VIRPWR applied to the even bit line BLe. The verify voltage signal VBLo is maintained at a high level so that the verify bit VIRPWR is continuously applied to the odd bit line BLo.

The even bit line selection signal BLSHFe is applied to the bit line selection unit 120 to turn on the NMOS transistor N121. Therefore, the even bit line BLe and the sensing node SO are connected. Thereafter, the program signal PROG is applied to the upper bit register 140 to turn on the NMOS transistor N145. Therefore, the sensing node SO and the node QA of the upper bit latch 141 are connected. According to the potential of the node QA, the potentials of the sensing node SO and the even bit line BLe are maintained as they are or discharged to a low level. Thereafter, a program voltage is applied to the word lines WL0 to WL31 of the memory cell 100 to program higher bit data into the memory cell 100.

After programming, the state of the lower bit page (LSB page) is verified to determine whether to continue or stop the higher bit program operation.

0.3 is applied to the word lines WL0 to WL31 of the memory cell 100 to distinguish whether the state of the memory cell 100 is '11' or '10', and then the lower bit page is read. Since the low bit read method has been described above, it will be omitted. After reading, when the potential of the node QB of the lower bit latch 151 is at a high level, the NMOS transistor N151 is turned on and the potential of the sensing node SO is at a low level. At this time, the NMOS transistor N152 is turned on by applying the selection signal SELECT to the lower bit register 150. Therefore, the sensing node SO and the ground power supply Vss are connected so that the potential of the sensing node SO is discharged to a low level. Therefore, the program operation of the memory cell 100 continues. On the other hand, after reading, when the potential of the node QB of the lower bit latch 151 is at the low level, the NMOS transistor N151 is turned off and the potential of the sensing node SO is at the high level. Therefore, the program operation of the memory cell 100 no longer proceeds.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, after inputting data to be programmed into the upper bit register of the page buffer, the lower bit data read from the memory cell is stored in the lower bit register, and the data to be programmed is transferred to the lower bit register, In the middle of programming the data of the register to the memory cell, a verification operation is performed to confirm whether the program is programmed, thereby reducing the program step by omitting the retransmission from the lower bit register to the upper bit register.

In addition, the transistors required for data transfer and transistors used to compare data and transistors required for initialization may be reduced, thereby reducing the area occupied by the page buffer and reducing the amount of current consumed.

Claims (10)

A verify signal supply unit connected to the even and odd bit lines of the memory cell array having the multi-level cells and supplying a verify signal to the even and odd bit lines of the memory cell array by a discharge signal; A bit line selection unit connected between the verification signal supply unit and the sensing node to connect the bit line and the sensing node in response to a bit line selection signal; An upper bit register coupled to the sensing node and an input / output terminal for reading upper bit data and programming upper bit data; And And a lower bit register coupled to the sense node and the input / output terminal in parallel with the upper bit register to control a program progress during a lower bit data read and an upper bit program operation. The method of claim 1, And the page buffer further comprises a precharge unit connected between a power supply terminal and the sensing node to maintain the predetermined potential by the precharge signal by a precharge signal. The method of claim 1, And the verify signal supply unit comprises a transistor configured to apply the verify signal to a bit line in response to the discharge signal. The method of claim 1, And the bit line selector comprises a transistor connecting the bit line and the sensing node in response to the bit line select signal. The method of claim 1, And the higher bit comprises a latch for storing data. The method of claim 1, The lower bit register includes a latch for storing data and a program control circuit for controlling a potential of the sensing node to a high level or a low level according to a data value stored in the latch during an upper bit program operation. . A method for controlling a program operation of a page buffer of a flash memory device including a plurality of multi-level cells connected to at least one pair of bit lines, Storing higher bit data in an upper bit register in response to the data input signals; Transmitting and storing the upper bit data stored in the upper bit register to a lower bit register; In response to bit line select signals and verify voltage signals, selecting one of the pair of bit lines and coupling the selected bit line to a sense node; Programming the higher bit data stored in the higher bit register into the multi-level cell; Reading data of the multi-level cell and storing the data in the lower bit register; And Controlling the potential of the sensing node according to the data value stored in the lower bit register to re-execute or stop the program of the upper bit data. The method of claim 7, wherein Re-programming or interrupting the higher bit data may include reprogramming the higher bit data when the higher bit data and the data read from the multi-level cell are different from each other. And stopping the program of the higher bit data when the data read from are the same. The method of claim 7, wherein The reading of the data stored in the multi-level cell into the lower bit register may include applying a predetermined voltage to a word line of the multi-level cell and performing a read operation to distinguish data stored in the multi-level cell. Program operation method of device. The method of claim 9, Program operation of a flash memory device for applying the predetermined voltage to the word line to distinguish data stored in the multi-level cell Way.

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