KR20070109174A - Method of reading a flash memory device - Google Patents

Abstract

A method of reading a flash memory device is provided to prevent the decrease of a precharge level by a threshold voltage of a transistor driven according to a loading between bit lines and a bit line selection signal, by precharging a bit line by applying a voltage to a triple P well of a cell without precharging the bit line through the transistor driven according to a bit line selection signal. A bit line connected to a memory cell array is discharged. The bit line is precharged by applying a voltage to a triple P well of the memory cell array. The state of the cell is sensed by detecting a potential of the bit line connected to the selected cell. The voltage applied to the triple P well is a power supply voltage. While the power supply voltage is applied to the triple P well, the power supply voltage is applied to a common source line of the memory cell array.

Description

Method of reading a flash memory device

1 is a circuit diagram of a cell string for explaining the configuration of a NAND type flash memory device.

2 is a configuration diagram of a page buffer applied to a NAND type flash memory device.

3 is a circuit diagram of a bit line selector included in a page buffer.

4 is a circuit diagram for explaining the configuration of a page buffer of a NAND type flash memory device to which the present invention is applied.

5 is an operation waveform diagram illustrating a method of reading a NAND type flash memory device according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of reading a flash memory device. In particular, a NAND type flash memory capable of reducing precharge time and reducing precharge level by applying a voltage to a triple P well to precharge a bit line It relates to a method of reading a device.

Recently, there is an increasing demand for semiconductor memory devices that can be electrically programmed and erased and that do not require a refresh function to rewrite data at regular intervals. In addition, in order to develop a large-capacity memory device capable of storing a large amount of data, a high integration technology of memory cells has been developed. A NAND type flash memory device is developed in which a plurality of cells are connected in series to form a string and two strings share a contact for high integration of memory cells. It became.

FIG. 1 is a circuit diagram for describing a configuration of a cell string of a general NAND type flash memory device.

Referring to FIG. 1, cell strings 101 and 102 are configured by connecting a plurality of cells in series for storing data. A drain select transistor 110 is configured between the cell strings 101 and 102 and the even bit lines and the odd bit lines BLe and BLo, and selects a source between the cell strings 101 and 102 and the common source line CSL. Transistor 120 is configured. The drain select transistor 110 is commonly connected to the drain select line DSL, and the source select transistor 120 is commonly connected to the source select line SSL. In addition, adjacent even and odd bit lines BLe and BLo are commonly connected to the page buffer. Cells connected to the even bit line BLe are assigned even numbers 0, 2, 6, ..., 60, 62 from cells adjacent to the source select line SSL, and are connected to the odd bit line BLO. The assigned cells are assigned odd numbers 1, 3, 5, ..., 61, 63 from cells adjacent to the source select line SSL. Meanwhile, a predetermined bias is applied to the cell gate through the word line WL for a predetermined operation of the cell, and a predetermined bias is applied to the drain through the even bit line BLe or the odd bit line BLo, and common. A predetermined bias is applied to the source through the source line CSL. In addition, a cell of a NAND type flash memory device includes a gate in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked in a predetermined region on a semiconductor substrate, and junctions are formed on both sides of the gate.

The NAND type flash memory device configured as described above is programmed and erased by controlling a threshold voltage of a memory cell while injecting or emitting electrons into a floating gate using an F-N tunneling scheme. Thus, an erased cell has a negative threshold voltage at which electrons of the floating gate are emitted, and a programmed cell has a positive threshold voltage by injecting electrons into the floating gate. However, in the case of a NAND type flash memory device, a defect due to a charge gain or a charge loss occurs, and various verifications are performed with respect to this characteristic. A page buffer is used to verify this normal program and erase, that is, read the state of the cell.

The page buffer receives a large amount of data from an input / output pad and provides the memory cells or stores and outputs data of the memory cells. In general, the page buffer is generally composed of a single register for temporarily storing data, but recently, in a NAND type flash memory device, a dual register is used to increase program speed when programming large data.

2 is a block diagram illustrating a page buffer of a dual register structure of a general NAND type flash memory device.

Referring to FIG. 2, the page buffer includes a bit line selector 22 connected between even and odd bit lines BLe and BLo and a sense node SO of a memory cell array 21 having a plurality of memory cells. A precharge unit 23 connected to the node SO, a main register 24 and a cache register 25 connected in parallel between the sensing node SO and the input / output terminal YA are included.

The bit line selector 22 selects an even bit line Ble or an odd bit line BLo according to a selection signal in a program operation, a read operation, or a verify operation, and connects the even bit line BLo to the sensing node SO.

The precharge unit 23 precharges the potential of the sensing node SO to a predetermined potential level.

The main register 24 and the cache register 25 temporarily store data input through the input / output terminal YA during programming, and then transfer them to the selected bit line through the sensing node SO or bit lines during a read or verify operation. Temporarily store the cell data contained in the and output it through the input / output terminal YA.

3 is a circuit diagram of a bit line selection unit constituting a page buffer of a NAND type flash memory device.

Referring to FIG. 3, the first and second NMOS transistors N31 and N32 are driven according to the even and odd discharge signals DISCHe and DISCHo, respectively, so that the verify voltage VIRPWR is driven to the even bit line BLe or the odd bit. The cell string of the memory cell array connected to the line BLo is applied. The third and fourth NMOS transistors N33 and N34 are driven according to the even and odd bit line selection signals BSLe and BSLo, respectively, to connect the bit lines of the memory cell array and the sensing node SO.

In order to read the state of the selected cell of the NAND-type flash memory device using the page buffer configured as described above, the selected bit line is subjected to three steps of precharge, evaluation, and sensing. This will be described with reference to FIGS. 2 and 3 as follows.

In order to precharge the bit line, a voltage of a predetermined level is supplied from the precharge unit 23 to the sensing node SO, and then the bit line selection signal BSLe is applied at the level of the first voltage V1. Accordingly, the voltages V1 -Vt obtained by subtracting the threshold voltage Vt of the third NMOS transistor N33 from the first voltage V1 are applied to the selected bit line BLe. Then, the potential of the sensing node SO is adjusted according to the state of the cell. In the case of an erase cell, the sensing node SO maintains a low level potential, and in the case of a program cell, the sensing node SO has a high level. Maintain the potential. Then, the potential level of the sensing node SO is stored in the main register 24 of the page buffer to sense the state of the cell.

As described above, various problems occur when the bit line is first precharged to a level of V1 -Vt. One of them is the loading problem of bitlines. The loading of the bit line is increased according to the resistance of the metal material constituting the bit line and the capacitance with the adjacent bit line. However, since the length of the metal wiring increases as the device shrinks, loading between the bit lines increases, making it difficult to precharge the bit lines through the NMOS transistor driven according to the bit line selection signal BSL. In addition, as the device shrinks, the threshold voltage increases when the bit line is precharged to a level of V1 -Vt.

On the other hand, a transistor driven according to the bit line selection signal BSL can use a high voltage NMOS transistor. However, as the device shrinks, the pitch of the cell decreases, so that the width of the high voltage NMOS transistor driven according to the corresponding bit line selection signal decreases and the threshold voltage increases. As a result, a back bias effect is applied to increase the threshold voltage. In general, when the width of the transistor driven according to the bit line selection signal BSL is 1 and the bias of the bit line is 1V, the threshold voltage of the transistor is 3V or more. Therefore, in order to precharge 1V or more to the bit line, at least 4V or more is required. V1 is required. This requires another pump, which is a serious problem.

For this reason, the precharge time of the bit line requires a time considering the V1 pumping time and the bit line loading, and ultimately, the read operation time is inevitably increased.

An object of the present invention is to provide a method of reading a flash memory device that can reduce the read operation time.

Another object of the present invention is to precharge a bit line by applying a predetermined voltage to a triple P well of a cell without precharging the bit line through a transistor driven according to a bit line selection signal, thereby reducing the size of the device between bit lines. The present invention provides a method of reading a flash memory device capable of preventing the precharge level from being reduced by a threshold voltage of a transistor driven according to a loading and bit line selection signal.

According to an embodiment of the present disclosure, a method of reading a flash memory device may include: discharging a bit line connected to a memory cell array; Precharging the bit line by applying a predetermined voltage to a triple P well of the memory cell array; And sensing a state of the cell by detecting a potential of the bit line to which the selected cell is connected.

The voltage applied to the triple P well is a power supply voltage, and the common source line constituting the memory cell array applies or floats the power supply voltage while the power supply voltage is applied to the triple P well.

In addition, a method of reading a flash memory device according to another embodiment of the present invention includes a plurality of cell strings configured by connecting a plurality of cells in series; A plurality of drain select transistors connected between the cell string and the drain and driven according to a signal applied through a drain select line; A plurality of source select transistors connected between the cell string and the common source and driven according to a signal applied through a source select line; A bit line connected to the drain; A first transistor for supplying a verify signal to a memory cell array through the bit line according to a first control signal; And a second transistor for connecting the memory cell array and a first node through the bit line according to a second control signal, and driving the first transistor according to the first control signal to the bit line. Supplying a verify signal to discharge the bit line; Precharging the bit line by applying a predetermined voltage to a triple P well of the memory cell string; Stopping supply of the predetermined voltage supplied to the triple P well and evaluating the selected cell; And sensing the state of the cell by detecting the potential of the bit line to which the selected cell is connected by driving the second transistor according to the second signal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 4 is a circuit diagram illustrating a configuration of a page buffer used in a read method of a NAND type flash memory device according to an embodiment of the present invention. The main register in the page buffer of a dual register structure having a main register and a cache register. A circuit diagram is shown.

Referring to FIG. 4, the bit line selector 420 includes a plurality of transistors, and the first and second NMOS transistors N401 and N402 may be formed according to the even and odd discharge signals DISCHe and DISCHo, respectively. The driving voltage is applied to the memory cell string of the memory cell array 410 connected to the even bit line BLe or the odd bit line BLO. The third and fourth NMOS transistors N403 and N404 are driven according to the even and odd bit line selection signals BSLe and BSLo, respectively, to connect the bit lines of the memory cell array 410 and the sensing node SO.

The PMOS transistor P401 is driven according to the precharge signal PRECHb to supply predetermined power to the sensing node S0.

The fifth NMOS transistor N405 connects the sensing node SO and the output node QAb of the latch 430 according to the copyback signal COPYBACK during the copyback program. The latch 430 temporarily stores output data output from the memory cell array 410 and data supplied from the outside. The sixth NMOS transistor N406 is driven according to the potential of the sensing node S0, and the seventh NMOS transistor N407 is driven according to the read signal READ_L to output the node QAb and the ground terminal of the latch 430. Connect (Vss). The eighth NMOS transistor N408 is driven according to the signal DI_L to connect the input / output terminal YA and the output node QAb of the latch 430, and the ninth NMOS transistor N409 according to the signal nDI_L. It is driven to connect the input / output terminal (YA) and the input node (QA) of the latch 430. The tenth NMOS transistor N410 is driven according to the reset signal RESET_L to initialize the latch 430. The eleventh NMOS transistor N411 is driven according to the signal PROGRAM_L during a program operation so that information to be programmed is transmitted to the selected bit line. The twelfth NMOS transistor N412 is driven according to the signal PBDO_L to output the potential of the program node NA. Inverter I401 also inverts the potential of output node QAb of latch 430 and transfers it to program node NA.

FIG. 5 is a waveform diagram illustrating a signal applied to a bit line selector and a cell string when a NAND type flash memory device according to an exemplary embodiment using the page buffer configured as described above is read.

A method of reading a NAND type flash memory device according to an embodiment of the present invention will be described with reference to FIGS. 4 and 5 as follows.

1) A section: discharge

Even and odd discharge signals DISCHe and DISCHo are applied at a high level to turn on the first and second NMOS transistors N101 and N102. Therefore, the potential of the verify signal VIRPWR is supplied to the bit lines BLe and BLo through the first and second NMOS transistors N401 and N402, and the verify signal VIRPWR at the time of reading maintains the potential of 0V. A voltage of 0 V is supplied to the even and odd bit lines BLe and BLo. The reset signal RESET_L is applied as a high level pulse to turn on the tenth NMOS transistor N110 to bring the node QA to a low level, thereby keeping the node QAb at a high level. Thus, latch 430 is initialized. At this time, a voltage of 0 is applied to all the word lines WL0 to WL31, and a voltage of 0 V is also applied to the drain select line DSL and the source select line SSL.

2) Section B: Precharge

The even discharge signal DISCHe is applied at a low level so that the first NMOS transistor N401 is turned off, the odd discharge signal DISCHo is maintained at a high level, and the second NMOS transistor N402 is turned on. Keep it. Since the verification voltage VIRPWR is applied in the high state of the power supply voltage Vcc level, the power supply voltage Vcc is applied to the odd bit line BLo. That is, the even bit line BLe, which is the selected bit line, is floated, and the power supply voltage Vccc is applied to the odd bit line BLO, which is the unselected bit line. At this time, 0 V is continuously applied to the selected word line Sel WL, and a read voltage Vread is applied to the unselected word line Unsel WL. Unlike the conventional method, the even and odd bit line selection signals BSLe and BSLo are applied at a level of 0 V to turn off the third and fourth NMOS transistors N403 or N404. That is, in the past, when the selected bit line selection signal, for example, the even bit line BLe, is selected, the even bit line selection signal BSLe is applied at the level of the first voltage V1. BLe and BLo) are both applied at a level of 0V. Instead, the present invention applies a power supply voltage (Vcc) to the triple P well of the cell string. Then, the power source voltage Vcc is applied to the common source line CSL or maintained in a floating state. At this time, a voltage of 0 V is also supplied to the drain select line DSL and the source select line SSL. In this case, the selected bit line BLe is applied with a voltage obtained by subtracting the back bias voltage Vfb that maintains about 0.7V from the power supply voltage Vcc. In addition, since the bit line and the triple P well are connected through drain contacts, the precharge time can be shortened compared to the conventional one because only one block of the bit line length is charged regardless of the length of the bit line or the capacitance between the bit lines.

3) Section C: Valuation

The even and odd bit line select signals BSLe and BSLo keep the low level so that the third and fourth NMOS transistors N403 and N404 remain turned off. In addition, the supply of the voltage applied to the triple P well and the common source line is stopped. Accordingly, the even bit line BLe potential is adjusted according to the state of memory cells respectively connected to the even bit line BLe. That is, when the memory cell is in the program state, the potential of the even bit line BLe maintains the potential of (Vcc-Vfb), and in the erase state, the potential of the even bit line BLe gradually increases at (Vcc-Vfb). Decreases to maintain a low level. In this case, a high level signal is applied through the drain select line DSL and the source select line SSL.

4) Section D: Cell Sensing

The even bit line selection signal BSLe is applied to a voltage VBSL lower than the power supply voltage Vcc to turn on the third NMOS transistor N403. In this case, when the memory cell is a program cell, the potential of the even bit line BLe maintains the potential of (Vcc-Vfb), and accordingly, the potential of the sensing node SO maintains the high level. However, when the memory cell is in an erased state, the potential of the even bit line BLe gradually decreases to maintain a low level, and thus the potential of the sensing node SO maintains a low level. In this state, when the read signal READ_L is applied as a pulse having a high level, when the memory cell is a program cell, the sensing node SO maintains a high level so that the sixth NMOS transistor N406 is turned on and the high pulse read signal ( The seventh NMOS transistor N407 is turned on by READ_L so that the node QAb maintains a low level and the node QA maintains a high level. In contrast, when the memory cell is an erase cell, the node QAb maintains a high level because the sense node SO maintains a low level, and the seventh NMOS transistor N407 is turned off, and the node QA maintains a low level. Will be maintained. Therefore, the potential of the node QA is detected to sense the state of the cell.

Meanwhile, in the above-described embodiment, the reading method of the NAND type flash memory device has been described as an example, but the same method may be applied to program verification or erase verification.

As described above, according to the present invention, a pre-charge of a bit line is performed by applying a predetermined voltage to a triple P well of a cell without precharging the bit line through a transistor driven according to a bit line selection signal. As a result, the precharge level can be prevented from being reduced by the threshold voltage of the transistor driven according to the inter-bit line loading and bit line selection signal. Can be.

Claims (5)

Discharging a bit line connected to the memory cell array; Precharging the bit line by applying a predetermined voltage to a triple P well of the memory cell array; And And detecting a state of the cell by detecting a potential of the bit line to which the selected cell is connected. The method of claim 1, wherein the voltage applied to the triple P well is a power supply voltage. The method of claim 1, wherein the power supply voltage is also applied to a common source line constituting the memory cell array while the power supply voltage is applied to the triple P well. The method of claim 1, wherein the common source line constituting the memory cell array is floated while the power supply voltage is applied to the triple P well. A plurality of cell strings configured by connecting a plurality of cells in series; A plurality of drain select transistors connected between the cell string and the drain and driven according to a signal applied through a drain select line; A plurality of source select transistors connected between the cell string and the common source and driven according to a signal applied through a source select line; A bit line connected to the drain; A first transistor for supplying a verify signal to a memory cell array through the bit line according to a first control signal; A second transistor for connecting the memory cell array and a first node through the bit line according to a second control signal; Driving the first transistor according to the first control signal to supply the verification signal to the bit line to discharge the bit line; Precharging the bit line by applying a predetermined voltage to a triple P well of the memory cell string; Stopping supply of the predetermined voltage supplied to the triple P well and evaluating the selected cell; And And driving the second transistor according to the second signal to detect a potential of the bit line to which the selected cell is connected to sense a state of the cell.

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