KR100938367B1 - 분기 예측 오류를 정정하는 시스템 및 방법 - Google Patents

분기 예측 오류를 정정하는 시스템 및 방법 Download PDF

Info

Publication number
KR100938367B1
KR100938367B1 KR1020077021439A KR20077021439A KR100938367B1 KR 100938367 B1 KR100938367 B1 KR 100938367B1 KR 1020077021439 A KR1020077021439 A KR 1020077021439A KR 20077021439 A KR20077021439 A KR 20077021439A KR 100938367 B1 KR100938367 B1 KR 100938367B1
Authority
KR
South Korea
Prior art keywords
pipeline
instruction
branch
instructions
branch instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020077021439A
Other languages
English (en)
Korean (ko)
Other versions
KR20070105366A (ko
Inventor
마이클 스콧 맥클베인
제프리 토드 브리지스
제임스 노리스 디펜더퍼
토마스 앤드류 사토리우스
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20070105366A publication Critical patent/KR20070105366A/ko
Application granted granted Critical
Publication of KR100938367B1 publication Critical patent/KR100938367B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • G06F9/3844Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854Instruction completion, e.g. retiring, committing or graduating
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
KR1020077021439A 2005-02-18 2006-02-17 분기 예측 오류를 정정하는 시스템 및 방법 Expired - Fee Related KR100938367B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/061,981 US7152155B2 (en) 2005-02-18 2005-02-18 System and method of correcting a branch misprediction
US11/061,981 2005-02-18

Publications (2)

Publication Number Publication Date
KR20070105366A KR20070105366A (ko) 2007-10-30
KR100938367B1 true KR100938367B1 (ko) 2010-01-22

Family

ID=36685580

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020077021439A Expired - Fee Related KR100938367B1 (ko) 2005-02-18 2006-02-17 분기 예측 오류를 정정하는 시스템 및 방법

Country Status (8)

Country Link
US (1) US7152155B2 (https=)
EP (1) EP1849063B1 (https=)
JP (1) JP4763727B2 (https=)
KR (1) KR100938367B1 (https=)
CN (1) CN100538629C (https=)
IL (1) IL185301A0 (https=)
MX (1) MX2007010048A (https=)
WO (1) WO2006089189A2 (https=)

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7254700B2 (en) * 2005-02-11 2007-08-07 International Business Machines Corporation Fencing off instruction buffer until re-circulation of rejected preceding and branch instructions to avoid mispredict flush
US7949861B2 (en) 2005-06-10 2011-05-24 Qualcomm Incorporated Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline
US8327115B2 (en) 2006-04-12 2012-12-04 Soft Machines, Inc. Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode
WO2008061154A2 (en) 2006-11-14 2008-05-22 Soft Machines, Inc. Apparatus and method for processing instructions in a multi-threaded architecture using context switching
US7624254B2 (en) * 2007-01-24 2009-11-24 Qualcomm Incorporated Segmented pipeline flushing for mispredicted branches
US8601234B2 (en) * 2007-11-07 2013-12-03 Qualcomm Incorporated Configurable translation lookaside buffer
US8261025B2 (en) 2007-11-12 2012-09-04 International Business Machines Corporation Software pipelining on a network on chip
US8874885B2 (en) * 2008-02-12 2014-10-28 International Business Machines Corporation Mitigating lookahead branch prediction latency by purposely stalling a branch instruction until a delayed branch prediction is received or a timeout occurs
US8443227B2 (en) * 2008-02-15 2013-05-14 International Business Machines Corporation Processor and method for workaround trigger activated exceptions
US7890739B2 (en) * 2008-02-19 2011-02-15 Oracle America, Inc. Method and apparatus for recovering from branch misprediction
US20090260013A1 (en) * 2008-04-14 2009-10-15 International Business Machines Corporation Computer Processors With Plural, Pipelined Hardware Threads Of Execution
US8423715B2 (en) 2008-05-01 2013-04-16 International Business Machines Corporation Memory management among levels of cache in a memory hierarchy
US8271765B2 (en) * 2009-04-08 2012-09-18 International Business Machines Corporation Managing instructions for more efficient load/store unit usage
CN103250131B (zh) 2010-09-17 2015-12-16 索夫特机械公司 包括用于早期远分支预测的影子缓存的单周期多分支预测
TWI541721B (zh) 2010-10-12 2016-07-11 軟體機器公司 使用指令序列緩衝器來增強分支預測效能的方法、系統及微處理器
US9733944B2 (en) 2010-10-12 2017-08-15 Intel Corporation Instruction sequence buffer to store branches having reliably predictable instruction sequences
WO2012135031A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
KR101966712B1 (ko) 2011-03-25 2019-04-09 인텔 코포레이션 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 메모리 프래그먼트
CN103562866B (zh) 2011-03-25 2018-03-30 英特尔公司 用于通过使用由可分割引擎实例化的虚拟核来支持代码块执行的寄存器文件段
US8862861B2 (en) 2011-05-13 2014-10-14 Oracle International Corporation Suppressing branch prediction information update by branch instructions in incorrect speculative execution path
US8886920B2 (en) 2011-05-13 2014-11-11 Oracle International Corporation Associating tag to branch instruction to access array storing predicted target addresses for page crossing targets for comparison with resolved address at execution stage
EP2710481B1 (en) 2011-05-20 2021-02-17 Intel Corporation Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
WO2012162189A1 (en) 2011-05-20 2012-11-29 Soft Machines, Inc. An interconnect structure to support the execution of instruction sequences by a plurality of engines
IN2014CN03678A (https=) 2011-11-22 2015-09-25 Soft Machines Inc
WO2013077876A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. A microprocessor accelerated code optimizer
US8930674B2 (en) 2012-03-07 2015-01-06 Soft Machines, Inc. Systems and methods for accessing a unified translation lookaside buffer
US9916253B2 (en) 2012-07-30 2018-03-13 Intel Corporation Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
US9710399B2 (en) 2012-07-30 2017-07-18 Intel Corporation Systems and methods for flushing a cache with modified data
US9229873B2 (en) 2012-07-30 2016-01-05 Soft Machines, Inc. Systems and methods for supporting a plurality of load and store accesses of a cache
US9740612B2 (en) 2012-07-30 2017-08-22 Intel Corporation Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
US9678882B2 (en) 2012-10-11 2017-06-13 Intel Corporation Systems and methods for non-blocking implementation of cache flush instructions
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
WO2014151018A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for executing multithreaded instructions grouped onto blocks
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
EP2972836B1 (en) 2013-03-15 2022-11-09 Intel Corporation A method for emulating a guest centralized flag architecture by using a native distributed flag architecture
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US9792252B2 (en) 2013-05-31 2017-10-17 Microsoft Technology Licensing, Llc Incorporating a spatial array into one or more programmable processor cores
US9672298B2 (en) * 2014-05-01 2017-06-06 Oracle International Corporation Precise excecution of versioned store instructions
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US10169044B2 (en) 2015-06-26 2019-01-01 Microsoft Technology Licensing, Llc Processing an encoding format field to interpret header information regarding a group of instructions
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US9952867B2 (en) 2015-06-26 2018-04-24 Microsoft Technology Licensing, Llc Mapping instruction blocks based on block size
US9720693B2 (en) 2015-06-26 2017-08-01 Microsoft Technology Licensing, Llc Bulk allocation of instruction blocks to a processor instruction window
US9946548B2 (en) 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
CN112559048B (zh) * 2019-09-25 2023-12-12 阿里巴巴集团控股有限公司 一种指令处理装置、处理器及其处理方法
US11360773B2 (en) * 2020-06-22 2022-06-14 Microsoft Technology Licensing, Llc Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching
US11074077B1 (en) 2020-06-25 2021-07-27 Microsoft Technology Licensing, Llc Reusing executed, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-execution

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040187119A1 (en) * 1998-09-30 2004-09-23 Intel Corporation Non-stalling circular counterflow pipeline processor with reorder buffer
US6799263B1 (en) * 1999-10-28 2004-09-28 Hewlett-Packard Development Company, L.P. Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5584009A (en) * 1993-10-18 1996-12-10 Cyrix Corporation System and method of retiring store data from a write buffer
DE69429612T2 (de) * 1993-10-18 2002-09-12 Via-Cyrix, Inc. Schreibpuffer für einen superskalaren Mikroprozessor mit Pipeline
ES2138051T3 (es) * 1994-01-03 2000-01-01 Intel Corp Metodo y aparato para la realizacion de un sistema de resolucion de bifurcaciones en cuatro etapas en un procesador informatico.
US5978909A (en) * 1997-11-26 1999-11-02 Intel Corporation System for speculative branch target prediction having a dynamic prediction history buffer and a static prediction history buffer
US6205542B1 (en) * 1997-12-24 2001-03-20 Intel Corporation Processor pipeline including replay
CN1280712C (zh) * 2004-03-09 2006-10-18 中国人民解放军国防科学技术大学 超长指令字微处理器中的指令控制流水线方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040187119A1 (en) * 1998-09-30 2004-09-23 Intel Corporation Non-stalling circular counterflow pipeline processor with reorder buffer
US6799263B1 (en) * 1999-10-28 2004-09-28 Hewlett-Packard Development Company, L.P. Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted

Also Published As

Publication number Publication date
US20060190707A1 (en) 2006-08-24
EP1849063A2 (en) 2007-10-31
KR20070105366A (ko) 2007-10-30
US7152155B2 (en) 2006-12-19
EP1849063B1 (en) 2018-08-01
CN100538629C (zh) 2009-09-09
WO2006089189A2 (en) 2006-08-24
WO2006089189A3 (en) 2006-10-12
JP2008530713A (ja) 2008-08-07
CN101156136A (zh) 2008-04-02
MX2007010048A (es) 2007-11-06
JP4763727B2 (ja) 2011-08-31
IL185301A0 (en) 2008-02-09

Similar Documents

Publication Publication Date Title
KR100938367B1 (ko) 분기 예측 오류를 정정하는 시스템 및 방법
JP2008530713A5 (https=)
TWI470546B (zh) 微處理器、管線式微處理器、快速執行條件分支指令之方法、以及解析第一或第二類別條件分支指令之方法
JP6370829B2 (ja) 誤予測された分岐のためにフラッシュするセグメント化パイプライン
CN102934075B (zh) 用于使用预先通知技术改变程序的顺序流程的方法和设备
KR101099203B1 (ko) 명시적 서브루틴 호출의 브랜치 예측 동작을 에뮬레이트하기 위한 방법 및 장치
US9021240B2 (en) System and method for Controlling restarting of instruction fetching using speculative address computations
EP2087420B1 (en) Methods and apparatus for recognizing a subroutine call
US10620953B2 (en) Instruction prefetch halting upon predecoding predetermined instruction types
KR100916168B1 (ko) 조건 평가를 위한 에미서리 명령을 통한 조건 명령 실행
JP2008530714A (ja) 非整列メモリアクセス予測
US6871275B1 (en) Microprocessor having a branch predictor using speculative branch registers
HK1112982A (en) System and method of correcting a branch misprediction
HK1112087A (en) Conditional instruction execution via emissary instruction for condition evaluation

Legal Events

Date Code Title Description
A201 Request for examination
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

Fee payment year number: 1

St.27 status event code: A-2-2-U10-U12-oth-PR1002

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20121227

Year of fee payment: 4

PR1001 Payment of annual fee

Fee payment year number: 4

St.27 status event code: A-4-4-U10-U11-oth-PR1001

FPAY Annual fee payment

Payment date: 20131227

Year of fee payment: 5

PR1001 Payment of annual fee

Fee payment year number: 5

St.27 status event code: A-4-4-U10-U11-oth-PR1001

FPAY Annual fee payment

Payment date: 20141230

Year of fee payment: 6

PR1001 Payment of annual fee

Fee payment year number: 6

St.27 status event code: A-4-4-U10-U11-oth-PR1001

FPAY Annual fee payment

Payment date: 20151230

Year of fee payment: 7

PR1001 Payment of annual fee

Fee payment year number: 7

St.27 status event code: A-4-4-U10-U11-oth-PR1001

FPAY Annual fee payment

Payment date: 20161229

Year of fee payment: 8

PR1001 Payment of annual fee

Fee payment year number: 8

St.27 status event code: A-4-4-U10-U11-oth-PR1001

FPAY Annual fee payment

Payment date: 20171228

Year of fee payment: 9

PR1001 Payment of annual fee

Fee payment year number: 9

St.27 status event code: A-4-4-U10-U11-oth-PR1001

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

Not in force date: 20190116

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

St.27 status event code: A-4-4-U10-U13-oth-PC1903

PC1903 Unpaid annual fee

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20190116

St.27 status event code: N-4-6-H10-H13-oth-PC1903

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000