KR100937941B1 - Delay Locked Loop for Semiconductor Memory Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a delay locked loop which reduces skew depending on temperature and voltage. The disclosed invention includes a phase detector, a low pass filter, a variable delay circuit, and a compensation delay circuit in a delay locked loop of a semiconductor memory device that generates an internal clock in synchronization with an external clock, wherein the compensation delay circuit includes a temperature and voltage. The present invention relates to a delay locked loop of a semiconductor memory device having an effect of reducing skew of an external clock and an internal clock by adjusting a delay time in consideration of a change in the lateral current.

Description

Delay Locked Loop for Semiconductor Memory Device

1 is a block diagram of a delay locked loop of a conventional semiconductor memory device.

FIG. 2 is a diagram illustrating a compensation delay circuit of the delay locked loop of FIG. 1. FIG.

3 is a block diagram of a delay locked loop of a semiconductor memory device according to an embodiment of the present invention.

4 is a diagram illustrating a compensation delay circuit of the delay locked loop of FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a delay locked loop having reduced skew according to temperature and voltage.

Generally, a device that generates an internal clock signal using a clock signal input from an external device among semiconductor devices operating in synchronization with a clock, is referred to as a phase locked loop (PLL) or a delayed locked loop (DLL). Etc. are widely used.

In particular, a DLL is generally used in a synchronous memory device to generate a clock that is faster than an external clock by a certain time in order to reduce an access time as high frequency and high speed operation is required.

1 is a block diagram of a general DLL of a conventional semiconductor memory device.

Referring to FIG. 1, a conventional DLL 1 includes an external clock input buffer 10, a phase detector 12, a low pass filter 14, a variable delay circuit 16, and a compensation delay circuit 18. do.

The external clock input buffer 10 buffers the external clock CLK_EX to generate the input clock CLK, and the phase detector 12 compares the phase of the input clock CLK and the feedback clock CLK_FB to detect a phase error.

The low pass filter 14 generates a control signal according to the phase error information of the phase detector 12 to control the delay time of the variable delay circuit 16, and the variable delay circuit 16 responds to the control signal. The internal clock CLK_IN is generated by performing a locking by delaying the input clock CLK with a variable delay time.

The compensation delay circuit 18 outputs the feedback clock CLK_FB by delaying the internal clock CLK_IN by the data output delay time D2.

Here, the data output delay time D2 is a time taken until the data DATA output from the memory cell array is output to the outside of the chip through the data output driver 22.

The data output driver 22 receives the internal clock CLK_IN output from the variable delay circuit 16 and the output clock CLK_OUT buffered through the internal clock buffer 24.

The conventional DLL 1 finds a variable delay by finding a time obtained by subtracting the delay time D1 of the external clock CLK_EX from the external clock input buffer 10 and the delay time D2 of the compensation delay circuit 18 in the internal clock one cycle tCC. The internal clock CLK_IN is locked by finding the delay time tCC-D1 + D2 of the circuit 16 to provide a reference clock which is inputted to and operated by another circuit of the semiconductor device.

Here, the locking of the internal clock CLK_IN is performed when the input clock CLK and the feedback clock CLK_FB input to the phase detector 12 are the same. Therefore, the phase detector 12 should accurately detect the phase error between the input clock CLK and the feedback clock CLK_FB.

On the other hand, a semiconductor memory device may have a severe process variation for each lot, and characteristics of the device may vary according to a change in power supply and temperature. In order to generate the internal clock CLK_IN by reflecting the phase error due to the characteristic change of the device, it is important that the delay time of the variable delay circuit 16 is precisely varied, but the delay time D2 by the compensation delay circuit 18 is compensated accurately. It is also important.

In general, the compensation delay circuit 18 should be configured to have the same delay time as the actual data path, but the data output driver 22 has a very large size to drive a large load outside the chip, so that Since it is difficult to implement the same load because a large load cannot be implemented inside the chip, the delay amount is modeled using a simple delay element.

2 is a circuit diagram showing an example of the compensation delay circuit 18 included in the conventional DLL.

Referring to FIG. 2, the compensation delay circuit 18 included in the conventional DLL includes a capacitor connected to a node between a plurality of resistors R1, R2 and R3 connected in series and a resistor R1, R2 and R3. And a delay unit 30 including C1, C2, and C3. In other words, the delay unit 30 is a circuit in which the delay time D2 is adjusted by connecting the unit delay means 31 connected in series with the resistor R1 and the capacitor C1 in series with the ground power supply VSS and adjusting the number thereof. .

However, since the compensation delay circuit 18 cannot adjust the delay time D2 by reflecting the delay time of the actual path according to the change of the process, power, temperature, etc., the feedback clock CLK_FB is not accurate, so the internal clock CLK_IN and the external clock are not accurate. There is a problem of increasing the skew between CLK_EX.

Accordingly, an object of the present invention is to reduce the skew between the internal clock and the external clock output from the delay lock loop by reflecting the delay time according to the temperature and voltage change in the compensation delay circuit to improve the delay lock loop of the semiconductor memory device effective for high speed operation. To provide.

According to an aspect of the present invention for achieving the above object, in the delay lock loop of a semiconductor memory device that generates an internal clock in synchronization with an external clock, detecting a phase error between the external clock and the internal clock, A phase detector for outputting a phase error signal to the phase detector; A low pass filter outputting a control signal in response to the phase error signal; A variable delay circuit for varying a delay time in response to the control signal and generating the internal clock by delaying a phase of the external clock according to the variable delay time to perform locking; And a compensation delay circuit for outputting a feedback clock to the phase detector by delaying a phase of the internal clock to a first delay time to compensate for a delay time from the memory cell array to the outside of the semiconductor memory device. The compensation delay circuit detects a change in temperature and voltage, and adjusts the first delay time according to the detection result to output the feedback clock as the feedback clock.

Here, the compensation delay circuit may include a temperature compensator for outputting a first output signal by delaying the internal clock by a second delay time corresponding to a temperature change; A voltage compensator for outputting a second output signal by delaying the first output signal by a third delay time in response to a voltage change; And a delay unit configured to output the feedback clock by delaying the second output signal to the first delay time.

The temperature compensation unit may include a first delay control unit including a plurality of delay model units modeling a delay amount differently according to the temperature; A temperature sensor for sensing the temperature and outputting a detection signal; And an output selector configured to select an output of the first delay adjuster based on the detection signal.

The first delay control unit may include a first delay model unit modeling the second delay time such that the first delay time does not change when the temperature is a specific temperature section; A second delay model unit modeling the second delay time such that the first delay time is reduced by connecting a resistance in parallel with the delay unit when the temperature is higher than a specific temperature section; And a third delay model unit modeling the second delay time such that the first delay time is increased by a predetermined time when the resistance is connected in series with the delay unit when the temperature is lower than a specific temperature section.

The output selection unit is preferably composed of mux.

The voltage compensator includes: a voltage comparator for comparing a reference voltage with a supply voltage and outputting a comparison signal; And a second delay adjuster that adjusts the third delay time in response to the comparison signal.

The second delay control unit includes a first capacitor connected to a power supply voltage, a second capacitor connected to a ground voltage, a PMOS transistor and an NMOS transistor connected in series between the first capacitor and the second capacitor, and the PMOS transistor. And the comparison signal is provided to a gate of the NMOS transistor, and the first output signal is connected to a common drain of the PMOS transistor and the NMOS transistor.

The delay unit may include unit delay means including a resistor and a capacitor connected in series to a ground voltage, and the plurality of unit delay means may be connected in series to adjust the first delay time.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of a delay locked loop of a semiconductor memory device according to an exemplary embodiment of the present invention.

3, the DLL 101 according to an embodiment of the present invention, the external clock input buffer 110, the phase detector 112, the low pass filter 114, the variable delay circuit 116 and the compensation delay Furnace 118 is provided.

The external clock input buffer 110 buffers the external clock CLK_EX to generate the input clock CLK, and the phase detector 112 detects a phase error by comparing the phase of the input clock CLK and the feedback clock CLK_FB. The low pass filter 114 generates a control signal according to the phase error information of the phase detector 112 to control the delay time of the variable delay circuit 116, and the variable delay circuit 116 responds to the control signal. The internal clock CLK_IN is generated by performing a locking by delaying the input clock CLK with a variable delay time. The compensation delay circuit 118 adjusts and delays the internal clock CLK_IN by the data output delay time D2 to output the feedback clock CLK_FB.

Here, the data output delay time D2 is a model of the time taken until the data DATA output from the memory cell array is output to the outside of the chip through the data output driver 122, and the actual path is a change in temperature and voltage. Due to variations in the characteristics of the device.

The data output driver 122 receives the internal clock CLK_IN output from the variable delay circuit 116 through the internal clock buffer 124 and receives the output clock CLK_OUT buffered.

The DLL 100 according to an exemplary embodiment of the present invention provides a delay time D1 at which the external clock CLK_EX is delayed at the external clock input buffer 110 and a delay time D2 of the compensation delay circuit 118 at an internal clock one cycle tCC. The subtracted time is found to find the delay time (tCC-D1 + D2) of the variable delay circuit 116, and the internal clock CLK_IN is locked to provide a reference clock that is input to and operated by another circuit of the semiconductor device.

Since the locking of the internal clock CLK_IN is performed when the input clock CLK and the feedback clock CLK_FB input to the phase detector 112 are the same, the phase error between the input clock CLK and the feedback clock CLK_FB must be accurately detected by the phase detector 112. In particular, the compensation delay circuit 118 should compensate for the delay time D2 by reflecting the phase error caused by the change of the characteristics of the semiconductor device by the change of temperature and voltage in the actual path.

4 is a diagram illustrating a compensation delay circuit of the DLL of FIG. 3.

Referring to FIG. 4, the compensation delay circuit 118 according to an exemplary embodiment of the present invention may include a temperature compensator (B) in front of the delay unit 130 to compensate for the delay time D2 by reflecting a phase error due to a change in characteristics of the device. 140 and the voltage compensation unit 150 are positioned.

The delay unit 130 is a capacitor (C4, C5, C6) connected to the node between the plurality of resistors (R4, R5, R6) and the resistors (R3, R4, R5) connected in series as in the conventional (Fig. 2) It includes. In other words, the delay unit 130 is a circuit in which the resistor R4 and the capacitor C4 are connected in series with the unit delay unit 131 connected in series with the ground power supply VSS and the number thereof is adjusted so that the delay time is D2. . Although three unit delay means 131 is shown here for convenience, the number preferably satisfies the delay amount modeled by the actual path.

The temperature compensator 140 senses a temperature and outputs a first delay by the temperature detector 142 for outputting the detection signal CON and the first delay adjuster 144 and the detection signal CON that model the delay amount differently according to the temperature. And an output selector 146 for selecting an output of the adjuster 144.

Here, when the temperature is a specific temperature section, the first delay control unit 144 is modeled so that the delay time D2 of the compensation delay circuit 118 does not change, and the temperature is a specific temperature. When the resistance value is higher than the interval, the second delay model unit FF modeled so that the delay time D2 is reduced because the resistance value is lowered and the delay amount of the actual path is lower than the delay time D2 of the compensation delay circuit 118. In the low case, the third delay model unit SS is modeled such that the delay time D2 is increased by increasing the resistance value and increasing the delay amount of the actual path than the delay time D2 of the compensation delay circuit 118.

Although the configuration of the first delay control unit 144 is not shown, an example of the configuration will be described. The first delay model unit TT does not have a separate delay means so that the delay time D2 does not change. The second delay model unit FF is connected to the delay unit 130, and the second delay model unit FF includes a resistance connected in parallel with the delay unit 130 to reduce the delay time D2, and the third delay model unit SS Switching having a resistor connected in series with the delay unit 130 as a delay means to increase the delay time D2, and switching between the first to third delay model unit (TT, FF, SS) and the delay unit 130; It is preferred to have a means and that one of the switching means is operated by the output selector 146 to form a connection.

The output selector 146 is configured with a mux for selecting the output of the first delay adjuster 144 according to the detection signal CON.

Looking at the operation of the temperature compensator 140, first, the temperature detector 142 detects the temperature and outputs a detection signal CON, the output selector 146 when the temperature is a specific temperature section according to the detection signal CON When the output of the first delay model unit TT having no delay amount is selected by the first delay control unit 144 and the temperature is higher than a specific temperature section, the output of the second delay model unit FF which reduces the delay amount If the temperature is lower than a specific temperature section, select and output the third delay model unit SS having the increased delay amount to output the output signal T_OUT having the delay amount adjusted according to the temperature change.

The voltage compensator 150 delays and outputs the output signal T_OUT output from the temperature compensator 140 according to a change in voltage. To this end, the voltage comparator 152 comparing the reference voltage VREF and the supply voltage VIN and the second delay adjuster 154 adjusts the delay amount of the output signal T_OUT corresponding to the comparison signal V_CON of the voltage comparator 152. do.

Here, the voltage comparator 152 outputs the comparison signal V_CON high when the supply voltage VIN is higher than the reference voltage VREF. On the contrary, the voltage comparator 152 outputs the comparison signal V_CON low when the supply voltage VIN is lower than the reference voltage VREF. do.

In addition, the second delay controller 154 may include the PMOS transistor P1 and the NMOS transistor N1 connected in series between the capacitors C7 and C8 and the capacitors C7 and C8 directly connected to the power supply voltage VDD and the ground voltage VSS. The comparison signal V_CON of the voltage comparator 152 is provided to the gates of the PMOS transistor P1 and the NMOS transistor N1, and the common drain of the PMOS transistor P1 and the NMOS transistor N1 is a temperature. The output signal T_OUT of the compensator 140 is connected.

Referring to the operation of the voltage compensator 150, the voltage comparator 152 compares the reference voltage VREF with the supply voltage VIN and outputs a comparison signal V_CON. When the comparison signal V_CON of the voltage comparator 152 is high (when the supply voltage VIN is higher than the reference voltage VREF), the second delay controller 154 turns off the PMOS transistor P1 and turns off the NMOS transistor N1. By turning on, the output of the output signal T_OUT is delayed while the capacitor C8 connected to the ground voltage VSS is being charged. On the other hand, when the comparison signal V_CON of the voltage comparator 152 is low (when the supply voltage VIN is lower than the reference voltage VREF), the PMOS transistor P1 is turned on and the NMOS transistor N1 is turned off to be connected to the power supply voltage VDD. The capacitor C7 is discharged to speed up the output of the output signal T_OUT.

As described above, the compensation delay circuit 118 of the present invention includes a temperature compensator 140 for adjusting the delay amount in front of the delay unit 130 and a voltage compensator 150 for adjusting the delay amount in accordance with the voltage change. ), It is possible to set the delay time D2 of the compensation delay circuit 118 by reflecting the actual delay amount that varies with temperature and voltage changes. Therefore, the skew of the internal clock CLK_IN and the external clock CLK_EX is reduced, thereby supporting high speed operation.

Therefore, according to the present invention, by providing a delay delay loop compensation delay circuit that reflects the actual delay time that varies with temperature and voltage changes in the delay time of the compensation delay circuit, thereby reducing the skew of the internal clock and the external clock to achieve high speed operation. It is effective to support.

Claims (8)

In a delay locked loop of a semiconductor memory device that generates an internal clock in synchronization with an external clock, A phase detector detecting a phase error between the external clock and the internal clock and outputting a phase error signal thereto; A low pass filter outputting a control signal in response to the phase error signal; A variable delay circuit for varying a delay time in response to the control signal and generating the internal clock by delaying a phase of the external clock according to the variable delay time to perform locking; And Compensation delay circuit for outputting a feedback clock to the phase detector by delaying the phase of the internal clock first delay time to compensate for the delay time from the memory cell array to the outside of the semiconductor memory device; , The compensation delay circuit detects a change in temperature and voltage, and adjusts the first delay time according to the detection result to output the feedback clock as the feedback clock. The method of claim 1, The compensation delay circuit, A temperature compensator for outputting a first output signal by delaying the internal clock by a second delay time corresponding to a temperature change; A voltage compensator for outputting a second output signal by delaying the first output signal by a third delay time in response to a voltage change; And A delay unit configured to delay the second output signal by a predetermined time and output the feedback clock delayed by the first delay time; The delay lock loop of the semiconductor memory device, characterized in that configured to include. The method of claim 2, The temperature compensation unit A first delay control unit including a plurality of delay model units modeling a delay amount differently according to the temperature; A temperature sensor for sensing the temperature and outputting a detection signal; And An output selector configured to select an output of the first delay adjuster based on the detection signal; The delay lock loop of the semiconductor memory device, characterized in that configured to include. The method of claim 3, wherein The first delay control unit, A first delay model unit modeling the second delay time such that the first delay time does not change when the temperature is a specific temperature section; A second delay model unit modeling the second delay time such that the first delay time is reduced by connecting a resistance in parallel with the delay unit when the temperature is higher than a specific temperature section; And A third delay model unit modeling the second delay time such that the first delay time is increased by a predetermined time by connecting a resistor in series with the delay unit when the temperature is lower than a specific temperature section; The delay lock loop of the semiconductor memory device, characterized in that configured to include. The method of claim 3, wherein And the output selector comprises a mux. The method of claim 2, The voltage compensation unit A voltage comparator for comparing a reference voltage with a supply voltage and outputting a comparison signal; And A second delay adjuster configured to adjust the third delay time in response to the comparison signal; The delay lock loop of the semiconductor memory device, characterized in that configured to include. The method of claim 6, The second delay control unit A first capacitor connected to a power supply voltage, a second capacitor connected to a ground voltage, and a PMOS transistor and an NMOS transistor connected in series between the first capacitor and the second capacitor, the gate of the PMOS transistor and the NMOS transistor The comparison signal is provided, and the first output signal is connected to a common drain of the PMOS transistor and the NMOS transistor. The method of claim 2, The delay unit And a unit delay means comprising a resistor and a capacitor connected in series to a ground voltage, and connecting the plurality of unit delay means in series to adjust the first delay time.

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