KR20080002589A - Delay locked loop circuit - Google Patents

Abstract

A delay locked loop circuit is provided to inhibit increase in locking time for delay period despite great differences of external voltage or temperature between before and after power down mode in a semiconductor memory device. A delay locked loop circuit includes a detecting unit(111) and a delay correcting unit(112). The detecting unit starts to operate in response to power down signal(p_down) enabled during power down mode. The detection unit detects the duration of power down mode to output the result of the duration at the power down mode. The delay correcting unit starts to operate in response to the result outputted by the detecting unit and corrects delay in accordance with the duration of the power down mode for generating internal clock(int_clk) in phase with external clock(CLK).

Description

Delay Locked Loop Circuit

1 is a block diagram illustrating a conventional delay locked loop circuit.

Figure 2 shows a detailed view of the conventional delay locked loop circuit of FIG.

3 shows a configuration of a delay locked loop circuit according to a first embodiment of the present invention.

4 shows the configuration of the delay locked loop circuit according to the second embodiment of the present invention.

5 shows the configuration of a delay locked loop circuit according to a third embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay locked loop circuit, and more particularly, to prevent a stock fail even when a large change in external voltage or temperature occurs before and after a power down mode in a semiconductor memory device such as a DRAM. The present invention relates to a delay locked loop circuit capable of preventing an increase in a locking time for a delay section.

In general, a clock is used as a reference signal for timing operation in a system or a circuit, and may be used to ensure faster operation without an error. When a clock input from the outside is used internally, a time delay (clock skew) occurs due to an internal circuit, which compensates for this time delay so that the DQ data or the DQ strobe has the same phase as the external clock. Phase locked loops (PLLs), delay locked loops (DLLs), etc., are used to adjust the phase of the phase to an appropriate level.

Although PLLs have been widely used in the past, DLLs are widely used in synchronous semiconductor memories including DDR Double Data Rate Synchronous DRAM (SDRAM) because of the advantages of DLLs that are less affected by noise than PLLs.

However, in the conventional delayed fixed loop circuit, when a change in external voltage or temperature is large in the semiconductor memory device before and after the power down mode, a stock fail occurs or the locking time for the delay period increases. There was a problem, which will be described in detail with reference to FIG. 1.

FIG. 1 is a block diagram illustrating a conventional delay locked loop circuit. In the conventional delay locked loop circuit, as shown in FIG. 1, the DLL block 100 receives an external clock CLK and a power down signal p_down. By processing this, an internal clock (int_clk) was generated. Prior to describing the problem of the conventional delay loop loop circuit, the basic operation of the delay loop loop circuit will be described with reference to FIG.

First, the buffer 101 buffers the external clock CLK to output the reference clock ref_clk. The variable delay unit 102 delays the reference clock ref_clk output from the buffer 101 by a predetermined period and outputs the delayed unit 102 under the control of the delay control unit 105. The delay section can be increased or decreased variably.

Subsequently, the buffer 106 buffers the signal supplied from the variable delay unit 102 and outputs an internal clock int_clk. The data output buffer 107 outputs data supplied from the cell array in synchronization with the internal clock int_clk.

Meanwhile, the replica delayer 103 outputs a feedback clock fb_clk by delaying the signal supplied from the variable delayer 102 by a predetermined period. Here, when the replica delayer 103 receives an external clock CLK into the buffer 101 and enters the delay element d1 and the buffer 106 until the variable delay unit 102 is output, data is output. It has a predetermined delay period (d1 + d2) modeling the delay element (d2) up to, and the replica delay unit 103 delays the output signal of the variable delay unit 102 by the delay period to improve the feedback clock (fb_clk) Output In principle, in order for the external clock CLK to be correctly synchronized with the DQ strobe, the phases of the reference clock ref_clk and the feedback clock fb_clk input to the phase detector 104 to be described below must coincide with each other.

The phase detector 104 compares the phase of the reference clock ref_clk and the feedback clock fb_clk from the replica delayer 103 and controls the operation of the delay controller 105 to control the phase control signal p_ctr. Outputs That is, the phase detector 104 compares the phases of the reference clock ref_clk and the feedback clock fb_clk and outputs a phase control signal p_ctr for controlling the delay operation of the variable delay unit 102 according to the result. .

The delay controller 105 controls the variable delay unit 102 to sequentially increase or decrease the delay section in response to the phase control signal p_ctr, and accordingly, the feedback clock fb_clk supplied through the feedback path and the like. This allows the synchronization between the reference clocks (refclk) to be maintained.

However, such a conventional delayed fixed loop circuit is to be turned on / off in response to the power down signal p_down as shown in FIG. That is, in the conventional delay locked loop circuit, when the semiconductor device enters the power down mode, the delay block is fixed, that is, locked by turning off the DLL block 100 in response to the power down signal p_down. After the power-down mode, the DLL block 100 was turned on again to relock the delay period. Therefore, the conventional power down signal p_down is only concerned with turning on / off the DLL block 100.

However, after entering the power down mode, the system environment, i.e., the sudden change in the external voltage, which is the operating voltage, or the change in the temperature conditions, causes the external voltage or temperature to be completed after the power down mode is completed. There are cases where great changes occur in environmental requirements. When such a large change occurs in the external voltage or the temperature, a variation occurs in the delay element of the variable delay unit 102 or the replica delay 103 constituting the DLL block 100, and the locking in the DLL block 100 occurs. By varying the delayed value, synchronization mismatch can occur between the output data and the internal clock.

However, the conventional delay loop circuit is only turned off in response to the power down signal (p_down) when entering the power down mode, so even if there is a change in environmental conditions such as external voltage or temperature before and after the power down mode. Proper compensation or correction for delay in the DLL block 100 could not be made. As a result, excessive synchronization mismatch between the external clock CLK and the internal clock int_clk occurs after the power-down mode is completed. Thus, a conventional stock fail (stock), which is a phenomenon that deviates from the appropriate locking range for the clock delay period, is conventionally used. There is a problem that occurs, and the time for locking the delay section again (locking time) also increases.

Therefore, the technical problem to be achieved by the present invention is to prevent the occurrence of a stock fail even if the external voltage or temperature changes largely before and after the power down mode in a semiconductor memory device such as DRAM and increase the locking time for the delay section It is to provide a delay locked loop circuit that can prevent the operation.

In order to achieve the above technical problem, the present invention, in order to synchronize the phase of the internal clock of the semiconductor memory device with the phase of the external clock, the internal clock having an appropriate phase by delaying the input of the external clock by a predetermined delay period. A delay locked loop circuit for generating and outputting a clock, the measurement unit operating in response to a power-down signal enabled in a power-down mode and measuring the elapsed time after entering the power-down mode and outputting the result of the measurement unit In response to the result from the above, there is provided a delay locked loop circuit configured to include a delay correction for correcting the delay section according to the elapsed section after entering the power down mode.

In addition, in order to synchronize the phase of the internal clock of the semiconductor memory device with the phase of the external clock, the present invention delays the input external clock by a predetermined delay period to generate and output the internal clock having an appropriate phase. In a fixed loop circuit, a voltage comparator which operates in response to a power-down signal enabled in a power-down mode and compares external voltages at each time before and after repeating at a predetermined cycle after entering the power-down mode and outputs the result In response to the result from the voltage comparator, there is provided a delay locked loop circuit including a delay correction section for correcting the delay section according to the amount of change in the external voltage.

In addition, in order to synchronize the phase of the internal clock of the semiconductor memory device with the phase of the external clock, the present invention delays the input external clock by a predetermined delay period to generate and output the internal clock having an appropriate phase. In a fixed loop circuit, a voltage comparator and a voltage comparator which operate in response to a power-down signal enabled in a power-down mode and output data relating to the variation of the external voltage by comparing an external voltage with a predetermined reference voltage. In response to the data, there is provided a delay locked loop circuit including a delay correction for correcting the delay section in accordance with the amount of change in the external voltage.

In the present invention, the delay correction unit preferably corrects the delay section of the variable delay unit included in the delay lock loop circuit.

In the present invention, the delay correction unit preferably corrects the delay section of the replica delay unit included in the delay lock loop circuit.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

3 is a block diagram of a delay locked loop circuit according to a first embodiment of the present invention. Referring to this embodiment, the present embodiment will be described below.

As illustrated in FIG. 3, in the delay locked loop circuit according to the first exemplary embodiment, the external clock (input) may be input so that the phase of the internal clock int_clk of the semiconductor memory device is synchronized with the phase of the external clock CLK. A delay locked loop circuit for generating and outputting the internal clock int_clk having an appropriate phase by delay-adjusting CLK by a predetermined delay period, and operating in response to a power-down signal p_down enabled in a power-down mode. In response to the results from the measuring unit 111 and the measuring unit 111 measuring the elapsed period after entering the power down mode and outputting the result, the delay period is corrected according to the elapsed period after entering the power down mode. The delay correction unit 112 is configured to include.

The operation of the first embodiment configured as described above will be described in detail with reference to FIG. 3.

In the delay lock loop circuit according to the first embodiment, the DLL block 100 receives an external clock CLK and processes the same to generate an internal clock int_clk, which is the same as the conventional operation described with reference to FIG. 2. In addition, when the DLL block 100 enters the power down mode, the delay value is fixed to, or locked to, the value before the power down mode is entered in response to the power down signal p_down.

On the other hand, the measurement unit 111 measures the elapsed period after entering the power down mode in response to the power down signal p_down and outputs the result. That is, the measuring unit 111 measures how long the power-down mode is maintained, and periodically provides the result to the delay correction unit 112.

As the measuring unit 111, a counter that counts a clock and provides a result may be used. That is, by using a counter that counts a clock having a predetermined period and periodically provides a counting result, the measurement unit 111 delays information about how long the power-down mode is maintained after the power-down mode is entered. May be provided to the government 112.

Subsequently, the delay correction unit 112 corrects the delay period of the DLL block 100 in response to the measurement result from the measurement unit 111, that is, the counter counting the clock. The delay correction unit 112 simulates the basic data about how the change in each condition such as the temperature change amount, the external voltage change amount, etc. changes depending on the duration of the power down mode, and how the delay period of the DLL block 100 changes accordingly. And adjust the delay period of the DLL block 100 based on the simulated data.

For example, when the delay value locked before entering the power-down mode is 1 [ns] and the temperature at this time is 90 [??], the semiconductor memory device operates in the power-down mode and the temperature is 50 [after 1 [ms]. If the delayed value is changed by 0.4 [ns], the delay correction unit 122 is 0.1 [ms] by using the information on the elapsed interval periodically provided from the measuring unit 111 The delay period of the DLL block 100 is corrected by 0.04 [ns] for each period of.

In the present embodiment, the delay correction unit 112 may correct the delay period of the variable delay unit 102 included in the DLL block 100 of FIG. 2, thereby correcting the delay period of the DLL block 100. In addition, the delay section of the replica block 103 included in the DLL block 100 of FIG. 2 may be corrected to correct the delay section of the DLL block 100.

As described above, the delay lock loop circuit according to the first embodiment corrects the delay section of the DLL block 100 by a predetermined period by a predetermined period according to the elapsed time after entering the power-down mode, thereby deviating from the appropriate locking range. In addition to preventing the stock fail from occurring after the power-down mode is completed, it is possible to prevent the time required for racking the delay section, that is, an increase in the locking time.

Next, FIG. 4 illustrates a configuration of a delay locked loop circuit according to a second embodiment of the present invention. Referring to this embodiment, the present embodiment will be described below.

As shown in FIG. 4, the delay locked loop circuit according to the second exemplary embodiment of the present invention provides an input of the external clock input in order to synchronize the phase of the internal clock int_clk of the semiconductor memory device with the phase of the external clock CLK. A delay locked loop circuit for generating and outputting the internal clock int_clk having an appropriate phase by delay-adjusting CLK by a predetermined delay period, and operating in response to a power-down signal p_down enabled in a power-down mode. In response to the results from the voltage comparator 121 and the voltage comparator 121 comparing the external voltages VDD at each time before and after repeated in a predetermined period after entering the power down mode and outputting the result, the external And a delay correction unit 122 for correcting the inter-study according to the variation amount of the voltage VDD.

The operation of the second embodiment configured as described above will be described in detail with reference to FIG. 4.

In the delay lock loop circuit according to the second embodiment, the DLL block 100 receives an external clock CLK and processes the same to generate an internal clock int_clk, which is the same as the conventional operation described with reference to FIG. 2. In addition, when entering the power down mode, the DLL block 100 locks the delay value to the value before entering the power down mode in response to the power down signal p_down.

On the other hand, the voltage comparator 121 measures the change in the external voltage after entering the power-down mode at a predetermined period to compare the external voltage at each time point. That is, if the external voltage at the first time point t1 is VDD1 and the external voltage at the second time point t2 is VDD2, and the voltage difference VDD2-VDD1 exceeds the predetermined ?? V, the voltage comparator 121 outputs a predetermined enable signal. When the external voltage at the third time point t3 becomes VDD3 and the voltage difference VDD3-VDD2 again exceeds ?? V, the voltage comparator 121 outputs the enable signal again. The voltage comparator 121 performs the voltage comparison operation at predetermined cycles and outputs an enable signal when the amount of change in the external voltage exceeds a predetermined value. The voltage comparator 121 may be any type of voltage comparator that periodically detects an amount of change in the input voltage and outputs a result signal according to the amount of change.

The delay compensator 122 corrects the delay section of the DLL block 100 in response to the enable signal input from the voltage comparator 121. The delay correction unit 122 has simulated basic data on how the delay period of the DLL block 100 changes according to the amount of change in external voltage after entering the power-down mode, and based on the simulated data, Adjust by adjusting the delay section of 100). Therefore, when the voltage comparator 121 detects the voltage change periodically and outputs the enable signal, the delay compensator 122 corrects the delay period of the DLL block 100 whenever the enable signal is input.

As in the first embodiment, in the second embodiment, the delay compensator 122 corrects the delay period of the variable delay unit 102 included in the DLL block 100 of FIG. The delay section may be corrected, and the delay section of the replica block 103 included in the DLL block 100 of FIG. 2 may be corrected to correct the delay section of the DLL block 100.

As described above, the delay locked loop circuit according to the second embodiment corrects the delay period of the DLL block 100 by the delay period simulated according to the amount of change of the external voltage after entering the power down mode, thereby completing the stock fail after the power down mode is completed. Not only can the phenomenon be prevented from occurring, but it is also possible to prevent an increase in the time taken to lock the delay section, that is, the locking time.

Next, FIG. 5 illustrates a configuration of a delay locked loop circuit according to a third embodiment of the present invention, which will be described below with reference to this embodiment.

As shown in FIG. 5, in the delay locked loop circuit according to the third exemplary embodiment, the external clock received in order to synchronize the phase of the internal clock int_clk of the semiconductor memory device with the phase of the external clock CLK. A delay locked loop circuit for generating and outputting the internal clock int_clk having an appropriate phase by delay-adjusting CLK by a predetermined delay period, and operating in response to a power-down signal p_down enabled in a power-down mode. In response to the data from the voltage comparator 131 and the voltage comparator 131 comparing the external voltage VDD with a predetermined reference voltage VREF and outputting data on the variation amount of the external voltage VDD. And a delay correction unit 132 for correcting the delay period according to the variation amount of the external voltage VDD.

The operation of the third embodiment configured as described above will be described in detail with reference to FIG. 5.

In the delay lock loop circuit according to the third embodiment, the DLL block 100 receives an external clock CLK and processes the same to generate an internal clock int_clk, which is the same as the conventional operation described with reference to FIG. 2. In addition, when entering the power down mode, the DLL block 100 locks the delay value to the value before entering the power down mode in response to the power down signal p_down.

On the other hand, the voltage comparator 131 compares the external voltage VDD with a predetermined reference voltage VREF and outputs data on the variation amount of the external voltage VDD. The comparison operation of the voltage comparator 131 continues until the power-down signal p_down is disabled, and the voltage comparator 131 has an external voltage VDD compared to the reference voltage VREF. Data is supplied to the delay correction unit 132.

The delay correction unit 132 corrects the delay period of the DLL block 100 in response to the data input from the voltage comparator 131. The delay correction unit 132 has basic data simulated about how the delay period of the DLL block 100 changes according to the amount of change in external voltage after entering the power-down mode, and based on the simulated data, Adjust by adjusting the delay section of 100).

As in the first and second embodiments, in the third embodiment, the delay correction unit 132 corrects the delay period of the variable delay unit 102 included in the DLL block 100 of FIG. 2 or replicates the delay unit 103. By correcting the delay section of the ()) it is possible to correct the delay section of the DLL block (100).

As described above, the delay lock loop circuit according to the third embodiment corrects the delay period of the DLL block 100 by the delay period simulated in advance according to the amount of change of the external voltage to the predetermined reference voltage after the power down mode is entered into the power down mode. Not only can the stock fail phenomenon be prevented from occurring after completion, but also it is possible to prevent an increase in the time taken to rack the delay section, that is, the racking time.

As described above, the delay-locked loop circuit according to the present invention prevents a stock fail from occurring even when a large change in external voltage or temperature occurs before and after a power-down mode in a semiconductor memory device such as a DRAM. There is an effect that can prevent the increase in the locking time.

Claims (11)

A delay locked loop circuit for generating and outputting the inner clock having an appropriate phase by delay-adjusting an external clock by a predetermined delay period, A measuring unit which operates in response to the power-down signal enabled in the power-down mode and measures the elapsed period after entering the power-down mode and outputs the result; And a delay correction section for correcting the delay section in accordance with the elapsed section after entering the power-down mode in response to the result from the measuring section. The method of claim 1, And the counter includes a counter for counting a clock and providing a counting result at a predetermined period, wherein the delay correction unit corrects the delay section at the predetermined period in response to the counting result. The method of claim 1, The delay correction loop correcting a delay section of the variable delay included in the delay locked loop circuit. The method of claim 1, The delay correction loop delay loop correction for correcting the delay section of the replica delay unit included in the delay loop loop circuit. In order to synchronize the phase of the internal clock of the semiconductor memory device with the phase of the external clock, in the delay locked loop circuit for generating and outputting the internal clock having a proper phase by delaying the input external clock by a predetermined delay period , A voltage comparator that operates in response to the power-down signal enabled in the power-down mode and compares the external voltages at each time before and after repeating at predetermined intervals after entering the power-down mode and outputs the result. And a delay correction section for correcting the delay section in accordance with the variation amount of the external voltage in response to the result from the voltage comparator. The method of claim 5, The voltage comparator periodically compares the external voltage at each time before and after the output and outputs an enable signal when the amount of variation exceeds a predetermined value. And the delay correction unit corrects the delay section by a predetermined section in response to the enable signal. The method of claim 5, The delay correction loop correcting a delay section of the variable delay included in the delay locked loop circuit. The method of claim 5, The delay correction loop delay loop correction for correcting the delay section of the replica delay unit included in the delay loop loop circuit. In order to synchronize the phase of the internal clock of the semiconductor memory device with the phase of the external clock, in the delay locked loop circuit for generating and outputting the internal clock having a proper phase by delaying the input external clock by a predetermined delay period , A voltage comparator which operates in response to a power-down signal enabled in the power-down mode and outputs data on the variation amount of the external voltage by comparing the external voltage with a predetermined reference voltage; And a delay correction section for correcting the delay section according to the amount of change of the external voltage in response to data from the voltage comparator. The method of claim 9, The delay correction loop correcting a delay section of the variable delay included in the delay locked loop circuit. The method of claim 9, The delay correction loop delay loop correction for correcting the delay section of the replica delay unit included in the delay loop loop circuit.

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