KR100921962B1 - Background operation for memory cells - Google Patents

Abstract

Techniques for performing an operation (e.g., erase, program, or read) in memory cells 105 are better to apply the operating voltage periodically to the gates 111 and 113 of the memory cells than to the continuous operating voltage. This reduces the power consumed during operation. While the selected memory cells are active, basic operations such as dynamic operation or basic erase also allow the remaining operations such as read, program or erase. This improves the operational speed of integrated circuits using dynamic operation as compared to continuous operation. In an embodiment for basic erase, the erase gates are charged to the erase voltage using a current pump (204, 208). The pump is then turned off 212 and the erase gates dynamically persist as a erase voltage (216). The erase voltage at the erase gate will be periodically checked and refreshed as needed until the memory cells are completely erased (224). While the charge pump is off to keep the erase voltage dynamically at the erase gates, other operations may be performed 220, perhaps in the remaining memory cells.

Description

Basic operation for memory cells {BACKGROUND OPERATION FOR MEMORY CELLS}

The present invention relates to nonvolatile erasable programmable memories and, in particular, techniques for erasing, programming, or reading these memory types.

Memory and storage are one of the key technology areas that enable the growth of the information age. The rapid growth of the Internet requires the World Wide Web (WWW), wireless phones, personal digital assistants, digital cameras, digital music players, computers, networks, and continually better memory and storage technologies. One particular memory type is nonvolatile memory. Non-volatile memory remains in its memory or stored state even when power is removed. Nonvolatile erasable programmable memories include flash, EEPROM, EPROM, MRAM, FRAM, ferroelectric and magnetic memories. Non-volatile storage products include CompactFlash (CF) cards, multimedia cards (MMC), flash PC cards (eg, ATA flash cards), smart media cards and memory sticks.

A widely used type of semiconductor memory storage cell is a floating gate memory cell. Types of floating gate memory cells include flash, EEPROM, and EPROM. The memory cells are configured or programmed for the desired configuration state. In particular, electrical charge is located or removed from the floating gate of the flash memory cell to make the memory into two or more stored states. Alternatively, there may be a programmed state and one or more deleted states, depending on technology and terminology. Flash memory cells may be used, represented by at least two binary states, i.e., zero or one. Flash memory cells can store more than two binary states, such as 00, 01, 10 or 11; The cell may store multiple states and may be called a multistate memory cell. The cell may have one or more programmed states. If one state is the deleted state (00), the programmed states will be 01, 10, and 11 even if the actual encoding of the states changes.

Despite the performance of nonvolatile memories, there is also a continuing need to improve the technology. It is desirable to improve the density, speed, durability, and reliability of such memories. It is also desirable to reduce power consumption. As shown, there is a need to improve the operation of nonvolatile memories. In particular, by allowing basic operation of non-volatile memory cells, this will speed up operations and reduce power consumption.

Summary of the Invention

The present invention provides a technique for erasing, programming, or reading nonvolatile memory cells by dynamically applying an operating voltage rather than a continuous voltage to the gates of the memory cells. . This reduces the power consumed during operation. Dynamic operations such as dynamic erase, dynamic program, dynamic read also allow any operation such as read, program or delete that occurs while selected memory cells are activated. Dynamic operation improves the operating speed of integrated circuits as compared to continuous operation. The technique may also be called basic operations such as basic deletion, basic program, or basic read. In an embodiment, the gates are charged to a working or operating voltage using a charge pump. The working voltage can be the erase voltage, the program voltage or the read voltage. The pump is then disconnected, and the gates continue as voltage dynamically. The operating voltage at the gates is checked periodically and refreshed as needed. While the charge pump is disconnected so that the operating voltage dynamically persists to the gates, other operations may be performed, possibly in other memory cells.

In one embodiment, the present invention is directed to a method of operating an integrated circuit with a nonvolatile memory that includes a conversion in a current pump to generate an erase voltage. The erase gate of one or more nonvolatile memory cells selected for erase is charged to the erase voltage. The charge pump is disconnected. The charge pump can also be turned off after it is disconnected. The erase gates are allowed to maintain the erase voltage dynamically while the charge pump is disconnected. The selected nonvolatile memory cells are erased using the dynamic erase voltage.

The charge pump is periodically connected to refresh the erase voltage on the erase gates. Programming of nonvolatile memory cells other than the nonvolatile memory cells selected for deletion is allowed while the charge pump is disconnected. Reading of nonvolatile memory cells other than the nonvolatile memory cells selected for deletion is allowed while the charge pump is disconnected.

Selected nonvolatile memory cells can be checked to see if they have been deleted. If the selected nonvolatile memories have not been erased, the charge pump is connected to refresh the erase voltage on the erase gates. The operation can be repeated.

In yet another embodiment, the present invention relates to a method of operating an integrated circuit that includes erasing, programming, or reading selected memory cells by dynamically charging the gates of selected memory cells by applying a periodically operating voltage to the gates. will be. Operations in memory cells other than the selected memory cells are allowed when no operating voltage is applied directly to the gate. When the selected memory cells are considered erase, program or read, the gates of the selected memory cells are discharged to ground. When the selected memory cells are erased, the VT of the floating gate transistor is constantly positive or negative.

In yet another embodiment, the present invention is an integrated circuit that includes an array of memory cells arranged in rows and columns. A large number of transfer transistors exist and are connected to the rows of each memory cell array. There are a large number of pumps and are connected to one of each transfer transistor. The pump dynamically charges the gates of the row of memory cells through the respective transfer transistors to an operating voltage that is sustained at the gates by dynamically turning off each transfer transistor.

Other objects, features and advantages of the present invention will become apparent from the following detailed description and the accompanying drawings, wherein like reference numerals refer to like features throughout the drawings.

1 shows an arrangement of memory cells and circuitry for the operation of memory cells.

2 shows a flow chart for dynamically deleting memory cells.

3 shows a flowchart for the operation of memory cells dynamically.

4 shows a diagram of a NOR flash cell.

5 shows a diagram of some NAND flash cells.

Integrated circuits that provide nonvolatile storage include programmable memory cells that can be nonvolatile erased. Many types of integrated circuits with nonvolatile memory cells include memory, microcontrollers, microprocessors, and programmable logic. The nonvolatile memory integrated circuits may be combined with other nonvolatile memory integrated circuits to form larger memories. Non-volatile memory integrated circuits may also be combined with the remaining integrated circuits or components, such as a controller, microprocessor, random extraction memory (RAM), or I / O device, to form a non-volatile memory system. An example of a flash EEPROM system is disclosed in US Pat. No. 5,602,987, incorporated by reference in accordance with all references mentioned in this application. The discussion of nonvolatile cells and reservoirs in the future is in US Pat. Nos. 5,095,344, 2,270,979, 5,380,672, and 6,230,233, which are incorporated by reference.

Among the types of nonvolatile storage elements or memory cells are flash, EERPOM, and EPROM. The present invention also applies to other types of memories such as displacement memory, NRAM, FRAM, magnetic ferroelectrics and many others. In general, memory cells are arranged in an integrated circuit of rows and columns. 1 shows an arrangement of flash memory cells 105. Details of the interconnections of the memory cells are not shown in the figures to simplify the diagram. Many other types and configurations of memory cells exist. Memory cell 105 is a multi-bit cell, which is described in more detail in US Pat. No. 5,712,180, incorporated by reference. The memory cell has a select or select gate line 160, a right control gate or erase gate 111, and a left control gate or erase gate 113. The right control gate is the control electrode of the right floating gate transistor (TFRG) 115 and the left control gate line is the control electrode of the left floating gate transistor (TFGL) 117. The right and left control gates are connected to the erase gate line 159. The select gate line is connected to the gate of the select transistor (TSEL) 119. Decoder 166 is connected to the select gate lines. The select gate lines and the select gates corresponding to the row are enabled or disabled by the row using the decoder.

For each memory cell 105, there are two floating gate transistors or cells 115, 117 for storing binary data. Each of these floating gate transistors can store a single bit or multiple bits of data. When storing multiple bits of data, each floating gate cell may also be called a multilevel or multibit cell because the cell can be programmed to have more than one VT (threshold voltage) level. For example, each floating gate transistor may store two bits per cell, four bits per cell, or a much larger number of bits per cell.

Floating gate transistors are optionally configured by applying an appropriate voltage on drain or source lines 123 and 125, control gate lines 113 and 111 and select lines 160. For example, drain or source line 123 may be selectively grounded by using transistor 128.

The present invention will be described with respect to the particular memory cell structure shown in FIG. 1, where there are two floating gate transistors for each cell. However, the present invention can also be applied to other memory cell structures. For example, the present invention can be used for memory cells in which there is a single floating gate transistor per cell. In yet another embodiment, there may be a single floating gate transistor and a single select transistor in each cell. The present invention can be applied to memory cells consisting of NOR or NAND arrays. 4 shows an example of a NOR cell, while FIG. 5 shows an example of a NAND cell.

In an embodiment, the present invention provides a technique of dynamically applying a voltage to some of the memory cells and allowing another operation to the remaining memory cells. By applying a dynamic voltage to some memory cells, this allows dynamic operation to occur on selected memory cells. This dynamic operation can be, for example, dynamic deletion, dynamic program, or dynamic read.

In particular, one of the operations on memory cells is to place the selected floating gate transistors in an erased state. While this discussion focuses on dynamic deletion, it is understood that the present invention similarly applies to any other dynamic operations, including dynamic programs and dynamic reads. Deletion refers to the configuration of each selected floating gate device having, for example, a VT (threshold voltage) of zero volts or less. When erased, the floating gate transistor flows current even when one volt is applied to the gate.

One technique for erasing selected memory cells includes connecting the erase gate line 159, where it is connected to the erase gate of the memory cells for the erase voltage. The erase voltage is generally a high voltage, which can be more than 15 volts. The erase voltage can be from about 15 volts to about 22 volts. The erase voltage can also be generated using an on-chip high voltage pump, also known as a current pump. In other embodiments, the erase voltage may be provided to the pins of the integrated circuit at the off-chip source.

The erase gates of the memory cells are continuously driven with the erase voltage until the memory cells are erased. The memory cells are erased when the VT of the floating gate devices is set to about zero or less. In general, a relatively large number of memory cells are deleted at the same time. For example, in a solid state disk such as a flash card, deletion may be performed in a group of cells called sectors. Memory rows or cells may be deleted one row or one column at a time. In addition, all memory cells of an integrated circuit may be bulk erased simultaneously.

In one embodiment, memory cells are initialized to a deleted state before they can be placed in a programmed state. The technique of erasing memory cells by driving the select gate continuously has drawbacks. The erase operation generally occurs at 1 second of 10000 or even 1 second of 1000. Reading (or sensing) the state of memory cells typically takes one millionth of a second. Programming memory cells typically takes one tenth of a second, and converting an erase pump or a charge pump takes some time in the range of 1 ms to 5 ms.

When erased by continuously driving the erase gate, the erase pump is turned on and generally consumes power: The capacitors of the erase pump are driven using a high voltage clock oscillator that consumes power. The power consumption of the integrated circuit during erase mode is typically 0.01 amps. The erase cycle is the entire time period (eg, one hundredth of a second) from the application of the erase voltage to the erase gates until the floating gate devices are erased. During the delete operation, there are no more other operations occurring during the entire delete cycle. One of the reasons why other operations are not performed during the erase mode is because it is undesirable to further increase power consumption during the erase mode. Another reason is that certain specific circuits, such as programming circuits, cannot be performed or achieve dual tasks.                 

In addition, reliability may be issued when erasing by continuous erasing voltage driving. In a multi-sector erase mode, when all sectors are erased with the same (eg, highest) voltage, they may be required to barely erase sectors, thus stressing unnecessarily fast erases. This leads to a situation where some memory cells are over erased (eg, erased with a lower VT than necessary), which creates surplus stress in these floating gates. This can be induced to reduce the lifetime of overstressed floating gate devices. Therefore, in order to prevent overerase, only patterns of any multi-sector deletion can be used. The erase clock and erase pump are on to draw current during the entire erase operation. In the event of a power shortage, the sector state (e.g., whether or not the sector has been completely erased) remains uncertain and crashes over time. When the memory chip is in erase mode, other types of operation are generally not possible.

A proposed technique for deleting memory cells is to dynamically apply an erase voltage to the control gate (or sometimes referred to as an erase gate) of the selected memory cells. The technique may be called dynamic deletion, latch deletion, or basic deletion. 2 shows a flow diagram of a dynamic deletion technique. The flow charts for the remaining dynamic operations (eg dynamic program, dynamic read) will be similar. In particular, dynamic deletion includes deleting memory cells by turning on the charge pump (box 204). For example, in FIG. 1, the selected erase pump 151 (or referred to as erase and decode circuit) may be turned on and connected and applied to selected memory cells. The erase voltage can optionally be applied to a selected erase line using a decoding circuit. Although details of the decoder circuit are not shown, any general decoder circuit may be used. The decoder circuit includes pass transistors and logic gates.

The transfer transistor 157 between the erase pump and the memory cells can be part of a decode or predecode circuit, which can itself be connected to the erase pump. Transistor 157 is turned on to connect the erase voltage of the erase pump to the erase gate. In order to pass a high voltage from the erase pump through the transfer transistor to the erase line equipped with erase gates, the gate of the transistor needs to be plus the VT of the transfer transistor at a high voltage level (eg, the erase voltage).

The erase gates are charged to the erase voltage (box 208). The erase pump is turned off (box 212) after the gates are charged and transistor 157 is turned off. When there is a parasitic capacitance on the erase line 159 (or also called a word line) connecting the erase (selection) transistors, the erase voltage will be maintained at the erase gates (box 216). Depending on the amount of capacitance, this is generally quite large (within the picofarad range), and the charge on line 159 will gradually weaken mainly due to charge transfer to the floating gate. During the time that line 159 is charged, memory cells will be dynamically erased by the dynamic erase voltage. While the purge pump is disconnected or off, the remaining operations will be performed (box 220). For example, other memory cells may be programmed or sensed and read.                 

Dynamic operation of memory cells may have a duration depending on on-chip logic, off-chip logic, on-chip timers, off-chip timers, or other circuitry. For example, after some time, the memory cells will be checked whether they have been deleted (box 224). This check can be performed using sense amplifier circuitry or other on-chip intelligence. Alternatively, the memory cells can be checked by an external circuit, such as a controller integrated circuit. If not deleted, the dynamic delete operation occurs again (boxes 204, 208, 212, 216, 220 and 224). The erase voltage can be refreshed again for the entire erase voltage level (box 216). The erase voltage will gradually be discharged by an equivalent amount of small current value per erase gate, and consumed by the erase operation of removing electrons from the floating gates. The dynamic erase operation continues until the selected memory cells are deleted (box 228). The deleted memory cells can be written to (or programmed) immediately.

By using the dynamic mode of operation, the above described problems for continuous erase voltage driving are solved. Since the erase line inherently has capacitance (at least some of which is parasitic capacitance), it can be applied to the erase gate at a desired voltage that can be controlled digitally-to-analog-converter (DAC). Then, the transfer gate (transistor 157) that drives it is turned off. The charge remains trapped on the erase line until the transfer gate is later turned on again, at which time the erase gate is refreshed or actively discharged to ground.

There are many ways in which the erase line is actively discharged to ground. The circuit may be part of the pump and decode circuit 151. 1 shows an example of one embodiment. The discharge transistor 163 is connected between the erase line and the ground. The discharge transistor may be connected to the side of the transistor 157, the side of the pump, or the side of the erase gates. In FIG. 1, transistor 163 is connected to the pump side of transistor 157. This discharge transistor is turned on to discharge the erase line after the memory cells are erased.

By using dynamic erase, any combination or pattern of erase gates can actually be latched for simultaneous erase. The erase gates can be discharged to different erase voltage levels, depending on their specific needs, which helps to prevent overstress. After one or more latching of the erase gates in the erase operation, the chip itself may perform some other operation (eg, read, write or delete). For example, the dynamic erase may be from two or more erase lines at the same time. However, certain segments of which deletions are occurring dynamically must be isolated. In addition, dynamic deletion may be performed on deletion lines in any desired pattern. For example, changing rows of memory cells can be deleted. The erase clock and the erase pump may be inactive during most erase operations and store current. If a power shortage occurs, it does not affect the trapped charges, so only relatively sufficient deletion will occur.

In addition, as described above, the erase operation takes a relatively long time compared to other operations such as a read or write operation. Integrated circuits using basic features will work faster. On the other hand, more operations can be performed on integrated circuits with basic erases as compared to integrated circuits with consecutive erases in the same amount of time. As an example, the read operation may take about 2 ms, the delete operation may take about 100 ms or more, and the program operation may take about 10 ms. The read operation is about 50 times or more faster than the delete operation. Therefore, more than 50 times read operations can occur simultaneously as a dynamic erase operation. Program operation is about 10 times faster than delete operation. Therefore, more than 10 times program operations can occur simultaneously according to the dynamic erase operation.

Since the actual voltage on the gate attenuates to floating gates or junction leakage over time due to Fowler-Nordheim tunneling, the refreshing operations can be returned to the desired level or overdriven. (overdrive) A value can be used instead. The overdrive figure can be about 0.5 volts higher than the normal figure.

The circuitry for satisfying the dynamic erase operation is very the same as the circuit used for the continuous or static erase operation. Therefore, there is no limitation of the die size. In addition, if for some reason, perhaps due to process variations, this mode of operation will be unsatisfactory, and standard erase using continuous or static erase voltages will still be used for these integrated circuits. Integrated circuits for which dynamic operation is not functional due to process or other variations can still be packaged and sold.

3 illustrates an alternative embodiment of the present invention wherein the dynamic or basic operation is not strictly a delete operation. First, the circuit for generating the required operating voltage is turned on (box 303). The circuit can be on-chip or off-chip. The circuit can be, for example, a charge pump, a high voltage switch, or a basic logic gate for output of high logic or low logic.

Next, the operating voltage is connected to one or more nodes of one or more nonvolatile memory cells (box 307). The connection can be connected, for example, by the method of a transfer or pass transistor or a logic gate. The node of the memory cell may be a drain, a source, a gate, an erase gate, a tunnel node, or some other node or nodes. The node is charged to an operating voltage, which voltage is held there dynamically by a capacitance comprising parasitic capacitance. The operating voltage is disconnected from the memory cells (box 307).

The dynamic operation occurs in memory cells (box 311). The dynamic operation can be delete, program or read. While dynamic operation is occurring, other memory cells (not dynamically operated) can be activated (box 318). For example, while some memory cells are being dynamically programmed, the remaining memory cells may be read, or, with slightly different start times, interleaved where dynamic operation occurs in two parts of the memory cells. Program, delete, or read may occur. Any combination of other operations may occur as long as the coupling does not disturb or interfere with dynamic operations.

Dynamic operation is checked whether it is complete (box 321). If so, the operation ends (box 325) and other operations can only occur dynamically in memory cells. Dynamic operation, on the other hand, occurs again until it is complete (boxes 307,311,314,318 and 321). The circuit used to check the completion of the dynamic operation can be on-chip, off-chip, and uses a sense amplifier or timer circuit.

4 shows a nonvolatile memory cell for a NOR configuration.

5 illustrates nonvolatile memory cells in a NAND configuration.

4 and 5, the nonvolatile memory cells are floating gate devices such as flash, EEPROM, or EPROM.

The foregoing description of the invention has been stated for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention described for the precise construction, and many variations and variations are possible in light of the above description. The above embodiments are chosen and described in order to best explain the principles of the invention and its practical applications. The foregoing description will enable others skilled in the art to best utilize and practice the invention in various embodiments and as various modifications as are appropriate for a particular use in the art. The scope of the invention is defined by the following claims.

Claims (23)

A method of operating an integrated circuit having nonvolatile memory cells, the method comprising: Turning on the charge pump to generate an erase voltage; Charging one or more erase gates of nonvolatile memory cells selected for erase to an erase voltage; Turning off the charge pump; Causing the erase gate to dynamically maintain an erase voltage while the charge pump is off; And Erasing the selected nonvolatile memory cells using the dynamic erase voltage; Integrated circuit operating method comprising a. 2. The method of claim 1 further comprising periodically turning on the charge pump to refresh the erase voltage on the erase gate. The method of claim 1, further comprising allowing programming of nonvolatile memory cells other than the nonvolatile memory cells selected for erasing while the charge pump is off. 3. The method of claim 2 further comprising allowing reading of nonvolatile memory cells other than the nonvolatile memory cells selected for erasing while the charge pump is off. 2. The method of claim 1 wherein each nonvolatile memory cell comprises two floating gate transistors and one select transistor, the select transistor having an erase gate. The method of claim 1 wherein the erase voltage has a voltage in the range of 15 volts to 22 volts. The method of claim 1, Checking whether the selected nonvolatile memory cells have been erased; And Turning on the charge pump to refresh the erase voltage on the erase gate when the selected nonvolatile memory cells are not erased; Integrated circuit operating method further comprising. The method of claim 1, further comprising allowing other operations in the integrated circuit other than the operation in the nonvolatile memory cells selected for the erase while the charge pump is off. 8. The method of claim 7, further comprising discharging an erase voltage from the erase gate after the selected nonvolatile memory cells are erased. As a method of operating an integrated circuit, Erasing selected memory cells, the erase step being performed by dynamically applying an erase voltage to the erase gates of the selected memory cells periodically to dynamically charge the erase gates; Permitting operation in memory cells other than the selected memory cells when an erase voltage is not directly applied to the erase gates; And When the selected memory cells are erased, discharging the erase gates of the selected memory cells to a voltage level equal to or less than an erase voltage; Integrated circuit operating method comprising a. The method of claim 10, wherein the selected memory cells are erased when the VT of the floating gate transistor is greater than 6 volts. 12. The method of claim 10 wherein all memory cells of the integrated circuit can be selected for erase by dynamically charging all erase gates of the memory cells. 12. The method of claim 11 wherein each memory cell comprises a floating gate transistor. 12. The method of claim 11 wherein each memory cell comprises a multibit floating gate transistor. An array of memory cells arranged in rows and columns; A plurality of transfer transistors each connected to a row of the memory cell array; And A plurality of erase pumps, each coupled to one of the transfer transistors, wherein the erase pump dynamically charges erase gates of a row of memory cells through the respective transfer transistor to an erase voltage and turns off each transfer transistor by turning off each transfer transistor. A plurality of erase pumps, wherein a voltage is maintained dynamically at the erase gates; Integrated circuit comprising a. The method of claim 15, wherein each memory cell, A first floating gate transistor having a first control gate; A second floating gate transistor having a second control gate; And A selection transistor having an erase gate and coupled between the first and second floating gate transistors; Integrated circuit comprising a. A method of operating an integrated circuit having a nonvolatile memory having controlled gate activity for memory cells, the method comprising: Turning on the circuit to generate an operating voltage; Charging one or more gates of the nonvolatile memory cells selected for operation to an operating voltage; Disconnecting the gate from the circuit; Dynamically disconnecting the disconnected gate from the operating voltage while the circuit is off; And Operating the selected nonvolatile memory cells using the dynamic operating voltage; Integrated circuit operating method comprising a. 18. The method of claim 17 further comprising periodically turning on the circuit when the circuit is turned off and reconnecting to the selected gate that is not actively discharged. 18. The integrated circuit of claim 17, further comprising allowing programming of nonvolatile memory cells other than the nonvolatile memory cells selected for operation while the charge pump is not connected to previously selected erase gates. How it works. 18. The integrated circuit operation of claim 17, further comprising allowing readout of nonvolatile memory cells other than the nonvolatile memory cells selected for operation while the charge pump is not connected to a previously selected erase gate. Way. The method of claim 17,  Evaluating whether the listed operations have been achieved; And Coupling the charge pump to refresh the operating voltage on the gate if the listed operation in the selected nonvolatile memory cells has not been achieved; Integrated circuit operating method comprising a. As a method of operating an integrated circuit, Coupling an operating voltage to the first portion of the nonvolatile memory cells; Charging a node of the first portion of the memory cells to an operating voltage; Disconnecting the operating voltage from a node of the first portion of the memory cells; Causing the node of the first portion of the memory cells to dynamically maintain the operating voltage; And Operating dynamically in the first portion of the memory cells; Integrated circuit operating method comprising a. 23. The method of claim 22, further comprising allowing operation in the second portion of the nonvolatile memory cells while the first portion of the nonvolatile memory cells is being operated dynamically.

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