JPH1064286A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To white, erase stably in a short time by a simple operation, by impressing pulse waves changing to a positive and a negative potentials to a control gate and discharging electric charges accumulated in a floating gate. SOLUTION: A memory cell 1 has a floating gate 3 and a control gate 2, and moreover is connected to a switch MOS transistor 8. A drain electrode of the memory cell 1 is connected to a capacitor 9. The drain electrode of the memory cell 1 is charged to a positive potential 5V and thereafter kept at a floating potential. Then, a positive pulse is impressed to an electrode of the control gate 2 so that a potential is +3V for a short time. A negative pulse is subsequently applied to the electrode of the control gate 2 so that the potential is -10V for a short time. A potential of the floating gate 3 is consequently changed thereby to lower a drain potential. The operation is repeated to reduce electric charges accumulated in the floating gate 3. In this manner, data stored in the memory cell are erased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of electrically rewriting information or data, and more particularly to a nonvolatile semiconductor memory device capable of performing writing and erasing operations easily and reliably. .

[0002]

2. Description of the Related Art In a conventional nonvolatile semiconductor memory device,
The rewriting operation of the stored information is roughly classified into a writing method using hot electrons and an erasing method using a tunnel current, and a writing method using a tunnel current and an erasing method using a tunnel current. The former is an electrically erasable flash EEPROM in which a write voltage Vpp is applied to both a control gate and a drain electrode of a memory cell, and hot electrons are injected into a floating gate to perform writing. Therefore, the threshold value of the memory cell varies depending on the channel length, the thickness of the tunnel insulating film, the voltage between the source and drain electrodes, and the like. The distribution of the threshold value V _TH after writing is as shown in FIGS. 38 (a) and 38 (b). It becomes big.

On the other hand, at the time of erasing, the control gate is grounded, an erasing voltage Vpp is applied to a source electrode (or drain electrode), and electrons captured by the floating gate are drawn out to the source electrode (or drain electrode). Also in this erasing operation, the distribution of the threshold value of the cell after erasing is shown in FIGS. 38A and 38B depending on the word line voltage, the drain voltage, the tunnel voltage insulating film thickness, etc. The result is a large variation as shown. The latter is a NAND type EEP
This nonvolatile memory is a nonvolatile memory in which writing and erasing are performed by a tunnel current from the entire surface of the floating gate. As in the case of the above-described erase, since the threshold varies depending on the applied voltage of the word line, the drain voltage, the tunnel insulating film, and the like, the distribution of the threshold V _TH of the memory cell after writing or after erasing is as shown in FIG. It has the feature of increasing as shown in FIG.

FIG. 38 (d) shows a threshold value of a UVEPROM of an ultraviolet erasing type, in which a write voltage Vpp is applied to both a control gate and a drain electrode of a memory cell.
Is applied to inject hot electrons into the floating gate to perform writing. Therefore, Flash EEPR
As in the case of the OM, the threshold voltages of the memory cells after writing are widely distributed. On the other hand, in the erasing operation, the electrons trapped in the floating gate are extracted by irradiating ultraviolet rays, so that the threshold voltage V _TH after erasing has a distribution in which the threshold voltage V _TH is about 0.8 V. In FIGS. 38A to 38D showing the distribution of the threshold voltage, the vertical axis indicates the threshold voltage V _TH , the horizontal axis indicates the frequency of the threshold voltage V _TH of each memory cell, and the electric charge is stored in the floating gate. The state of accumulation is shown as "0" data, and the state of no accumulated charge in the floating gate is shown as "1" data, showing the distribution of threshold voltages. In a conventional semiconductor nonvolatile memory,
As described above, the feature is that the threshold voltage V _TH varies. Therefore, the writing operation and the erasing operation cannot be performed with the same threshold voltage _VTH . Normal,
Even within the same chip, there is variation in threshold value, and the writing time is changed by changing the writing time for each bit so that the threshold voltage falls within a predetermined range.

Further, in a conventional semiconductor nonvolatile memory,
The semiconductor memory device has a logic circuit for detecting and correcting the write state and the erase state of the memory cell, and occupies a large area in the semiconductor memory device. In addition, this logic circuit usually detects a written state or an erased state from a drain current flowing in a memory cell in many cases. One example is JP-A-64-46297 (inventor: Winston K.M.L, applicant: Intel Corporation). FIG. 39 (a), (b)
Is a circuit diagram of the principle thereof, and erasing of the nonvolatile memory can be performed by a special circuit for controlling the final potential of the floating gate.

As shown in FIG. 39A, a nonvolatile memory cell 1 has a control gate 2 and a floating gate 3. The erase voltage source 7 supplies an erase voltage to the source S of the memory cell. A feedback amplifier 4 is connected between the drain D and the control gate 2. In operation, when the drain voltage increases, the control voltage 2 also increases,
Electrons are discharged from the floating gate. As a result, the feedback voltage further increases and is applied to the control gate 2 to cancel the erase voltage. By controlling the amount of feedback of the feedback amplifier circuit 4, the final potential of the floating gate can be controlled.

As shown in FIG. 39 (b), the nonvolatile memory 1 has a control gate 2 and a floating gate 3, and a reference voltage source 6 is connected between the drain of the nonvolatile memory 1 and the control gate 2. The comparator 5 has an output terminal connected to the erase voltage source 7. Drain voltage rises and exceeds the reference voltage V _R, the output of the comparator 5 is inverted to stop the operation of the erase voltage source 7. This prevents the non-volatile memory from being over-erased and generating a negative threshold value. As described above, the conventional nonvolatile memory has a predetermined distribution of thresholds in an initial state, and a circuit for performing a stable operation by reducing a variation in threshold voltage at the time of writing, and an erase state. The memory cell is over-erased at the time of erasing by preventing the occurrence of a negative threshold voltage by providing a feedback circuit or a logic circuit for detecting and correcting the threshold voltage of the memory cell in the initial state. To reduce variations. Thus, the conventional nonvolatile semiconductor memory has a more complicated circuit configuration. in this way,
Since many circuits are required in addition to the memory cells, the size of the nonvolatile semiconductor memory device becomes larger than necessary. Further, when the threshold voltage of the memory cell in the initial state varies, the threshold voltage of the memory cell is set within a predetermined range by changing the write time, and there is a disadvantage that the write time is required.

[0008] Generally, in a write / erase operation of a flash EEPROM, an electric charge is previously stored in a floating gate.
Since the data stored in the floating gate is erased after writing the data "0", there is a disadvantage that the erase operation is complicated.
In the ROM, the erasing operation is performed by temporarily storing the electric charge in the floating gate and then extracting the electric charge. In addition, to save the writing time,
A method of recording data in M and then writing data in a nonvolatile memory cell is adopted.

Therefore, a large peripheral circuit is required.
In order to solve such a drawback, a DRAM (dynamic RAM) is formed in a peripheral area of the nonvolatile memory device while retaining a write / erase operation function of the nonvolatile memory, and after data is once written in the RAM, A method of sequentially writing data in a nonvolatile memory cell has been considered.

When the leakage (leakage current) of the floating charge stored in the sub-bit line is large, the potential drops rapidly, and the precharge is not sufficiently performed. This hinders reading of stored information. Further, in the case where data is accumulated by accumulating charge in the floating gate of the nonvolatile memory cell, if the accumulated charge of the precharged sub-bit line is released by the leakage current, the drain voltage ( Charging voltage). Therefore, the erasing operation may not be performed. It is desirable that the drain voltage is constant, and when the fluctuation is large,
Write / erase operations cannot be performed effectively.

[0011]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, a first object of the present invention is to provide a nonvolatile semiconductor memory which can be erased by a simple erase operation. A second object of the present invention is to provide a nonvolatile semiconductor memory device which can hold a charge accumulated in a bit line and reliably perform a write / erase operation of a floating gate nonvolatile memory. is there. A third object of the present invention is to provide a non-volatile semiconductor memory device capable of reliably performing a stable write / erase operation in a short time. A fourth object of the present invention is to
An object of the present invention is to provide a nonvolatile semiconductor memory device capable of reliably performing a write / erase operation and reducing power consumption.

[0012]

Embodiments of the present invention will be described below from the following four aspects. According to the first aspect of the present invention, a plurality of word lines, a plurality of bit lines intersecting the word lines and a source line, and an intersection of the word lines and the bit lines and the source lines are provided. A plurality of memory cells, each having a source, a drain, a floating gate, and a control gate, the control gate, the drain, the floating gate, and the source being connected to each word line, bit line, and source line, respectively. Means for giving a charge to the source or drain of the memory cell, and a means for floating after a certain time, and applying a signal that changes between a positive potential and a negative potential to the control gate of the selected memory;
Thus, the nonvolatile semiconductor memory device is provided with means for causing the threshold to converge to a constant voltage.

A nonvolatile semiconductor memory device according to a first aspect of the present invention will be described with reference to FIGS.
In the principle diagram of FIG. 1A, a nonvolatile memory cell 1 has a source / drain diffusion layer on a semiconductor substrate and first and second insulating layers (tunnel oxide films) formed on its main surface. The memory cell 1 also has a first electrode (floating gate) surrounded by the first and second insulating films and a second electrode (control gate) formed on the first electrode. Memory cell 1 is connected to switch MOS transistor 8, and its drain electrode is connected to capacitor 9. The capacitor 9 has a bit line connected to a plurality of memory cells, and a total parasitic capacitance Co of a portion electrically connected to the bit line. Portions connected to the bit lines are, for example, the selection switch element 8 and the memory cell. Other transistors or wirings have a structure corresponding to a circuit. Although the selection switch element 8 and the memory cell have at least one transistor, the parasitic capacitance of the impurity diffusion layer on the side to which the transistor is connected mainly or substantially contributes to the parasitic capacitance Co. As the bit line lengthens and the number of nonvolatile memory cells increases, the parasitic capacitance increases. If the bit line or the like is short and the generation of the parasitic capacitance is insufficient, another capacitance element may be connected to the parasitic capacitance Co as an auxiliary to the bit line.

It is now assumed that charges are injected into the floating gate 2 so that data is written to the cell, and that the floating gate 2 is sufficiently charged to a negative potential so that the threshold value of the memory cell is sufficiently high.

As shown in FIG. 1B, the drain electrode of the memory cell 1 is charged to a positive potential (5 V), and thereafter, is set to a floating potential. Next, a positive pulse is applied to the control electrode 2 so that the potential of the control electrode 2 becomes positive (3 V) for a short time, and then a negative pulse is applied to the control electrode 2 so that the potential of the control electrode is short. Make it negative (-10V). Therefore, the potential of the floating gate 3 slightly changes to lower the drain potential. Such an operation is repeated to reduce the charge stored in the floating gate 3, thereby erasing the data stored in the memory cell.

As described above, in the nonvolatile semiconductor memory device according to the first aspect of the present invention, erasing is performed as follows. A pulse wave (signal) that changes to a positive or negative potential is applied to the control gate to discharge the charge stored in the floating gate. When the threshold value of the memory cell becomes sufficiently low, the charge in the drain is transferred to the source through the channel. To lower the drain potential.

The drain potential decreases when a pulse wave is applied to the control electrode. Therefore, even if a negative pulse is applied to the control electrode, no tunnel current flows between the floating gate and the drain, and the floating gate potential does not change any more.

According to a second aspect of the present invention, there are provided a plurality of word lines, a plurality of main bit lines intersecting the word lines, and a sub-bit line and a source line connected thereto via a selection transistor. A source line, a drain, a floating gate, and a control gate, respectively stored at the intersection of the word line and the sub-bit line, the source line, and the control gate, the drain and the source are each word line, sub-bit line,
A plurality of memory cells connected to the source line, a means for precharging one of the sub-bit lines and bringing them into a floating state after a predetermined time, and a control gate of the selected memory cell having a positive peak potential. Means for applying a pulse signal that fluctuates between negative peak potentials, so that the threshold value converges to a constant voltage, and means for supplying a current for compensating leakage current from the sub-bit line to the sub-bit line; And a non-volatile semiconductor memory device provided with:

In a second aspect of the nonvolatile semiconductor memory device according to the present invention, a charge signal stored in the floating gate is extracted by applying a positively or negatively oscillating pulse signal to a control gate of the memory cell. Make the voltage converge to a constant voltage. If the leakage of the precharged charge is large, a current that supplements the leakage current is applied to the sub-bit line to prevent the charging voltage of the sub-bit line from rapidly dropping. Thus, the writing / erasing operation is performed while the charged potential of the sub-bit line is maintained.

According to a third aspect of the present invention, in the nonvolatile semiconductor memory device according to the second aspect, the pulse signal is different from the positive peak value potential between the positive peak value potentials. And a pulse fluctuating between the positive peak value potential and the negative peak value potential is superimposed. Further, a pulse in which the pulse signal fluctuates between another positive peak potential higher than the positive peak potential and the negative peak potential is superimposed between the positive peak potentials. A non-volatile semiconductor memory device is provided.

Referring to FIG. 2A, a third embodiment of the present invention
Brief description of the operation of non-volatile semiconductor memory devices
I do. In FIG. 2A, Ts is a transistor for selection.
M ₁Is a non-volatile memory transistor with a floating gate.
It is a Gista. Memory transistor M₁Drain
It is connected to the source of the selection transistor Ts. That connection
At the continuation point, the capacitor Co and the equivalent resistance corresponding to the leakage wire
R₀Is connected. Apply a signal to the control gate to
The threshold voltage of non-volatile memory with different values is subtracted from its charge.
By omitting it, it converges to a predetermined value.

When the leakage current is large, the fluctuation of the drain voltage is reduced by the leakage current supply means for supplementing the current corresponding to the current value, and the detection of the threshold voltage is facilitated. The capacity Co can be omitted when the line capacity is large.

First, the drain of the selection transistor Ts
And apply a 5V voltage to the gate electrode.
To turn on the selection transistor Ts and
The capacitor Co is charged and the selection transistor Ts is turned off.
As the memory transistor M ₁In a floating state. Note
Retransistor M₁The control gate of FIG.
A pulse as shown in (d) is applied.

The signal shown in FIG. 2C is composed of positive and negative oscillating pulses, and the positive potential pulses A and B have peak values (3 V, 2.
5V), and the peak value of the negative potential pulse C (−10
V) is constant. The pulse signal shown in FIG. 2D is also a pulse oscillating between positive and negative potentials. As shown, negative pulses B and C having peak values of -10V and -5V are alternately repeated and superimposed between positive pulses A each having a constant peak value.

In this manner, the positive potential pulse A sets the memory transistor M ₁ to a predetermined threshold voltage, and lowers the potential of the positive potential pulse B.
The consumption flow can be reduced.

According to a fourth aspect of the present invention, a plurality of word lines, a plurality of main bit lines intersecting the word lines, and a sub-bit line and a source line connected thereto via a selection transistor, A word line and the sub-bit line, each having a source, a drain, a floating gate, and a control gate provided at the intersection of the source line, the control gate, the drain and the source being each word line, the sub-bit line,
A plurality of memory cells respectively connected to the source line, means for charging the source or drain of each of the memory cells to a positive potential, and a positive peak value potential and a negative peak value potential at a control gate of the selected memory cell. Means for applying a pulse signal that fluctuates between the first and second memory cells so that the threshold value converges to a constant voltage, and means for supplying a small current to the source or drain of each of the memory cells. A semiconductor memory device is provided.

In the nonvolatile semiconductor memory device according to the fourth aspect of the present invention, an erase / write operation is performed by supplying a pulse signal to a control gate of a memory transistor (cell) via a word line. Means for supplying a very small current corresponding to a leakage current is provided on the main bit line or the sub bit line, and a small current is supplied to a predetermined bit line in accordance with the operation of the column decoder circuit at the time of an erase / write operation. Therefore, the threshold values of a large number of memory cells can be simultaneously and accurately controlled to a predetermined value.

The "signal" applied to the control gate of the memory cell of the present invention can be defined as a signal that changes between a positive potential and a negative potential, and any signal that can achieve the intended operation of the present invention can be used.

Next, a method of making the threshold values of the floating gate nonvolatile semiconductor memory cells M _{1 to} Mn uniform will be described. In this description, the transistors forming the memory cells M _{1 to} Mn are referred to as “memory cells”. A more specific explanation will be given to facilitate understanding. However, the present invention should not be limited to the specific description. The electrode of the memory transistor on the side where the storage node N (the junction between the transistor and the capacitor in FIG. 1A) is located is called a drain electrode, and the electrode of the memory transistor on the opposite side is called a source electrode. The above definitions of the source electrode and the drain electrode are for convenience. In some cases, depending on the actual operation mode of the nonvolatile semiconductor memory device, it may be better to use the electrode of the memory transistor where the storage node is located as the source electrode. For example, in a known virtual ground line system, a bit line to which a drain electrode of a memory transistor is commonly connected and a source line to which a source electrode thereof is commonly connected are alternately switched to a ground potential. The present invention includes such a mode.

In a certain structure of the memory cell and a voltage application state (distribution of electric field intensity), a tunnel current may flow between the floating gate and the channel of the memory transistor. However, in the following description, regardless of the memory structure and electric field distribution, taking into account that the electrons extracted from the floating gate are finally transferred to the drain electrode in order to place the drain electrode at a relatively high voltage, It is assumed that a tunnel current flows between the floating gate and the drain electrode.

(Method of Adjusting Threshold Value of Nonvolatile Semiconductor Memory Cell) FIG. 1B is a timing chart of a method of adjusting the threshold value of the nonvolatile semiconductor memory cell according to the present invention. In this adjustment method, a constant amplitude, for example, positive,
An AC voltage or an AC pulse signal oscillating between negative potentials is applied a certain number of times. In this way, the drain electrode of the memory transistor is previously maintained at a higher potential than that of the source electrode. In order to maintain the drain electrode at a high potential, it is preferable to accumulate charges by using the parasitic capacitance of the drain electrode and the bit line connected thereto as a capacitor. Otherwise, it can be realized even if a capacitor is specially connected to the drain electrode and charge is accumulated there. Next, an alternating pulse signal that oscillates positively and negatively is applied to the control gate. When a positive voltage is applied to the control gate, a memory transistor having a threshold lower than a certain value determined by a correlation with the applied voltage or a range near the certain value (hereinafter referred to as an expected value) is turned on, and the nonvolatile memory cell is turned on. Transfer from the drain electrode to the source electrode. As a result, the drain voltage is sufficiently lowered, and the tunnel current stops flowing even when a negative voltage is applied to the source electrode thereafter. That is, since the extraction of electrons from the floating gate does not occur, the threshold value of the nonvolatile memory cell does not change thereafter.

On the other hand, when a negative voltage is applied to the control gate, the electric charge stored in the floating gate of the memory transistor is extracted to the drain electrode, and the threshold voltage of the nonvolatile memory cell is reduced by the extracted amount. When a positive voltage is continuously applied to the control gate, the memory transistor having a threshold lower than the expected value is turned on,
Charges move from the drain electrode to the source electrode. As a result, the drain voltage is sufficiently reduced, so that even if a negative voltage is applied to the control gate thereafter, electrons are not extracted from the floating gate, and the threshold value of the nonvolatile memory cell does not change thereafter.

By repeating the above operation, all the nonvolatile memory cells eventually converge to the threshold. still,
For example, if the number of repetitions of the above operation is small, the threshold value may not have a strict convergence to a constant value and may have a desired range. Even in such a case, it is clear that the threshold value of the nonvolatile memory cell is appropriately adjusted by using the above method, and whether to converge strictly to a constant value or to a desired range is determined. It's just a matter.

As is clear from the principle of this method, the waveform of the AC pulse signal applied to the control gate of the nonvolatile memory cell is not particularly limited. It can be a square wave,
It may be a sine wave. This will be described more specifically. For example, consider a case where an AC pulse signal oscillating between 3V and -10V is applied to the control gate of a nonvolatile memory cell having only 10 pulses.

First, when the drain voltage of the selection transistor Tr ₁ is set to 5 V and the gate voltage of the selection transistor is set to 5 V to turn on the selection transistor, the parasitic capacitance of the bit line BL and the portion electrically connected to it is formed. Is charged. By this charging, the drain potential of a memory transistor related to an arbitrary nonvolatile memory Mk is increased. Thereafter, the selection transistor Tr ₁ in the OFF state (gate voltage 0V), is applied to the AC pulse signal to the control gate of the memory transistor according to the non-volatile memory Mk. First, when a positive voltage of 3 V is applied to the control gate of the memory transistor, the memory transistor having a threshold value equal to or less than an expected value determined by a correlation with the positive voltage is turned on, and the memory transistor is turned from its drain electrode toward the source electrode. Channel current flows. This means that the drain voltage of the memory transistor decreases due to the release of the charge stored in the capacitor. In such a memory transistor, a tunnel current does not flow when a negative voltage is applied to the control gate thereafter. Next, -1 is applied to the control gate of this memory transistor.
When a negative voltage of 0 V is applied, the potential of the floating gate becomes negative,
Usually it is about half the potential of the stab gate. Then, electrons are slightly extracted from the floating gate to the drain electrode, and a corresponding tunnel current flows between the floating gate and the drain electrode. As a result, the threshold voltage of the memory transistor is reduced by the amount of electrons extracted from the floating gate. Subsequently, when a positive voltage of 3 V is applied to the control gate of the memory transistor, the drain voltage of the memory transistor having a threshold value lower than the expected value decreases. Thereafter, the application of the AC pulse signal is repeated. Then, finally, the threshold values of all the nonvolatile memory cells are adjusted so as to converge to the expected value.

FIGS. 42 (a) to 42 (c) show the temporal _variation of the floating gate potential _VFG when a pulse-like control gate voltage V _CG (FIG. 42 (c)) is applied to the control gate of the floating gate type memory transistor. Change ((a) in the figure) and the bit line potential V _BL
(B) of FIG. Figure (c)
The control gate voltage V _CG shown in FIG. 1 is an AC voltage formed by continuously coupling a plurality of pulses oscillating between 5 V and −10 V. (A) and (b) of FIG.
As shown in (c), in the initial state, -6V, -4V,
The floating gate potential V _{FG, which} is different such as 2V, is about 100
It has converged to a predetermined potential (about -2 V) in μ seconds. Since the threshold of the memory cell can be considered to be about twice that of the floating gate,
Initially, 12 V, 8
It can be seen that the thresholds distributed as V and 4V converged to about 4V. At this time, as shown in (c) of FIG. 42 (b), as soon as the first pulse ((1) of FIG. 42 (c)) is applied to the memory cell having a low threshold value, the bit line potential V _BL has been decreasing and has approached a certain value since then. On the other hand, as shown in (a) and (b) of FIG. 42B, the fourth pulse (FIG.
The bit line potential V _BL does not decrease rapidly until (4)) of (c) is applied, and the bit line potential V _BL increases as the threshold value increases.
Late timing of lowering The _BL, are asymptotic to a constant bit line potential V _BL regardless of the size of the threshold. Therefore, according to FIG. 42, it is understood that when an AC voltage is applied to the control gate of the floating gate type memory transistor, the threshold value of the memory cell can be adjusted.

This effect is clearly shown in FIGS. 44 and 45. In these figures, the horizontal axis represents the threshold voltage at the beginning of the memory cell, and the vertical axis represents the threshold converged by applying an AC voltage composed of 10 pulses to the control gate. The pulse constituting the AC voltage is 4 in the case of FIG.
V, 3 V or 2 V (15 μs) and −10 V (10 μs)
Seconds), and is a rectangular wave that oscillates between
V (15 μs). As you can see from these figures,
A convergence value or a convergence range of the threshold can be predicted using at least the initial threshold and the AC voltage applied to the control gate as parameters. From these figures, it can be seen from the drawings that when the initial threshold value is 4 V or more, the expected value is approximately constant regardless of the initial threshold value, and the memory value is higher than the positive peak voltage of the AC voltage applied to the control gate. If the initial threshold value of the cell is larger, the expected value is approximately constant regardless of the initial threshold value. If the negative peak voltage of the AC voltage applied to the control gate is −10 V or less, the initial value is It can be seen that it is approximately constant regardless of the threshold value. Initial threshold (Vth
0) is smaller than 4 V and if the positive voltage applied to the control gate is V +, the threshold after convergence is 0.7+ to 0.8.
+ (Vth0 = 2V, about 070V +, Vth0 = 3V
0.73V +, Vth0 = 4V, approximately 0.3V
80V +).

According to the above-described threshold adjustment method, the threshold of the memory cell is lowered by applying a lower voltage (a negative voltage is applied to a junction of an alternating voltage that oscillates positively and negatively). By applying (a positive voltage in the case of an alternating voltage that oscillates positively and negatively), it can be said that the threshold value of the memory cell is verified and sorted. Here, the verification of the threshold value of a memory cell refers to an operation of comparing an actual threshold value of a target memory cell with a convergence value of a threshold value determined by a correlation with a higher voltage or an expected value which is a convergence range. In other words, selecting a memory cell means an operation of distinguishing whether a memory cell has a threshold value equal to or less than an expected value or not. When the memory cells are selected based on the higher voltage, in the memory cells that have a threshold value lower than the expected value, the drain voltage of the memory transistor included in the memory cell decreases, and thereafter, the lower voltage becomes lower. Even if a voltage is applied, a tunnel current does not flow, and the threshold voltage of the memory cell is not verified thereafter. On the other hand, in a memory cell that still has a threshold value higher than the expected value, a tunnel current flows when a lower voltage is applied. Therefore, verification of the threshold value of the memory cell until the threshold value becomes lower than the expected value and subsequent selection of the memory cell are performed. To be served.

In this case, the expected value at which the threshold value of the memory cell should converge can be arbitrarily determined by the higher voltage applied to the control gate. Also, the shorter the application time of the lower voltage, the smaller the tunnel current flowing during that time. In other words, since electrons can be extracted from the floating gate little by little, the accuracy of the convergence of the threshold value of the memory cell to the expected value can be improved.
On the other hand, if the application time of the higher voltage is short, the lower voltage starts before the drain voltage of the memory transistor has not fallen all the time, and the convergence of the threshold value of the memory cell cannot be properly controlled. Therefore, it is preferable that the application time of the higher voltage is long as long as the operation speed of the nonvolatile memory device itself is not hindered.

In the case of an alternating voltage that oscillates positively and negatively, the absolute value of the positive voltage is preferably smaller than the absolute value of the negative voltage. Although it depends on the electric field strength distribution in the gate oxide film, the likelihood of injection of electrons into the floating gate when a positive voltage is applied to the control gate and the possibility of electron injection when the negative voltage is applied to the control gate If the absolute value of the positive voltage is larger than the absolute value of the negative voltage, the threshold voltage of the memory cell may be diverged as a result. Of course, there are conditions under which the injection of electrons into the floating gate due to the application of the positive voltage can be neglected. It can be said that it is effective.

The lower voltage applied to the control gate of the memory transistor is preferably sufficiently low with respect to the drain voltage of the memory transistor. By applying the lower voltage, electrons are extracted from the floating gate, but the drain voltage gradually decreases in the process of applying the AC voltage. Accordingly, extraction of electrons from the floating gate becomes complicated. Therefore, the lower voltage applied to the control gate is made sufficiently low with respect to the drain voltage of the memory transistor, thereby facilitating electron extraction and tunnel current flow. Therefore, it is preferable that the amplitude of the lower voltage applied to the control gate changes in accordance with the fluctuation of the drain voltage.

In the above method of adjusting the threshold value, the higher voltage (positive voltage in the case of an AC voltage oscillating positive and negative) is replaced by the lower voltage (the positive voltage in the case of an AC voltage oscillating positive and negative). It is preferable to apply the voltage to the control gate of the memory transistor before the negative voltage). This is because, when the target memory cell is an EEPROM, if a negative voltage is applied first, the threshold of a memory cell already having a sufficiently low threshold is further lowered, and this memory cell is in a kind of over-erased state. As a result, the source electrode and the drain electrode are short-circuited, the application of the drain voltage becomes impossible,
This is because troubles such as defective data reading and inability to charge the bit line occur.

However, the lower voltage may be applied first. For example, instead of a low voltage of -10V,
In practice, if the voltage is as high as -1 V, the problem of over-erasing does not often occur. Therefore, a lower voltage may be applied first. However, for example, after -1 V is applied first and then 3 V is applied, tunnel current flows more easily when, for example, -10 V, that is, a sufficiently low negative voltage with reference to the drain voltage of the memory trata is applied. It is preferred.

From a different point of view, the above-described method of adjusting the threshold value is different from the floating gate type nonvolatile memory cell in that the threshold value of the floating gate type non-volatile memory cell is reduced and the threshold value is converged to a desired value or a desired range. It is also a new method of erasing (or writing, by definition) non-volatile memory cells. In this sense, in the following practical examples, there is a junction that is generally referred to as an AC pulse method for convenience.

(Description of Basic Structure of Memory to which AC Pulse Method is Applied) The basic structure of a nonvolatile memory device to which the above-described AC pulse method is applied will be described with reference to FIG. In the figure, 1 is a memory array, and 2 (21 to 2)
4) is a selection circuit represented by a multiplexer, 3 is a voltage source, 4 is an AC voltage generation circuit, 5 is a voltage detection circuit, 6 is other peripheral circuits, and 7 is a control circuit. Wi or WLi is a word line, Sj is a source line, Bk or BL
k bit lines, STk the gate selection lines, SL ₁ is the source select line, Trk is selected transistors. Where i, J,
k and l are integers corresponding to the number of main lines such as word lines and source lines and the number of selected transistors.

The memory array 1 has a plurality of nonvolatile memory cells M _{1 to} Mn arranged regularly. An arbitrary nonvolatile memory cell Mk includes a transistor having a control gate and a floating gate (hereinafter, referred to as a memory transistor), and is arranged at an intersection of a word line Wi and a bit line Bk. The gate electrode, the drain electrode, and the source electrode of the memory transistor are respectively connected to a word line W
i, a bit line Bk and a source line Sj. The selection circuit 2 selects a word line, a bit line, and a source line corresponding to a specific address according to a control signal from the control circuit 7. For this reason, it may be considered that the selection circuit 2 includes an address decoder. The selection circuit 21 applies a voltage only to a specific bit line to be selected,
It contributes to power saving. The selection circuit 22 selects a specific gate selection line, and enables the switching operation of the selection transistor corresponding to the selected gate selection line. These selection circuits 2
Bits 1 and 22 that are necessary for the AC pulse method or a supplementary capacitive element can be charged by the methods 1 and 22. Select circuits 23 and 24 select a specific word line and a specific source line. The AC voltage generation circuit 4 supplies a predetermined AC pulse signal to the selected word line via the selection circuit 23. This circuit 4 may be the same as or a part of a circuit for generating a linear voltage signal as a selection signal for selecting a word line, that is, a word line driving circuit. The voltage detection circuit 5 detects the potential of the bit line that is reduced during or after the application of the AC pulse method. This circuit 5 may be used also as a sense circuit for reading memory information. The peripheral circuit 6 collectively summarizes the roundings that are not directly required for the application of the AC pulse method, and briefly describes them.

The control circuit 7 includes a selection circuit 2 (21 to 2).
4), which controls the voltage source 3 and the AC voltage generating circuit 6 in a comprehensive manner, and controls all the controls necessary for the operation of the AC pulse method, including the control of the operation timing of each circuit. A part or all of the control circuit may be formed on a chip on which the memory array 1 is arranged. However, a control signal is input from the outside of the chip and the control circuit 7 performs the operation of the AC pulse method. The control is, for example, as follows.

1. Controlling the selection circuit 2 (1) Select a specific memory cell, a specific word line or a specific bit line. It is also possible to select a number of memory cells, word lines or bit lines at a time. (2) The source potential, drain potential, substrate potential and the like of the selected memory cell can be set to predetermined values. As a result, it is possible to set a potential condition in which a tunnel current or a channel current easily flows in the memory transistor, including setting the potential of the selected bit selection relatively high and maintaining the floating state.

2. By controlling the AC voltage circuit 4, (1) a predetermined AC pulse signal is selected. The amplitude of the pulse, the type, number or cycle of the pulses constituting the AC voltage, the pulse width, the peak value, the pulse waveform, and the like can be appropriately set. Further, it is possible to change which of the positive voltage and the negative voltage is applied first. In particular, for example, the control circuit 7 can increase the absolute value of the peak value of the negative voltage based on a signal from the voltage detection circuit 5 that detects that the potential of the specific word line is decreasing. Similarly, the control circuit 7
Can change the pulse width and the type of pulse constituting the AC pulse based on the signal from the voltage detection circuit 5.

(2) A predetermined AC pulse signal is supplied to the selection circuit 2
3 can be applied to a specific word line.

(3) The application of the AC pulse signal to the specific word line by the AC voltage circuit 4 can be stopped.
In particular, the control circuit 7 stops applying the AC voltage to the specific word line based on a signal from the voltage detection circuit 5 which detects that the potential of the specific word line has sufficiently decreased. This saves power.

3. The voltage source 3 is controlled so as to enable on / off control of the voltage source required for the operation of the switched capacitor.

In each embodiment described below, FIG.
The basic structure of the non-volatile memory device shown in (1) is basically common, unless otherwise specified. Therefore, in each embodiment, only the main part of the memory array 1 needs to be described in principle.

[0054]

Embodiments of the present invention will be described below with reference to the drawings. (First Aspect) A nonvolatile semiconductor memory device according to a first aspect of the present invention will be described with reference to FIG. In the figure, nonvolatile memory cells are arranged in a matrix to form a nonvolatile semiconductor memory device. Each of the memory cells M ₁₁ , M ₁₂ , M ₂₁ , and M ₂₂ has a source / drain diffusion layer formed on a semiconductor substrate, and has a capacity of about 100
Gate oxide film is formed, and the gate oxide film and ONO
The floating gate is covered with an insulating film such as a film (silicon oxide film, silicon oxide film, silicon oxide film), and a control gate is formed thereon.

Memory cell M₁₁, M₁₂Control gate
Do line W₁Connected to the memory cell M _{twenty one}, M_{twenty two}Control game
Is the word line W_TwoIs connected to Bit line B₁No
Morisel M₁₁, M_{twenty one}One electrode of,,, and select
Transistor Tr₁Connected to the source electrode of the
B_TwoIs the memory cell M₁₂, M_{twenty two}One of the electrodes
And select transistor Tr_TwoConnected to the source electrode
ing. Memory cell M ₁₁And M₁₂Connection point and memory cell M
_{twenty one}And M_{twenty two}Are connected in common to the source line S
₁To the source of the source-side select transistor via
Has been continued. Select transistor Tr₁, Tr_TwoIs
Drain electrodes are connected to the pull-up circuit 10, respectively.
And their gate electrodes are connected to a reference voltage source 11.
I have. Bit line B₁And source line S₁Capacitor C between
₁Are connected to the source line S₁And bit line B_TwoBetween
Pasita C_TwoIs connected. Note that the capacitor C₁, C
_TwoMay be connected via a transistor.

Of course, although not limited to this, each memory cell of the embodiment has a floating gate of 3 μm ×
It is assumed to be 1 μm in size, formed with a channel or a part of the source / drain diffusion layer interposed between the gate insulating film, and the size of the channel region is 1 μm × μm.

The required capacitance of the capacitors C ₁ and C ₂ is determined under the following conditions. (Capacitance of floating gate of one memory cell) << (capacitance between bit line and source line)

(Leakage current of floating bit line and its capacitance) >> (Pulse width of AC voltage applied to word line)

Further, when the AC pulse method is applied and an AC voltage is applied to the control gate of the memory transistor, the potential drop of the bit line during application of the AC voltage is within 5%. Desirably. Empirically speaking, the capacitance of the capacitive element 9 and Co satisfying the above conditions is approximately 100 to 300 fF. For this reason, it can be said that the auxiliary capacitance elements C ₁ and C ₂ need not be provided when the parasitic capacitance of the bit line and the portion electrically connected to the bit line is larger than this value.

Referring to the waveform diagrams of FIGS.
An erasing method for the above memory device will be described. First,
The potential of the bit line B ₁ is set to 5 V, the potential of the bit line B ₂ is set to the ground potential, and the potential of the source line S ₁ is set to the ground potential.
Next, the selection transistors Tr ₁ and Tr ₂ are turned off,
The bit lines B ₁ and B ₂ are floated (floating state). The capacitors C ₁ and C ₂ are charged. Subsequently, the word line W ₂ is dropped to the ground potential, applied pulse wave shown in FIG. 4 (a) to (signal) to the control gate of the word lines W ₁ and the memory cell M _11, M _12. The potential of the floating gate connected to the word line W _1, as shown in FIG. 4 (c), the control potential is applied, gradually decreases. FIG.
As shown in (c), the voltage of the drain electrode connected to the bit line B ₁ decreases when the potential of the floating gate is a predetermined threshold and a positive potential is applied to the control gate.

As described above, the pulse wave applied to the control gate via the bit line is initially a positive potential having a peak value of 3 V, and a pulse having a pulse height of 20 μs is applied. A pulse having a negative potential of −10 V and a pulse width of 10 μs is applied. Positive and negative voltages are alternately and repeatedly applied to the control gate to reduce the potential at the floating gate and the drain.

The absolute value of the positive voltage of the pulse wave is
It is necessary to set smaller than the absolute value of the voltage of the negative potential. In addition, it is set so that a pulse of a positive potential is applied to the control gate via the bit line of the memory cell, and then a pulse of a negative potential is applied. The pulse wave is applied from a pulse generation circuit via the switch 13.

[0063] By this operation, when applying a negative pulse to the word line W ₁ which is connected to the control gates of the memory cells M _11, tunnel current flows through the floating gate and the drain diffusion layer. As a result, the charge stored on the floating gate decreases. When the threshold gradually decreases, the source
Channel current starts to flow between the drains. Due to this channel current, the drain voltage decreases, and a tunnel current stops flowing between the floating gate and the drain. Thus, the memory cell M ₁₁ is to have a threshold voltage that is converged.

[0064] On the other hand, in the memory Celta M _12, to the potential of the bit line B ₂ is a ground potential, a tunnel current does not flow between the floating gate and the drain (or source), the threshold of the memory cell M ₁₂ Maintains a high voltage state. In the memory cells M ₂₁ and M ₂₂ , the word line W
_Since the potential of ₂ is the ground potential, the potentials of those floating gates do not change, and the thresholds do not change.

Next, the case where the memory cell has a low threshold value of 2 V will be described. First, signals are applied to bit lines, source lines, word lines, and selection transistors, as in the case where the threshold voltage is high. The potential of the bit line B ₁ to 5V,
The potential of the bit line B ₂ and the ground potential, the potential of the source lines S ₁ and the ground potential.

Next, the selection transistors Tr ₁ and Tr ₂ are turned off, and the bit lines B ₁ and B ₂ are set in a floating state. At that time, the capacitances C ₁ and C ₂ are in a charged state. Subsequently, the word line W ₂ is dropped to the ground potential, indicated pulse wave in FIG. 5 (a) (signal) is applied to the control gate of the word line W _1, i.e., the memory cell M _11, M _22.

[0067] With this operation, in the memory cell M _11,
When a positive pulse is applied to the word line W ₁ that is connected to the control electrode, the channel current flows between the source and drain, the drain voltage is lowered. As a result, even when a negative pulse is applied, no tunnel current flows between the floating gate and the drain. As described above, by applying the positive pulse first, the charge is not further extracted from the floating gate of the memory cell whose threshold value is already low. No operation is required. Here, in order to sufficiently reduce the drain voltage, it is desirable to lengthen the period of the positive potential of the pulse.

Meanwhile, in the memory cell M _12, since the potential of the bit line B ₂ is a ground potential, a tunnel current does not flow between the floating gate and the drain (or source), the threshold of the memory cell M ₁₂ Remain at a high voltage.

In the memory cells M ₂₁ and M ₂₂ ,
Since the potential of the bit line B ₂ is a ground potential, and the potential of the floating gate to change, it does not change the threshold value. Further at the time when the potential of the bit line is lowered all that responsible of the word lines W _1, by completing the erase operation, it is possible gate to erase a large number of memory cells connected to the word line in parallel. Since the erase operation is normally completed in ten cycles or less, the upper limit of the number of memory cells connected in parallel is set to 12 or less.
By setting to about 8, it is not necessary to spend a long time for erasing.

Here, since the potential of the bit line gradually decreases with time due to the source current, a faster and more stable erase operation can be realized by applying a pulse amplitude in anticipation of this decrease to the word line. Can be. In addition, control accuracy can be improved by reducing the pulse width.

Needless to say, the nonvolatile semiconductor memory device according to the first aspect of the present invention is not limited to the nonvolatile semiconductor memory device shown in FIG. Also applicable to

In the memory device shown in FIG. 6, the word lines W _{1 to} W ₄ are orthogonal to the channels of the selector transistors Tr ₁ and Tr ₂ , and the respective memory cells M ₁₁ , M ₁₂ ,
The _{M 22, M 31, M 32} , the source lines S ₁ to S ₃ of M _41, M ₄₂ are connected to the wide area source line Si.

Further, since the erase operation can be simultaneously controlled with respect to the threshold values of a large number of memory cells connected to one word line, if the memory cells have the above dimensions, the number of memory cells that can be arranged in parallel Can be improved from about 64 to about 1000, and the erasing time can be greatly reduced.

In the nonvolatile semiconductor memory device according to the first aspect of the present invention, a pulse wave (signal) is applied to the control gate of the nonvolatile semiconductor memory cell to erase the electric charge stored in the floating gate, thereby erasing the charge. The memory cell is set to the initial state. Therefore, the erasing method is simple.
Further, the conventional write operation before erasure becomes unnecessary, and the erasure time can be greatly reduced.

Further, erasing of a large number of memory cells connected in parallel can be performed simultaneously. By controlling the pulse width of the pulse wave (signal) applied to the control gate, the threshold voltage of the memory cell can be set accurately. This eliminates the need for a special feedback circuit or logic circuit for eliminating a malfunction due to a variation in the threshold value of the nonvolatile memory cell. As a result, if the storage capacity is the same, a nonvolatile semiconductor memory device smaller than before can be provided, and the manufacturing cost can be reduced. Of course, in the writing operation, the processing time can be reduced by the similar operation.

(Second Aspect) A nonvolatile semiconductor memory device according to a second aspect of the present invention will be described. FIG. 7 is a circuit diagram of one embodiment of a nonvolatile semiconductor memory cell according to the second aspect of the present invention. In FIG. 1, a nonvolatile semiconductor memory device includes a nonvolatile memory cell array 21, a level shifter circuit 22, a threshold detection circuit 24 for detecting a threshold voltage of the nonvolatile memory cell, a switch circuit 23,
5, a row / column decoder (not shown), a sense amplifier circuit (not shown), and the like.

[0077] In the memory cell array 21, the drain of the selection transistor Tsa ₁ is mainly connected to the bit line BLa _1, sub bit about BLsa ₁ is connected to its source. The non-volatile memories Ma ₁ and Ma ₂ are connected to the sub-bit line BLsa _1.
Are connected, the sources of the nonvolatile memories Ma ₁ and Ma ₂ are connected in common, and the source side select transistor Trs
It is connected to the _first drain, a source-side select line SL ₁ is connected to the control gate of the source side select transistors Trs _1. Capacitors Ca ₁ between the source and drain of the nonvolatile memory Ma _1, Ma ₂ are connected.

On the other hand, the drain of the selection transistor Tsb ₁ is connected to the main bit line BLb ₁ , the sub-bit line BLsb ₁ is connected to its source, and the nonvolatile memories Mb ₁ , Mb ₁
b ₂ and the capacitor Cb ₁ has a the and trains connections.

The word line W ₁ is connected to the nonvolatile memories Ma ₁ , Mb
_The word line W ₂ is connected to the control gates of the nonvolatile memories Ma ₂ and Mb ₂ . The selection transistor Tsa ₁ and capacitor Ca ₁ and nonvolatile memory Ma ₁ which is connected to the sub-bit line BLsa _1, Ma ₂ and 1 block 1a _1, such a block is the main bit line B
It is connected to the La _1. Then, the selection transistor T
sb ₁ , cache Cb ₁ and memory cells Mb ₁ , Mb ₂
It is connected to the main bit line BLb _1.

The word lines W ₁ , W _2, ... Are commonly connected, and are connected to the level shifter 23 via the switch circuit 23. The switch 23 may be a multiplexer, and is connected to the level shifter circuit 22 via the multiplexer for each block.

The sub bit line BLsa ₁ is connected to a threshold detection circuit 24 via a switch circuit 25, and the sub bit line BLsb ₁ is also connected to the threshold detection circuit 24. The threshold detection circuit 22 includes a transistor (MOSFE).
T) A CMOS inverter composed of T6 and T7.

The level shifter circuit 22 includes a CMOS inverter composed of transistors (MOSFETs) T ₂ and T ₃ , a transistor T 4 whose input side is set to be always on, and a positive feedback of the output of this CMOS inverter to its input side. Transistor T5.

In operation, a pulse having a peak value of 5 V as shown in FIG. 8A is applied to the input stage of the level shifter circuit 22, and a positive or negative pulse as shown in FIG. 3V, -10V). That is, “H” is input to the input stage of the level shifter circuit 22.
A pulse signal of a level (5V) and an "L" level (0V) is supplied at a predetermined cycle. When the "L" level is input, the output becomes "L" level (-10V), and -1
A voltage of 0 V is applied to word lines W ₁ and W ₂ . Also,"
When the H level is input, its output becomes the "H" level (3 V), and a voltage of 3 V is applied to the word lines W ₁ and W ₂ .

The threshold detection circuit 24 sets the voltage line VDD applied to the source of the transistor T7 to about 2 of the floating gate voltage at the time of erasing the nonvolatile memories Ma ₁ , Ma ₂ ,.
Set to twice the voltage.

Further, the blocks 1a ₁ , 1b _1, ... Basically constitute a DRAM comprising capacitors and transistors. For example, the block 1a _1, the selection transistor Tsa with selection gate line ST ₁ as an almost word line
_1, constituting an auxiliary capacitor Ca ₁ capacitance Co consisting parasitic capacitance of the sub-bit line BLsa _1, and a DRAM cell comprising a non-volatile memory device Ma _1, Ma _2.

A write / erase or refresh operation is performed on a DRAM in a usual manner. DRA
The data once stored in M is transferred to a predetermined memory element (cell) of the nonvolatile semiconductor memory device.

When the floating capacitance due to the sub-bit line BLsa ₁ and the nonvolatile memories Ma _{1 and} Ma ₂ is small, it is not always necessary to provide the capacitor Ca ₁ . Although the parasitic capacitance is small with the miniaturization of the memory element, the floating capacitance is 10
If it is 0 pF or more, the capacitor can be omitted.

Referring to FIGS. 9A and 9B, the write / erase operation of the nonvolatile semiconductor memory cell shown in FIG. 7 will be described. FIG. 9A is a circuit diagram showing a main part of FIG. FIG. 9B shows a waveform applied to each part of the circuit. In FIG. 9A, T ₁ is a selection transistor, Ma ₁ is a nonvolatile semiconductor memory element, Co is a stray capacitance, and Ro is an equivalent resistance corresponding to a leakage current.
Hereinafter, a case where the leakage current can be ignored will be described.

First, write / erase operations will be described.
Threshold of non linear onset memory Ma ₁ is described as being more than 7V. The selection transistors T ₁ is turned on, a voltage of 5V is applied to the sub-bit line BLsa _1, the ground potential the potential of the source line, charges the sub-bit line BLsa ₁ (pre-charge). Thereafter, the OFF state of the selection transistor Tsa _1, the sub-bit line BLsa ₁ in a floating state.
The capacitance component CO including the capacitor Ca ₁ is charged.

Subsequently, the control gate of the nonvolatile memory Ma _{1 is connected to} the control gate of the nonvolatile memory Ma ₁ via the word line W ₁ as shown in FIG.
A pulse signal is applied. When the pulse of the negative (-10 V) to the control gate of the nonvolatile memory Ma ₁ is once applied, a tunnel current flows to the valency of the floating gate and the drain of the nonvolatile memory Ma _1, the threshold voltage Vth is sufficiently low , A channel current flows between the source and the drain. This channel current, the drain voltage (the potential of the sub-bit line BLsa ₁₎ decreases, the tunneling current between the floating gate and the drain does not flow, the threshold voltage of the nonvolatile memory Ma ₁ decreases, the threshold value of the non-volatile memory The voltage is set to a constant value.

Next, a case where the threshold voltage of the nonvolatile memory Ma ₁ is as low as 2 V will be described. First, as with the threshold voltage is high, the sub-bit line BLsa ₁ potential to 5V, the source potential and the ground potential, the selecting transistor T
₁ is turned off, and the sub-bit line BLsa ₁ is charged (precharged) to be in a floating state. The capacity component Co is in a charged state.

[0092] Subsequently, as in the case described above, through the word line W _1, as shown in FIG. 9 to the control gate, applying a pulse signal. When the nonvolatile memory device Ma ₁ positive voltage (3V) is applied, the source-drain channel current flows between the drain voltage is lowered, a negative voltage (-1
Even if 0 V) is applied, the tunnel wire does not flow between the floating gate and the drain. As described above, by applying the pulse of the positive voltage, the charge is not further extracted from the floating gate of the nonvolatile memory element having a low threshold voltage in the initial state. That is, the over-erased state does not occur.

Therefore, even if nonvolatile memories having different threshold voltages are simultaneously erased, no excessive erasure occurs. Therefore, it is not necessary to perform the operation of adjusting the threshold value by the writing operation before erasing, which is conventionally performed.

Referring to FIG. 10, another embodiment of the nonvolatile semiconductor memory device according to the second aspect of the present invention will be described.

The embodiment of FIG. 10 differs from the embodiment of FIG. 7 only in the configuration of the level shifter circuit, and the other circuit configurations are the same. The level shifter circuit 22 'includes a transistor (MOSFET) T ₈ ,
A CMOS inverter evening 26 consisting of T _9, a transistor (MOSFET) CMOS inverter 27 consisting of T _10, T _11, CMOS inverter 28 composed of transistors _{(MOSFET) T 12, T 13} , inverters I _1, I ₂
And speed-up circuit 2 consisting of the capacitor C ₁
9, and consists transistors T _14, T _15, the drain of the transistor T ₁₁ and the transistor T ₁₂ is connected in common and connected to the input terminal of the CMOS transistor 26,
0 V is applied to the connection point.

The output terminal of the CMOS inverter 27 is connected to the source of the transistor T ₈ , the output terminal of the CMOS inverter 28 is connected to the source of the transistor T ₉ , and the commonly connected sources of the transistors T ₁₁ and T ₁₂ are , And the input terminal of the CMOS inverter 26. The input terminal of the CMOS inverter 28, the drain of the speed-up circuit 29 and the transistor T ₁₅ is connected, the gate of the transistor T ₁₅ is connected to the output terminal, its source is connected to a negative voltage source.

In operation, CMOS inverter 2
The input terminal of the 7, 28, are applied pulse signal IN1, IN2 of the peak value of 5V, respectively, respectively, the source of the transistor T ₁₀ a positive voltage (3V) is applied, a negative voltage to the transistor T ₁₃ ( -10 V) is applied.

Next, based on FIGS. 11 (a) to 11 (c),
The operation of the level shift circuit 22 'will be described. FIG.
As shown in FIG. 1 (a), an "L" level signal is
Is input to the inverter 27, the transistor T ₁₀ is turned on, the transistor T ₈ is turned on. On the other hand, to the input terminal of the CMOS inverter 28, since the "L" level is input, the transistor T ₁₂ is kept off, the transistor T ₉ is also in the OFF state, CM
From the output terminal of the OS inverter 26, a voltage of 3 V is applied to the word lines W ₁ , W ₂ ,.

[0099] Subsequently, when "H" level signal is inputted to the CMOS inverter 27, the transistor T ₁₀ is turned off. On the other hand, since the "H" level is input to the input terminal of the CMOS inverter 28, the transistor T
₁₃ is turned on, and the transistor T9 is also turned on.
Voltage of 10V is applied to the word line W _1, W ₂ ,,,.

As a result, by applying a pulse signal as shown in FIG. 11C to the word lines W ₁ , W _2, ..., The threshold values of the nonvolatile memory elements are made uniform. Next, the case where the leakage of the charge stored in the sub-bit line is large will be described. When the value of the equivalent resistance Ro shown in FIG. 9A is small, that is, when the muddy current (leakage current) is large, the floating gate voltage _VFG hardly converges. FIGS. 12A to 12C show waveforms at various parts of the nonvolatile memory for explaining such a case.

As shown in FIG. 12C, when a pulse signal whose peak value oscillates from 5 V to -10 V is applied to the control gate to erase the nonvolatile memory element,
As shown in (a), the floating gate voltage V _FG oscillates according to the amplitude of the pulse applied to the control gate electrode. However, memory elements (a) having different floating gate voltages V _FG ,
(B) and (c) do not easily converge to the predetermined threshold voltage Vth. Further, as shown in FIG. 12B, the non-volatile memory elements (a), (b) and (c) have their bit line voltages VBL
Has dropped sharply.

Next, still another embodiment of the nonvolatile semiconductor memory device according to the second aspect of the present invention will be described.
FIG. 13A shows an embodiment in which the leakage current is large, and includes an electric current supply circuit for compensating the leakage current. That is, in the memory cell array 21, the resistance between the main bit lines BLa ₁ and sub bit line BLsa ₁ Ra ₁
Is connected. That is, when the leakage current is large, the charging voltage of the sub-bit line BLsa ₁ rapidly decreases. To avoid such an inconvenience, either via the resistor Ra ₁ to the sub-bit line BLsa ₁ equal to the leakage current, it is adapted to suppress a decrease in charging voltage heal subjected any more current. Resistance Rb ₁ are similarly connected. The configuration of the memory cell array 21 is the same as those in FIGS. The level shifter circuit may have the same configuration as in FIGS.

FIG. 13B shows an equivalent circuit of a main part of the circuit of FIG. 13A, and FIG. 13C shows a voltage waveform applied to each part. In FIG. 13B, Co indicates a capacitance component generated on the sub-bit line, Ro indicates an equivalent resistance set by a voltage applied to the sub-bit line and a leakage current, and Ra _{1 according to} the fourth aspect. a ₁ is equal to the leakage current, a resistor for supplying a further current.

Referring to FIGS. 14A to 14C, still another embodiment of the nonvolatile semiconductor memory device according to the second aspect of the present invention will be described. In FIG. 14A, a memory cell array 21 has the same configuration as that of the above-described embodiment, and a current supply circuit for compensating a current for compensating for a leakage current includes:
It consists series connected transistors Ta and (MOSFET) by resistance Ra _1, transistor Ta to the main bit lines BLa ₁
The drain of the connection, its source connected to one end of resistor Ra _1, the other end of the resistor Ra ₁ is connected to the sub bit line BLsa _1. Further, the transistor Tb and the resistor Rb ₁
Has a similar configuration.

In this embodiment, by turning on the transistor Ta, the electric charge accumulated in the sub-bit line can be held for a long time. Therefore, a DRAM (dynamic RAN) can be configured by using the selection transistor Tsa ₁ as a transfer gate and using the sub-bit line as a capacitor. The reading of this dynamic RAM, and the transistor Tsa ₁ is turned on, by applying a low voltage (1 to 2 V) to the memory cell is carried out by measuring the cell current.

The operation of charging the floating gate is performed by closing the selection transistor Tsa ₁ and applying a sufficiently high voltage to the word line to inject electric charge into the floating gate by hot electrons, or between the substrate and the word line. A method of giving a sufficiently high potential difference and charging the floating gate by a tunnel current through a thin oxide film can be used. In addition, the operation of extracting charge from the floating gate is performed by setting the main bit line BLa ₁ to the higher potential side, turning on the selection transistor Tsa ₁ , turning off the transistor Ta, and passing the high resistance to the sub-bit line, which is equal to the leakage current. Or by supplying a higher current. Of course, the resistors Ra ₁ , Rb ₁
, A diode connected in reverse bias may be used.

In the embodiment shown in FIGS. 13A and 13B, the first time constant due to the equivalent resistance Ro and the capacitance component Co is larger than the second time constant due to the resistance Ra ₁ and the capacitance component Co. Set to a small value. For example, if the resistance value of the resistor Ra1 is 100 MΩ, the second time constant with the capacitance component Co including the stray capacitance is set to about 15-50 μsec, and the period of the pulse applied to the floating gate of the nonvolatile memory is Set to about 30 μsec. In this way, the second time constant is made smaller than the first time constant, and the second time constant is made shorter than half the period of the pulse applied to the control gate of the nonvolatile semiconductor memory cell. This is for the following reason.

[0108] When the leakage of the charge accumulated in the bit line is large, when the current is supplied through a resistor Ra ₁ to the drain electrode of the nonvolatile memory cell, the supply current must be greater than the leakage current. However, for memory cells where the electrons in the floating gate have been sufficiently extracted,
No further electron pulling occurs. In other words,
No further current supply to restore the drain potential takes place. The time required to recover the drain potential is defined by the second time constant. Therefore, it is desirable that the second time constant is smaller than the first time constant and is about half of the period of the applied pulse.

FIGS. 15A to 15C show the operation states of the nonvolatile memories (A) and (B) having different floating gate voltages _VFG . A pulse signal g that changes between a positive (3 V) and a negative (−10 V) potential and has a period of about 30 μsec is applied to the floating gate. As shown in FIG.
The floating gate voltage _VFG fluctuates according to the pulse period. Floating memory (A), gradually converges to the floating gate voltage V _FG is a predetermined voltage (B).

On the other hand, as shown in (b) of FIG. 15B, the bit voltage VBL (drain voltage) of the memory (b)
Pulsates due to the drop due to the leakage current and the rise due to the supply current as the charge of the floating gate is extracted.
However, as shown in (a) of FIG. 15B, the drain voltage of the memory (a) keeps a sufficiently high potential until the electric charge accumulated in the floating gate is sufficiently extracted. Is completed, the drain voltage begins to pulsate due to the rise due to the supply current and the fall due to the leakage current.

The leakage current is compensated by a gated diode as shown in FIG. A P-type well region 31 is formed in the N-type semiconductor layer 30, and N-type source / drain regions are formed in the P-type well region 31. A gate electrode 33 is formed in the channel region.

The main bit line is the N-type source / drain region 1
2s and 12d are connected to the N-type semiconductor layer 10. The word line is connected to the gate electrode 13, and the P-type well region 11 is connected to the sub-bit line. In such a structure, by synchronizing the pulse signal applied to the gate electrode 13 with the voltage applied to the word line, fluctuations in drain voltage can be reduced.

The leakage current is considered to be caused by a tunnel current between the floating gate and the drain caused by the negative gate current, a crystal defect around the drain diffusion layer, and the like. The former is the main factor.

In this embodiment, since the current is supplied to the drain in synchronization with the leakage current, the drain voltage fluctuation can be reduced.

As described above, the nonvolatile semiconductor device according to the second aspect of the present invention supplies a current larger than the leakage current to the sub-bit line to maintain the potential precharged to the sub-bit line or the main bit line. The current supply means is provided. That is, the current source consisting of the voltage source and the resistor shown in the embodiment is connected to the sub-bit line or the main bit line. This current source circuit is not limited to those used in the embodiments, but can be realized by some known circuits.

Needless to say, the memory cell array is not limited to the above embodiment. For example, when a source line and a sub-bit line are provided, a leakage current can be compensated by connecting a current supply circuit to the source line and the sub-bit line. In this case, the drain of the transistor Ta ₁ is connected to the sub-bit line, its source connected to the source line.
The memory cell array may be composed of a plurality of blocks each having a plurality of nonvolatile semiconductor memory cells connected to the main bit line.

As described above, according to the second aspect of the present invention, a sub-bit line is precharged and a positive / negative oscillating pulse signal is applied to the floating gate of the nonvolatile memory cell via the level shifter circuit. Therefore, different floating gate voltages can be converged to a predetermined voltage, and there is an advantage that the writing / erasing operation can be performed by extremely simple means.

Further, even if the potential of the charging voltage stored in the sub-bit line is reduced by the leakage current, the electric wire supply means for supplying the leakage current provides the potential of the sub-bit line. And the stored charge in the floating gate can be erased. Therefore, a predetermined threshold value can be reliably set for the nonvolatile memories having different floating gate voltages.

Further, according to the nonvolatile semiconductor memory device of the second aspect of the present invention, since the precharge is sufficiently performed, a stable operation as a DRAM can be performed.

(Third Aspect) Various embodiments of the nonvolatile semiconductor memory device according to the third aspect of the present invention will be described with reference to the drawings. FIG. 17A is a circuit diagram of one embodiment of a nonvolatile semiconductor memory device. As shown in FIG. 17A, the nonvolatile semiconductor memory device includes a memory self-lay 41 using a nonvolatile memory, a pulse peak value setting circuit 42, a switch circuit 43 (for example, a multiplexer),
And peripheral circuits (not shown) such as a row / column decoder and a sense amplifier circuit.

[0121] In the memory cell array 41, the drain of the select transistor Tsa ₁ is connected to the main bit lines BLa _1, the source of the select transistor Tsa ₁ is connected to the sub-bit line. The drains of the memories Ma ₁ and Ma ₂ are connected to the sub-bit line BLsa ₁ , and the commonly connected sources are connected to the drains of the source-side selection transistors via the source lines. Source-side selection transistor T
The source side select SL ₁ to the control gate of the rs ₁ is connected. A capacitor is connected between the source and the drain of each of the memory elements Ma ₁ and Ma ₂ .

On the other hand, the drain of the selection transistor Tsb ₁ is connected to the main bit line BLb ₁ , and the sub-bit line BLsb ₁ is connected to the source thereof, and the memory element Mb
₁ and Mb ₂ have a capacitor Cb
₁ is connected. When the parasitic capacitance due to the sub-bit line BLsa ₁ and the nonvolatile memory cells Ma ₁ and Ma ₂ is relatively small, it is not necessary to provide a capacitor. Parasitic capacitance tends to decrease with miniaturization of the memory element. If the stray capacitance is 100 pF or more, the capacitor Ca ₁ can be omitted.

The word line W ₁ is connected to the memory elements Ma ₁ , Ma ₂
And the word line W ₂ is connected to the memory element M
a ₂ and Mb ₂ are connected to control gates. The word lines W ₁ , W ₂ ,... Are connected to the switch circuit 43. The switch circuit 43 (which may be a switch) outputs the output pulse signal from the pulse peak value setting circuit 42 to the word lines W ₁ and W ₁ .
₂ , ,... Are continuously applied.

A plurality of memory cells may be formed as one block, and the word lines of the memory elements in each block may be shared, and the charges accumulated in the memory elements may be sequentially erased.

Next, the configuration of the pulse height setting circuit 42 will be described.
Will be described. P-channel transistor evening (MOSFE
T) T₁And N-channel transistor (MOSFET)
T_TwoTo form a CMOS inverter, and the transistor T₁of
Source is transistor T₃₄, T_FourConnected to the
Star T_TwoIs connected to a negative voltage source (-10V).
And the transistor T₁, T_TwoDrain speed up
Transistor T _FiveConnected to the gate of the
Star T_FiveOf the transistor T₁, T_TwoCommon connection of
Connected gate and transistor T6 for self-bias.
Connected to source. Transistor T3 and transistor
Star T_FourAre connected to the first voltage source (4
And a second voltage source (5 volts)
Are commonly connected.

[0126] In the pulse wave height value setting circuit 42, the input signal IN1 is input to the drain of the transistor T _6, is input to the drain of the input signal IN2 transistor T _6, is input, the input signal IN2 is transistor T _3,
Is input to the gate of T _4. From the output stage of circuit 42,
As shown in FIG. 17, 4 pulses superimposed between a positive pulse of 5 V (peak value) and a positive pulse of 5 V (peak value) in a predetermined cycle.
An output pulse obtained by combining a positive pulse of V (peak value) and a negative pulse of -10 V (peak value) is selectively supplied to the word lines W ₁ , W ₂ ,. Applied.

The output pulse signal from the pulse crest value setting circuit 42 is applied to the control gate of the memory element via the switch circuit 43 and the word line, and the charge accumulated in the floating gate of each memory transistor in a floating state is extracted. ,
The threshold voltage is adjusted to a predetermined value or range.

FIG. 18 shows another embodiment of the nonvolatile semiconductor memory device according to the third aspect of the present invention. Pulse peak value 42 shown in Figure 18, differs from the embodiment of FIG. 17 (a), the source of transistor T ₁ of the CMOS inverter in is connected to a voltage source 4V, transistor T
₄ is connected to the source and its drain is a voltage source (5V)
Connected to. Other circuit configurations are the same. FIG.
Input signals IN1 and IN2 different from those of (b)
Is input, the generated output pulse signal is the same as that of FIG. 17 (b).

Referring to FIGS. 19A to 19C, FIG.
The operation of the circuit of FIG. FIGS. 19 (a) to 19 (c)
Floating gate voltage V_FG, Drain voltage (bit line voltage
Pressure V _BL) And control gate voltage V_CGFIG.

The pulse signal shown in FIG. 19 (c) is a pulse (A) having a positive potential peak value of 3 V at a predetermined period, and a positive potential peak value superimposed between these pulses (A) being 2V. .5
A pulse (B) of V and a pulse having a peak value of −10 V of the negative potential are included. Such a pulse signal is applied to the control gate. The peak value of the positive potential pulse applied to the control gate is not limited to 3V, but may be 5V.

The peak value of the pulse (B) is 2.5 V
May be set to -5V. Also, this value may be set and fixed in a range of 3V (or 5V) to -10V.
It is not limited to the pulse (B) of 5V or -5V.
In operation, the selection transistors Tsa ₁ and Trs ₁ are turned on, and the sub-bit line BLsa ₁ and the capacitor Ca ₁
After that, the selection transistor Tsa ₁ is turned off, and the memory transistors Ma ₁ and Ma ₂ are set in a floating state. Subsequently, the pulse signal as shown in FIG. 19 (c) (the control gate voltage V _CG) is applied to the word line W1 via the switch circuit 43, charges accumulated in the floating gate of the memory transistor Ma ₁ is Pulled out. FIG.
(A), (b), as shown in (c), different floating gate voltages V _FG converges at about 300.0Myusec.
The bit line voltage V _BL corresponds to (a), (b),
The waveform is as shown in FIG. (A) of FIG.
The difference between the waveforms (b) and (c) is caused by the initial value of the floating gate voltage and the leakage current generated in the bit line.

FIG. 20 shows a nonvolatile memory according to the third aspect of the present invention.
7 shows another embodiment of the nonvolatile semiconductor memory device. Pulse peak value
The setting circuit 44 includes a switch circuit 44 and a voltage source circuit 45.₁,
45_TwoAnd 45_Three, And the switch circuit 44 is
Buffa 44₁a, switch 44₁b, buffer 44_Twoa, sui
Switch 44_ThreeIt consists of b. Switch 45₁, 45
_Two, 45_ThreeAre connected in common and connected to the switch circuit 43
Have been. Power supply circuit 45 ₁, 45_Two, The voltage from (3
V) and (-5V) are output, and the buffer 44₁a, 44_Twoa
Through the switch 44₁b, 44_Twob and the voltage source 4
The voltage (−10 V) from the switch 53_Threeentered in b
You.

The operation of the embodiment of FIG. 20 will be described with reference to FIG. FIG. 21A shows an equivalent circuit of the switch circuit 44 in FIG. Switch 44 ₁ b~44 ₃ b are respectively denoted as a to c. The timing of the selection signal for controlling these switches is shown in FIG. The output of the switch circuit 44 is shown in FIG.

[0134] The switch a is turned on at the timing t _1,
When the other switches b and c are turned off, the output becomes 3 V
A (peak value) positive potential pulse is output. The switch c is turned on at timing t _2, when turning off the other switches, the pulse of the negative electric potential of -10 V (peak value) is outputted. At timing t _3, the switch b is turned on, when to turn off the other switches, the pulse of the negative electric potential of -5V is output. As described above, by controlling the switches a, b, and c, the combined pulse is applied to the control gate of the memory element via the switch circuit 43.

FIG. 22 shows another embodiment of the nonvolatile semiconductor memory device according to the third aspect of the present invention. FIG.
As shown in FIG. 2A, the switch circuit 44 includes a switch A
1, B1, C1, A2, B2, and C2. One ends of the switches A1 and A2 are connected to a voltage source (3V) 451,
One end of each of the switches B1 and B2 is connected to a voltage power supply circuit (−5V) 4
52, and one ends of the switches C1 and C2 are connected to a voltage power supply circuit (−10 V) 453. Switch A1,
The other ends of B1 and C1 are commonly connected, and the other ends of switches A2, B2 and C2 are commonly connected, and are connected to a word line via a switch circuit 43 (for example, a multiplexer).

The synthesized pulse will be described with reference to FIGS. 22 (b) and 22 (c). Switch A1 at the timing t ₁
The When turned on, the pulse of the positive potential of 3V (peak value) is outputted, when turning on the switch C1 at the timing t ₂ -
A pulse of a negative potential of 10 V (peak value) is output. Then, when you turn on the switch B1 at the timing t _3, one 5
V pulse of negative potential is output (peak value), the switch C2 is turned on at a timing t _3, -10 V (peak value)
Is output.

As the extraction of the charge from the floating gate is completed, the pulsation of the drain voltage becomes a noise when detecting a decrease in the drain voltage, and interferes with the detection of the threshold voltage of the memory. This pulsation can be reduced by reducing the pulse width in the word line, but causes an increase in current consumption. However, the three levels A, B, and C of the pulse signal applied to the control gate are changed to 3 V and -5, respectively.
By setting V and -10 V and setting the B level to a potential as negative as possible, the amount of charges charged and discharged via the word lines can be reduced, and the current consumption can be reduced.

Of course, a large leakage current interferes with the erase / write operation, which can be compensated for by the current supply means supplying a current equal to the leakage current generated by the memory element.

FIGS. 23A and 23B show a third embodiment of the present invention.
9 shows another embodiment of the nonvolatile semiconductor memory device according to the aspect.
And a NAND gate type EEPROM. FIG.
1A, a memory element (cell) M₁~ M_ThreeIs for selection
Transistor Ts₁, Ts_TwoConnected in series between them
Control gate electrodes each have a word line W ₁~ W_ThreeConnected to
Have been. Selection transistor Ts₁The drain of the
The power supply voltage is connected to the reset line BLa1 via the resistor R1.
(5V). ST ₁, ST_TwoIs the selection line
You.

The potential of each word line required to extract charges from the floating gates of the cells M _{1 to} M ₃ is shown in the table of FIG. For example, when the cell 1 is to be erased, the select lines ST ₁ , ST ₂ and the word lines W ₂ , W ₃ are set to “H” level, and the above-described pulse is applied to the word line W ₁ to ensure the erasure. Electric charges accumulated in the floating gate can be extracted. Of course, the pulse signal here may be constituted by a pulse that fluctuates between positive and negative potentials. Resistor R ₁ is the resistance for supplying a small current, which is the simplest leakage current supplying means. The only bit line when the capacity of the capacitor is insufficient, adds Capacity evening C _0.

As described above, in the nonvolatile semiconductor memory device according to the third aspect of the present invention, a pulse signal varying between a positive potential and a negative potential is applied to the control electrode of the memory element, and the pulse signal is stored in the gate. This is to erase and write by extracting the charged electric charge. When a pulse having a peak value higher than the normal potential is applied at a predetermined cycle, the channel conductor of the memory element temporarily rises and the drain potential changes rapidly, so that it is easy to reduce the threshold voltage. Can be detected.

Further, applying a pulse having a potential higher than a predetermined potential means that the word line is charged / discharged at high speed, and current consumption increases. However, this disadvantage can be eliminated by charging the low (negative) potential pulse during the high potential pulse. That is, it contributes to setting the high-potential pulse threshold voltage, and the current consumption can be reduced when the negative potential pulse is charged. According to the third aspect of the present invention, by performing a erase operation and a write operation by applying a pulse signal to a word line, a stable threshold voltage can be detected and the operation time can be reduced. it can. Further, according to the present invention, a large number of memory transistors can simultaneously extract the charge from the floating gate, and the threshold voltages can be precisely aligned.

(Side 4) Referring to the drawings, the fourth aspect of the present invention
An embodiment of the nonvolatile semiconductor memory device according to the aspect will be described. First, for the purpose of comparison with the fourth aspect, the above-described improvements required for the present invention will be described. Means for capturing the threshold voltage of the floating gate type memory transistor has been proposed by the present inventors. In the proposed method, a pulse is applied to the control gate of the memory transistor in a floating state, and the charge stored in the floating gate is extracted to make the threshold voltage uniform. FIGS. 40A and 40B show an equivalent circuit diagram showing the outline thereof and an operation waveform diagram thereof.

In FIG. 40A, To is a selection transistor, and Mo is a nonvolatile memory transistor. In the operation, as shown in the waveform diagram of FIG. 40 (b), a voltage of 5V is applied to the drain of the selection transistor To as an electrical reduction voltage, and a voltage of 5V is applied to its control gate. Thereafter, the drain of the memory transistor Mo is brought into a floating state. Subsequently, a pulse that oscillates positively and negatively at a predetermined cycle is applied to the control gate of the memory transistor Mo to extract surplus electrons and lower the threshold voltage. An example of a pulse generation circuit is shown in FIG. In FIG. 41, the CMOS inverter is a PMO
A self-biased transistor is connected to an input stage of the transistor Ta and an NMOS transistor Tb, and a drain and a control gate of the speed-up transistor Ta are connected to input / output terminals thereof, respectively.
A 3V voltage source is connected to the source of the PMOS transistor Ta, and -1 is connected to the drain of the NMOS transistor Tb.
A voltage source of 0 V is connected.

FIG. 41 (b) shows an input signal IN having a peak value of 5V, and FIG. 41 (c) shows an output signal OUT of -10V to 3V. FIGS. 42A to 42C show changes in the potentials of the floating gate and the bit line when a pulse-like control voltage _VCG is applied to the control gate of the memory transistor. That is, when the pulse shown in FIG. 42 (c) is applied to the control gate, as shown in (a), (b) and (c) of FIG. floating gate electrode Mr V _FG converges to a predetermined threshold voltage value at approximately 100 .mu.sec. In that case, the bit line voltage fluctuates as shown in (a), (b), and (c) of FIG. However, when the equivalent resistance R1 is small, a large leakage current flows. As a result, FIG.
As shown in the waveform of the floating gate V _FG (a), (b),
(C) does not converge even after 200 μsec has elapsed.

Referring to FIG. 24, memory cell array 62
Memory element (MOSFET) M₁₁, M₁₂, M_{twenty one}, M_{twenty two}Or
Become. Select transistor T₁, T_TwoEach in the source
Bit line BL₁, BL_TwoIs connected. Secondary bit
Line BLs₁Has a memory element M ₁₁, M_{twenty one}Drain connected
And the sub-bit line BLs_TwoHas a memory transistor M₁₂,
M_{twenty two}Of the memory transistor M₁₁,
M₁₂, M_{twenty one}, M_{twenty two}The source of each is source line S₁But
Connected, source line S₁Of the selection transistor Ts
Connected to drain. SL₁, ST₁Is the selection line
, WL₁, WL_TwoIs a word line.

The bit lines BL ₁ and BL ₂ are connected to the minute current supply circuits 66 and 67 and also to the column decoder 64. The word lines WL ₁ and WL ₂ are connected to a column decoder 62 via a word drive circuit 63. The word lines WL ₁ and WL ₂ are supplied with a pulse signal for erasing / writing from a pulse generating circuit 65 via a word drive circuit 63. A clock signal φ and a clock signal φ bar are applied to the minute current supply circuits 66 and 67, respectively.

At the time of the erasing operation, a pulse signal oscillating positively or negatively is applied from the pulse generating circuit 65 to one of the selected word lines WL ₁ and WL ₂ . In the erase operation, in accordance with the operation of the column decoder circuit 64, from any of the current supply circuits 66 and 67, sub-bit lines BLs ₁ or B
Ls ₂ (source or drain of memory transistor)
Current is supplied via the selection transistors T ₁ or T ₂ in. The current supplied from the minute current circuit 66 or 67 corresponds to leakage current (3 to 5 nA) from the source or drain of the memory element. Thus, FIG.
Inconvenience in the erasing / writing operation described in relation to (a) and 40 (b) can be avoided.

The minute current supply circuits 66 and 67 can apply a predetermined charging voltage to the sub-bit lines BLs ₁ and BLs ₂ via the selection transistors T ₁ and T ₂ to supply a minute current to the drain of the memory element. The predetermined charging voltage can be supplied from, for example, a charging circuit including a transistor and a capacitor.

The minute current supply circuits 66 and 67 are shown in FIGS.
8 and the switched capacitor shown in FIGS.

Referring to FIG. 25, another embodiment of the nonvolatile semiconductor memory device according to the fourth aspect of the present invention will be described. The embodiment of FIG. 25 differs from the embodiment of FIG. 24 in the following points. The bit lines BL ₁ and BL ₂ are connected to a column decoder circuit 64, and the minute current supply circuit 68 is connected to the column decoder circuit 64. The minute current supply circuit 68 to which the clock signals φ and φ bar are applied is controlled by the transistor 64. The minute current from the minute current supply circuit 68 is supplied to the main bit line B via the column decoder circuit 64.
L ₁ , BL ₂ and the selection transistor T
It is supplied to sub-bit lines BLs ₁ and BLs ₂ via 1 and T2. The transistor T ₃ to which the control signal is supplied to the control gate operates according to the operation timing of the column decoding circuit 64. In this case, the column decoder circuit 68 operates to supply a very small current through the column decoder circuit 64.
The other circuit configuration is the same as that of FIG.

The minute current supply circuit 68 is composed of a charge pump circuit and a switch circuit on the same line as the embodiment of FIG. 24, and supplies a minute current corresponding to a leakage current for each main bit line.

Referring to FIG. 26, still another embodiment of the nonvolatile semiconductor memory according to the fourth aspect of the present invention will be described. The embodiment of FIG. 26 differs from the embodiment of FIG. 24 in the following points. The minute current supply circuits 66 and 67 include transistors T whose control gates are controlled by a column decoder circuit 64.
4, connected to T5. Micro current supply circuits 66, 6
7 sets the potential for each bit line. Micro current supply circuit 6
The circuits 6 and 67 are constituted by the same circuits as the embodiment of FIG. 24, and the other circuit constitutions are the same as those of the embodiment of FIG.

In this embodiment, as in the embodiment of FIG. 25, the minute current supply circuits 66 and 67 are controlled by transistors T ₄ and T ₅ , respectively, and supply a minute current to each bit line. Next, an embodiment of the minute current supply circuits 66 and 68 will be described with reference to FIGS. FIG.
Denotes a minute current supply circuit 70 including a charge pump. In FIG. 27, self-biased transistors T ₆ , T ₇ , and T ₈ are connected in series. The coupling capacitor C ₁ is connected to the connection point between the transistors T ₇ and T _8.
There are connected, the coupling capacitor C ₂ to a connection point of the transistor T _6, T ₇ are connected. Coupling the clock signal φ through the capacitor C ₁ is applied, the clock signal φ bar is applied through the coupling capacitor C _2. The output OUT of the charge pump circuit is applied to the bit lines BL ₁ and BL _{2 respectively} .

The clock signals φ and φ bar have a peak value of 5 volts and a frequency of 1 MHz. Inverted clock signals φ and φ bar are applied to each connection point, and a predetermined voltage is supplied to the bit line from the transistor T8. A predetermined voltage is applied to the bit line via the charge pump circuit, and a minute current I1 (about 3 to 5 nA) is supplied to the sub-bit line via the ON-state selection transistor. The coupling capacitors C ₁ and C ₂ are _{1 to} 100 f
F capacity. The value of the minute current I1 is set by the clock frequency and the oscillation frequency. The supply current I1 is supplied to the bit line and charged as a line capacitance. The clock signal used in this embodiment has a clock frequency of 1 MHz and a peak value of 5V. Parasitic capacitance of bit line 1p
F. The value of the minute current I1 is the leakage current IL (3-5
It is set arbitrarily by the value of V).

FIG. 28 shows a charge pump circuit for obtaining a higher potential. To the ground of the charge pump circuit of Figure 27, the transistor T ₉ is connected in series which are self-biased. The connection point between the transistors T ₆ and T _9, the coupling capacitor C3 is connected, the clock signal φ is applied through the coupling capacitor C _3, the other coupling capacitor C _1, C ₂ 27
The same clock signal is applied. Its output OUT
Is applied to the bit line. The capacitor C ₄ indicates a bit line parasitic capacitance (about 1 pF), T ₁ is a selection transistor, and M is a memory transistor. The transistors T _{6 to} T ₉ are MOS transistors.

FIGS. 29A to 29E are waveform charts showing the operation states of the circuit of FIG. Referring to FIG.
The operation of the nonvolatile semiconductor memory device including the charge pump will be described. ON-state selection transistor T
_A power supply voltage (5 V) is applied to the drain of the memory ₁ to store the memory T ₁
Charge the drain or source. Supplying a small current I1 (3-5V) to the drain of the memory element M through the selecting transistor T ₁ of the on-state. Thus, the drain of the memory element M is set to a substantially floating state. Thereafter, the word line W is connected to the control gate of the memory transistor M.
A pulse signal as shown in FIG. 29 is applied via L to perform an erase / write operation. When the surplus electrons are drawn out and the threshold voltages are uniform, the channel contactance of the memory transistor is about 1 MΩ.

On the other hand, in the charge pump circuit, clock signals φ and φ having a frequency of 1 MHz and a peak value of 5 V are connected to connection points A, B and C via cup link capacitors C ₁ , C ₂ and C _3. Respectively. Waveforms at the connection points are shown in FIGS. 29 (a) to (d).

[0159] As is apparent from the waveform diagram of FIG. 29 (a) ~ (e) , when applied through a clock signal φ through the coupling capacitor C _3, a charge to the transistor T ₉ is charged, A The potential at the point increases. At the same time, B
Clock signal φ bar whose phases are inverted is applied to the point, is charged to the transistor T _6. The generated potential is A
Superimposed on the point. Thus, the potentials are sequentially superimposed and a potential as shown in FIG. 29 is applied as the voltage of the bit line BL.
Thereafter, a very small current is supplied to the source / drain of the memory element M via the on-state selection transistor T1.
A pulse-like signal as shown in (e) is applied to extract the residual charge charged in the floating gate, thereby making the threshold of the memory element uniform.

FIG. 30 shows a switched capacitor circuit used as the minute current supply circuits 66 to 68. FIG.
As shown in, the voltage source E0 is connected to the drain of the transistor T _10, a source connected to the drain of one end transistor T ₁₁ of Capacity evening C _5, the source of the transistor T ₁₁ is connected to the bit line BL ing. Bit line BL is its parasitic capacitance of about 1 pF, the capacitance of the capacitor C ₅ is about 15pF.

The control gates of the transistors T ₁₀ and T ₁₁
Clock signals φ and φ bar are respectively applied, and the transistors T ₁₀ and T ₁₁ are alternately turned on. "H" level pulse is applied to the control gate of the transistor T _10,
The transistor T ₁₁ is simultaneously since "L" level signal is applied, the voltage Eo of the capacitor C ₅ is charged is applied. Next, when "L" level signal to the control gate of the transistor T ₁₀ is applied, turned off, since the transistor T ₁₁ is "H" level signal is applied, turned on. The capacitor C _5, the charge has been charged voltage is output via the transistor T _11,
It is charged to the parasitic capacitance C ₆ of the bit line. As described above, a predetermined voltage is applied to the bit line BL by alternately operating the transistors T ₁₀ and T ₁₁ . In addition,
The capacitor C5 is selected to have a small capacitance of 1 to 100 fF. The frequency and amplitude of the clock signal φ and φ bar are selected to be optimum values so that a minute current is supplied to the bit line BL.

FIG. 31 shows operation waveforms when a switched capacitance circuit is used as a minute current supply circuit. Clock signals φ and φ are applied to the control gates of the transistors T ₁₀ and T _11.
When the bar is applied, the capacitor C ₅ is charged gradually, the potential of the connection point of the transistors T _10, T ₁₁ is increased. As a result, an output voltage having a waveform as shown in FIG. 31A is applied to the bit line BL. At that time, FIG.
A pulse signal as shown in FIG. 1 (c) is applied to the control gate of the memory element. As a result, different floating gate voltages V _FG are aligned with a predetermined threshold. The bit line voltage V _Bl is shown in FIG.
The waveform is as shown in FIG.

FIG. 32 shows another embodiment of the switched capacitor. In the circuit of FIG. 30, transistors T ₁₁ and T ₁₃
There is further connected, diode-connected MOS transistors to the connection point of the transistor T ₁₁ and T ₁₃ are connected. As a result, since noise components can be removed, a stable output can be applied to the bit line. Transistor T ₁₀ ~T ₁₃ is a transistor of the MOS type. The waveforms at each point of the capacitor circuit of FIG.
This is shown in (d).

FIG. 34 shows another embodiment of the nonvolatile semiconductor memory device according to the fourth aspect of the present invention. In this embodiment, the memory cell array 61 has the same structure as that shown in FIG. The minute current circuit 70 is connected to the sub-bit line B via the switch circuit 71 (for example, a multiplexer).
Ls ₁ and BLs ₂ are connected. Micro current supply circuit 71
Can be connected to the sub-bit line of the adjacent memory cell array via the switch circuit 71. The capacitance of each of the auxiliary transistors Ca and Cb is about 100 to 300 fF.

The erase / write operation in this embodiment is executed as follows. After the drain (or source) of the memory element is charged to a positive potential, the selection transistor is turned off. A minute current (approximately 3 to 5 nA) is applied to the drain (bit line) to bring it into a floating state. The charge stored in the floating gate is reduced by applying a pulse signal to the control gate of the memory element, and the write / erase operation is performed. A small current is supplied to the sub-bit line via the switch circuit 71 during the erase / write operation.

FIGS. 35 to 37 show still another embodiment of the nonvolatile semiconductor memory device according to the fourth aspect of the present invention. In the above-described embodiment, the bit line is charged by using a charge pump or a switched capacitor circuit as a micro electric circuit. On the other hand, the embodiments shown in FIGS. 35 to 37 are intended to improve the response characteristics of charging and discharging to enhance the high-speed erasing / writing performance.

The embodiments shown in FIGS. 35 to 37 correspond to bit lines.
Charging / discharging system is added to the embodiment of FIGS.
It is characterized by. In FIG. 35, bit line BL₁,
BL_TwoAre the transistors T₆, T ₇To the source
It is connected. The drain of these transistors is a voltage
Connected to source Vcc. The other circuit configuration is that of FIG.
Is the same as In operation, the transistor T₆, T
₇A charging signal Sc is applied to the source of the
_Four, T_FiveThe discharge signal Sd is applied to the gate of. Erasure
At the start of the write operation, a charging signal is applied. End
Sometimes, the discharge signal Sd is applied to the bit line BL.₁, BL
_TwoThe electric charge stored in the battery is discharged.

In FIG. 36, bit line BL ₁ is connected to the connection point between transistors T ₈ and T ₉ and bit line BL 1
₂ is connected to the connection point between the transistors T ₁₀ and T ₁₁ . The transistors T ₉ and T ₁₁ constitute a charging system. Charge signal S
By applying c ₁ and Sc ₂ to the gates of the transistors T ₉ and T ₁₁ respectively, the bit lines BL ₁ and BL ₂ are charged to perform the erase / write operation. Further, the transistors T ₈ and T _{10 form} a discharge system. At the end of the erase / write operation, the discharge signals Sd ₁ and Sd ₂ are applied to discharge the charges charged in the bit lines BL ₁ and BL ₂ .

In FIG. 37, the bit line BL ₁ is connected to the connection point between the transistors T ₈ and T ₉ and the bit line BL ₂
Is connected to a connection point between the transistors T ₁₀ and T ₁₁ . The transistors T ₉ and T ₁₁ constitute a charging system. By applying a charging signal Sc to the gates of the transistors T ₉ and T ₁₁ , the bit lines BL ₁ and BL ₂ are charged, respectively, to perform the erase / write operation. Also, the transistor T ₈ ,
T ₁₀ constitute a discharge system. The gates of the transistors T ₈ and T ₉ are connected in common, and at the end of the erase / write operation, a discharge signal Sd is applied to the bit lines BL ₁ and BL ₂
Is discharged.

In the embodiments shown in FIGS. 35 to 37, a charge signal is applied to the bit line by a charge pump circuit or a switched capacitor circuit before a predetermined potential is applied to the bit line, whereby the charge signal is higher than the source potential. Charge the bit line to potential. Thereafter, a pulse signal is applied to the word line to equalize the threshold value of a predetermined memory element. Therefore, the erasing / writing operation can be performed at high speed. On the other hand, after the erasing / writing operation is completed, the bit line is set to a potential lower than the drain potential so that the next operation can be performed in a short time.

As described above, in the nonvolatile semiconductor memory device according to the fourth aspect of the present invention, a very small current is supplied to the bit line or the bit line is charged, and then the selection transistor is turned off. A small current corresponding to the leakage current is supplied to the bit line. Thereafter, a pulse signal is applied to the control gate of the memory element to make the thresholds uniform. Since the minute current is supplied to the bit line while the channel conductance of the memory element is at a large value, it is necessary to prevent excessive bleeding due to excessive extraction of electric charge or to recover the potential on the drain side. It is preferable to apply a pulse signal having a pulse width shorter than the recovery time to the control gate.

Although a charge pump circuit or a switched capacitor circuit capable of setting the current value to a frequency and a peak value can be used, various known circuits capable of supplying a small current can be used. good.

The nonvolatile semiconductor memory device according to the fourth aspect of the present invention relates to an erase / write operation for extracting charges from the floating gate, and the method of injecting electrons into the floating gate is not different from the conventional method. Therefore, the present invention can be applied to a nonvolatile semiconductor memory device of a system in which a floating gate is charged to a negative potential by hot electrons from a channel and released from the floating gate to a source, a drain or a substrate by a tunnel current.

In the nonvolatile semiconductor memory device according to the fourth aspect of the present invention, the bit line is set to a substantially floating potential by a small current, and a pulse signal that changes between positive and negative potentials is applied to the control gate of the memory element. Excess charge accumulated in the floating gate is extracted to perform erasing / writing. Even if there is a leakage current from the bit line (drain or source), a minute current is supplied to the bit line by the minute current supply circuit, so that charges can be simultaneously and accurately supplied from the floating gates of many memory elements. . Further, by performing the erase / write operation after charging the bit line, the rise time of the charged potential can be reduced.

[Brief description of the drawings]

FIG. 1A is a principle circuit diagram of a nonvolatile semiconductor memory (cell) according to a first aspect of the present invention, and FIG. 1B is a waveform diagram showing the operation of the memory shown in FIG. is there.

2A is a circuit diagram showing the principle of a nonvolatile semiconductor memory (cell) according to a second embodiment of the present invention, FIG. 2B is a waveform diagram showing the operation of the memory shown in FIG. FIGS. 2C and 2D show the state shown in FIG.
FIG. 3 is a waveform diagram of a pulse applied to the gate of the memory shown in FIG.

FIG. 3 is a circuit diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

4A is a waveform diagram of a pulse applied to a word line of the memory shown in FIG. 3, FIG. 4B is a diagram showing a potential of a floating gate of the memory shown in FIG. 3, and FIG. FIG. 4 is a diagram showing potentials of bit lines of the memory shown in FIG.

5A is a waveform diagram of a pulse applied to a word line of the memory shown in FIG. 3, FIG. 5B is a diagram showing a potential of a floating gate line of the memory shown in FIG. 3, and FIG. 4) is a diagram showing a potential of a bit line of the memory shown in FIG.

FIG. 6 is a circuit diagram of another nonvolatile semiconductor memory device according to the first aspect of the present invention.

FIG. 7 is a circuit diagram of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIGS. 8A and 8B are a waveform diagram input to the level shifter and a diagram showing the waveform, respectively.

FIGS. 9A and 9B are an equivalent circuit diagram showing a main part of the memory shown in FIG. 7 and a waveform diagram showing voltages applied thereto, respectively.

FIG. 10 is a circuit diagram of another nonvolatile semiconductor memory device according to the second aspect of the present invention.

11A and 11B are waveform diagrams of an input pulse applied to a level shifter, and FIG. 11C is a waveform diagram of an output pulse thereof.

FIGS. 12 (a), (b), and (c) show each of FIGS.
FIG. 3 is a waveform diagram showing a floating gate voltage, a bit line voltage, and a control gate voltage of the memory device shown in FIG.

FIG. 13A is a circuit diagram of still another nonvolatile semiconductor memory device according to the second aspect of the present invention, and FIGS. 13B and 13C respectively show a main part of the memory shown in FIG. FIG. 3 is an equivalent circuit diagram and a waveform diagram showing a voltage applied thereto.

FIG. 14A is a circuit diagram of still another nonvolatile semiconductor memory device according to the second aspect of the present invention, and FIGS. 14B and 14C respectively show a main part of the memory shown in FIG. FIG. 3 is an equivalent circuit diagram and a waveform diagram showing a voltage applied thereto.

FIGS. 15 (a), (b), and (c) each show FIG.
FIG. 4 is a waveform diagram showing a floating gate voltage, a bit line, and a control gate voltage of the memory device shown in FIG.

FIG. 16 is a sectional view showing another example of the current supply means.

FIG. 17A is a circuit diagram of an embodiment of a nonvolatile semiconductor memory device according to the third aspect of the present invention, and FIG.
FIG. 4 is a waveform diagram of a pulse applied to a control gate during a write operation.

FIG. 18 is a circuit diagram of another embodiment of the nonvolatile semiconductor memory device according to the third aspect of the present invention.

FIGS. 19 (a), (b), and (c) respectively show FIGS.
FIG. 9 is a waveform diagram showing a floating gate voltage, a bit line voltage, and a control gate voltage of the memory device shown in FIG.

FIG. 20 is a circuit diagram of still another embodiment of the nonvolatile semiconductor memory device according to the third aspect of the present invention.

21A is an equivalent circuit diagram of the embodiment of FIG. 20,
(B), (c) is a waveform diagram showing the operation timing of the switch.

FIG. 22 (a) is another equivalent circuit diagram of the embodiment of FIG. 20,
(B) is a waveform diagram showing the operation timing of the switch,
(C) is a waveform diagram of the composite pulse.

FIG. 23 (a) is a circuit diagram of still another embodiment of the nonvolatile semiconductor memory device according to the third aspect of the present invention, and (b).
FIG. 9 is a diagram for explaining an erase operation.

FIG. 24 is a circuit diagram of still another embodiment of the nonvolatile semiconductor memory device according to the fourth aspect of the present invention.

FIG. 25 is a circuit diagram of another nonvolatile semiconductor memory device according to the fourth aspect of the present invention.

FIG. 26 is a circuit diagram of still another nonvolatile semiconductor memory device according to the fourth aspect of the present invention.

FIG. 27 is a circuit diagram of an embodiment in which the minute current source is a charge pump circuit.

FIG. 28 is a circuit diagram of another example of the charge pump.

29 is a diagram showing operation waveforms based on the charge pump shown in FIG.

FIG. 30 is a circuit diagram showing an embodiment in which the minute current source comprises a switched capacitor.

FIG. 31 is an operation waveform diagram based on the switched capacitor circuit shown in FIG. 30;

FIG. 32 is a circuit diagram of another example of the switched capacitor circuit.

FIG. 33 is an operation waveform diagram based on the switched capacitor shown in FIG. 32;

FIG. 34 is a circuit diagram of another embodiment of the nonvolatile semiconductor memory device according to the fourth aspect of the present invention.

FIG. 35 is a circuit diagram of another embodiment of the nonvolatile semiconductor memory device according to the fourth aspect of the present invention.

FIG. 36 is a circuit diagram of another embodiment of the nonvolatile semiconductor memory device according to the fourth aspect of the present invention.

FIG. 37 is a circuit diagram of another embodiment of the nonvolatile semiconductor memory device according to the fourth aspect of the present invention.

FIGS. 38A and 38B are diagrams each showing a distribution of threshold voltages of a conventional flash EEPROM, and FIG. 38C is a diagram showing distributions of threshold voltages of a conventional NAND EEPROM;
(D) is a diagram showing the distribution of the threshold voltage of the UVEPROM.

FIGS. 39A and 39B are circuit diagrams showing a conventional method of erasing a nonvolatile semiconductor memory.

FIGS. 40A and 40B are an equivalent circuit diagram of a nonvolatile semiconductor memory and waveform diagrams for explaining the operation thereof.

41 (a) is a circuit diagram showing an example of a pulse generation circuit, and (b) and (c) are waveform diagrams for explaining the operation thereof.

FIG. 42 is a waveform chart for explaining the operation of the nonvolatile semiconductor memory.

43 (a) to (c) are waveform diagrams for explaining a problem to be solved by the present invention.

FIG. 44 is a diagram showing the effect of adjusting the threshold according to the present invention.

FIG. 45 is a diagram illustrating an effect of adjusting a threshold according to the present invention.

FIG. 46 is a block diagram of a basic structure of a memory to which the “AC pulse method” is applied.

Claims (22)

[Claims] 1. A non-volatile semiconductor memory device, comprising: a plurality of word lines; a plurality of bit lines intersecting the word; a bit line connected to a source line via a selection transistor; And a source, a drain, a floating gate, and a control gate, each having a control gate, a drain, and a source connected to each word line, bit line, and source line, respectively. Means for applying a charge to a source or a drain of a selected memory cell to set it in a floating state; a pulse signal fluctuating between a positive peak potential and a negative peak potential at a control gate of the selected memory cell. , And means for causing the threshold to converge. 2. The non-volatile semiconductor memory device according to claim 1, further comprising a minute current supply unit for supplying a current for compensating a leakage current of the bit line. 3. The nonvolatile semiconductor memory device according to claim 1, further comprising a plurality of main bit lines electrically connected to each of said bit lines via a selection transistor. 4. A first switch for applying a potential not lower than a source potential to a source or a drain of each memory cell, and a second switch for applying a potential not higher than a drain potential to a source or a drain of each memory cell. 2. The non-volatile semiconductor memory device according to claim 1, further comprising: switch means. 5. The nonvolatile semiconductor memory device according to claim 4, wherein a bit line is set to a potential higher than a source potential by said first switch means before applying a signal to the control gate. 6. The method according to claim 1, wherein the bit line is set to a potential higher than a source potential by the first switch before applying a signal to the control gate, and the signal is applied to the control gate. 5. The nonvolatile semiconductor memory device according to claim 4, wherein said bit line is set to a potential lower than a drain voltage by a second switch. 7. After the floating gate of the memory cell is charged to a negative potential by hot electrons from the channel of the memory cell, the charge stored in the floating gate from the floating gate to the source, drain or substrate is subjected to tunnel current. 5. The non-volatile semiconductor memory device according to claim 4, wherein the device is escaped as a non-volatile memory. 8. The floating gate of the memory cell is charged to a negative potential by a tunnel current flowing from the source, the drain or the substrate, and the electric charge accumulated in the floating gate is separated from the floating gate to the source, the drain or the substrate. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said non-volatile semiconductor memory device escapes as a tunnel current. 9. The nonvolatile semiconductor memory device according to claim 2, wherein said microcurrent supply means is connected to at least one bit line directly or via a switch. 10. The nonvolatile semiconductor memory device according to claim 9, wherein said switch is a switched capacitor and includes at least one MOS diode. 11. A non-volatile semiconductor memory device, comprising: a plurality of word lines; a plurality of bit lines intersecting the word lines; a plurality of bit lines intersecting the word lines; A plurality of memory cells having a floating gate and a control gate, the control gate, the drain and the source being respectively connected to each word line, bit line and source line. Means for charging and floating after a certain time, and applying a signal consisting of a pulse having a positive peak value and a negative peak value potential to the control gate of the selected memory cell via the word line to lower the threshold voltage. A non-volatile semiconductor memory device comprising: means for converging to a predetermined voltage. 12. The nonvolatile semiconductor memory device according to claim 11, further comprising means for supplying a leakage current of said bit line. 13. The nonvolatile semiconductor memory device according to claim 11, further comprising means for supplying a small current to a source or a drain of each of said memory cells. 14. A semiconductor device comprising a plurality of main bit lines,
12. The nonvolatile semiconductor memory device according to claim 11, wherein each main bit line is electrically connected to each of said bit lines via a selected transistor. 15. A first time constant based on a capacitance component of the bit line and an equivalent resistance value due to a current from the current supply unit is a second time constant based on a capacitance component of the bit line and an equivalent resistance value due to the leakage current. 12. The nonvolatile semiconductor memory device according to claim 11, wherein the first time constant is smaller than a time constant of the signal and the first time constant is longer than substantially half of a period of the signal. 16. The nonvolatile semiconductor memory device according to claim 11, wherein said current supply means comprises a resistor connected to a voltage source or a resistor connected in series to a switch. 17. The nonvolatile semiconductor memory device according to claim 11, wherein said current supply means comprises a reverse-biased diode connected to a voltage source or a reverse-biased diode connected in series to a switch means. 18. The nonvolatile semiconductor memory device according to claim 11, wherein said current supply means comprises a gated diode connected to a voltage source or a gated diode connected in series to a switch. 19. The nonvolatile semiconductor memory device according to claim 11, wherein said current supply means is connected between main bit lines or bit lines. 20. The nonvolatile semiconductor memory device according to claim 11, wherein the signal includes a plurality of positive peak value potentials. 21. The nonvolatile semiconductor memory device according to claim 11, wherein the signal includes a plurality of negative peak value potentials. 22. The nonvolatile semiconductor memory device according to claim 11, wherein said signal includes a plurality of positive peak value potentials.