JP2000124429A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce consumption power by setting a well potential during erasing verify at the same potential as a well potential during data erasing. SOLUTION: Erasing verify is carried out by selecting a word line one by one and selecting a memory cell one by one in a memory cell row connected to a selective word line. A word line WL0 is selected by a row selective circuit 2 and a potential 3V is applied to the selective word line WL0. Bit lines BL0 and BL1 connected to a memory cell M00 are selected by a bit line control circuit 3, a potential 1 V is applied to the selective bit line BL0, a potential 0 V is applied to the selective bit line LB1, and a potential -8 V which is the same potential as that during erasing is applied to a well. As a result, it is possible to keep a well potential always at a fixed potential without any variation and power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having an erase verify function.

[0002]

2. Description of the Related Art In a conventional non-volatile semiconductor memory device, for example, IEDM Tech. Dig. 95-26
7, as shown in FIG. 2, the word line WL and the bit line B
A method is shown in which the potentials of the L and the wells WELL are set and write, erase, and read / verify (write verify and erase verify) are performed.

That is, as shown in FIG. 2 and FIG. 3, writing is performed on the word line WL with the N- side (source) of the bit line BL floating (FLOAT) and the well WELL set at 0V. 8V, N + of bit line BL
This is performed by applying +4 V to the side (drain), extracting the electrons accumulated in the floating gate FG to the drain by the potential difference, and lowering the threshold value of the memory cell.

In erasing data in a memory cell, that is, in raising the threshold value of the memory cell, the operation shown in FIG.
4 and FIG. 4, the potential of the well WELL (−8
V), the source potential (−8 V), and the drain potential (−8 V).
V) and the potential difference (16 V) between the potential of the word line WL (8 V) and injection of electrons into the floating gate FG.

Further, in the read and verify operations, as shown in FIGS. 2 and 5, the potential (0 V) of the well WELL, the drain potential (1 V), and the source potential (0 V) are set.
V) and the word line potential (3 V) to detect whether or not a channel is formed (whether or not a current flows). In the erase verify operation, if the threshold value of the memory cell is not sufficiently high, a channel is formed and a current flows, so that it is determined that the erase is insufficient, and the erase operation is further performed, as shown in FIG. This is repeated until erasure is completed (no detection current is detected for all memory cells).

FIG. 7 shows a timing waveform of each of the above-mentioned signals at the time of transition from the erase operation to the erase verify operation. Here, the memory cell array is (n + 1) × (m +
1) Consider a case where the memory cell is composed of a matrix of memory cells.

At the time of erasing operation, all main bit lines MB
-8 V for L0 to MBLm (connected to bit lines BL0 to BLm via switching transistors), 8 V for all word lines WL0 to WLn, and a well on which a memory cell array is built To WELL,
-8 V is applied.

Subsequently, when the operation shifts to the erase verify operation, first, all the main bit lines MBL0 to MBL
m, the potentials of the word lines WL0 to WLn, and the well WELL are set to 0 V, so that no memory cells are selected. Then, the memory cells constituting the memory cell array are sequentially verified one by one. Go. That is, in a state where the well potential of the memory cell is set to 0 V, 3 V is applied to the first word line WL0, and the main bit line MB
1V is applied in order from L0 to MBLm. When this operation is completed, 3 V is applied to the next word line WL1, and similarly, 1 V is applied sequentially from the main bit lines MBL0 to MBLm. This operation is repeated up to the last word line WLn to verify all the memory cells. In this process, if any of the memory cells is determined to be insufficiently erased, the operation returns to the erase operation as shown in FIG. 6, and the erase verify operation is performed again, and it is determined that all the memory cells have been erased. The operation cycle of erase / erase verify is repeated until the operation is completed.

In recent years, the progress of nonvolatile semiconductor memory devices has been remarkable, and power consumption has been reduced.
No. 443 discloses a method for reducing power consumed by repetition of a data write operation and a write verify operation. That is, when changing from the write operation to the write verify operation, the potential applied to the well in which the row decoder for driving the control gate (corresponding to the word line) is formed is prevented from being lowered, thereby accumulating data in the well. It is intended to reduce power consumption due to charging and discharging of the electric charge.

[0010]

By the way, in recent nonvolatile semiconductor memory devices, further reduction in power consumption is required due to the evolution of portable devices and the like. During the transition from the erase operation to the erase verify operation, the potential -8 V and 0 V are repeatedly supplied to the well in which the memory cell array is formed, so that the charge stored in the well is charged and discharged. There is a problem that power consumption increases. Also, in the method disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 6-112443, in which the power consumed by the row decoder unit is reduced, the ratio of the row decoder unit to the chip area is small. There was a problem that a reduction effect could not be obtained.

The present invention has been made in view of the above, and has been made for the purpose of providing a nonvolatile semiconductor memory device capable of further reducing power consumption.

[0012]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a memory cell array formed on a well formed in a semiconductor substrate. In a semiconductor memory device, the well potential at the time of erase verification is set to the same potential as the well potential at the time of data erase.

According to a second aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the memory cell array is an EEPROM.
Is a memory cell array.

According to the nonvolatile semiconductor memory device of the present invention, at the time of an erasing operation, the row selecting circuit for selecting a word line applies 8 V to all the word lines, and the column selecting circuit for selecting a bit line. Applies -8 V to all the bit lines, and the well potential supply circuit applies -8 V to the well in which the memory cell array is formed. Thus, an erasing operation is performed. At the time of the erase verify operation after the erase operation, the row selecting circuit for selecting the word line applies 3 V to the selected word line, and the column selecting circuit for selecting the bit line applies 1 V to the drain side of the selected memory cell column. , And 0 V is applied to the source side. At this time, the well potential supply circuit continuously applies −8 V applied at the time of the erase operation to the well in which the memory cell array is formed. Therefore, in the well where the memory cell array is formed,
Even if the erase operation and the subsequent erase verify operation are repeated, a constant potential (-8 V) is always applied and different potentials are not supplied alternately, so that power consumption is reduced. Can be achieved.

Further, the memory cell array is EEPRO
In the case of a memory cell array of M, when the number of times of writing and erasing increases, the threshold value at the time of erasing deviates from an expected value due to deterioration of the oxide film due to movement of electrons in the oxide film between the floating gate and the drain and the well. The likelihood increases, and as a result, the number of erase verify operations increases. By applying the present invention to such a nonvolatile semiconductor memory device, a greater effect of reducing power consumption can be obtained.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a main part of a flash memory (EEPROM) according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a plurality of memory cells M
A memory cell array in which 00 to Mnm are arranged in a matrix, 2 is a row selection circuit, 3 is a column selection circuit,
This is a bit line control circuit including a sense circuit and a rewrite circuit. The selection and potential control of the word lines WL0 to WLn are performed by the row selection circuit 2. Also, the bit lines BL0 to BL0
The selection / potential control of BLm is performed by connecting the main bit lines MBL0 to MBLm to the bit lines BL0 to BLm by turning on the switching transistors T00 to T0m by the memory cell array selection signal SG0 from the row selection circuit 2. Is performed by the bit line control circuit 3.
Although not shown in FIG. 1, a plurality of memory cell arrays are provided in the extending direction of the main bit line MBL.
A row selection circuit is provided. The signal SG0 from each row selection circuit is configured such that only the signal SG0 from any one row selection circuit is “H” and the others are “L”, whereby a plurality of signals SG0 in the main bit line extension direction are provided. Only one of the memory cell arrays is selected from the memory cell arrays, and only the bit lines BL of the selected memory cell array are
It is configured to be connected to the main bit line MBL.
The wells in which the memory cell arrays are formed are provided separately and independently for each memory cell array.

Next, the operation will be described.

FIG. 8 is a diagram showing potentials applied to various parts in the flash memory according to the present embodiment at the time of writing, erasing, and reading / verifying.

FIG. 9 shows a timing waveform of each signal at the time of transition from the erase operation to the erase verify operation. As shown in the figure, at the time of transition from the erase operation to the erase verify operation, the well potential does not change, and a constant potential (-8 V) is applied.
Is a feature of the present invention.

First, the erasing operation will be described.

At the time of erasing, all the word lines WL0 to WL0n are selected by the row selection circuit 2, and a potential of 8 V is applied to all the word lines. Further, all the bit lines BL0 to BLm are selected by the bit line control circuit 3, and a potential of -8 V is applied to all the bit lines.
Further, a potential of -8 V is applied to the well.

Thus, the word line WL, the bit line BL and the well WELL are connected to the floating gate of the memory cell.
Electrons are injected due to the potential difference between 8V − (− 8V) = 16V, and the threshold is raised, thereby performing erasure. This erasing operation is the same as the conventional one. Also, the writing operation is completely the same as the conventional one, and therefore the description is omitted.

Next, the erase verify operation will be described.

The erase verify is performed by sequentially selecting word lines and sequentially selecting one memory cell at a time from memory cell rows connected to the selected word line.

First, the row selection circuit 2 causes the word line WL
0 is selected, and a potential of 3 V is applied to the selected word line WL0. Further, the bit lines BL0 and BL1 connected to the memory cell M00 are selected by the bit line control circuit 3, and the selected bit line BL0 is supplied with the potential 1V, and the selected bit line BL1 is supplied with the potential 0V. Applied. Further, the same potential of −8 V as in the erase operation is continuously applied to the well. This control of the well potential is a feature of the present invention.

FIG. 10 shows the potential state of each part in the memory cell M00 at this time. Here, the word line WL
The potential difference between 0 and the well WELL, 3V − (− 8V) = 11V, is a potential difference that is insufficient (sufficiently low) for electron injection to the floating gate. Therefore, no electron is injected into the floating gate during this erase verify.

When the threshold value of the memory cell M00 is sufficiently high by the erasing operation, that is, when erasing is completely performed, a channel is formed in the well immediately below the floating gate of the memory cell M00. Since no current is formed, no current flows, and this is detected by the sense circuit unit in the bit line control circuit shown in FIG. 1, and it is determined that the memory cell M00 has been erased. On the other hand, when the threshold value of the memory cell M00 is not sufficiently high, that is, when erasing is insufficient, a channel is formed in the well immediately below the floating gate of the memory cell M00, and current flows. This current is detected by the sense circuit section in the bit line control circuit shown in FIG. 1, and it is determined that the memory cell M00 is insufficiently erased.

If it is determined that the erasure of the memory cell M00 is completed, the process proceeds to the verification of the next memory cell M01. That is, the bit line control circuit 3 selects the bit lines BL1 and BL2 connected to the memory cell M01 while keeping the word line potential unchanged, and the selected bit line BL1
, And a potential 0 V is applied to the selected bit line BL2. Further, the same potential of −8 V as in the erase operation is continuously applied to the well.

When the threshold value of the memory cell M01 is sufficiently high by the erasing operation, that is, when erasing is completely performed, a channel is formed in the well immediately below the floating gate of the memory cell M01. Since it is not formed, no current flows, and this is detected by the sense circuit portion in the bit line control circuit shown in FIG. 1, and it is determined that the memory cell M01 has been erased. On the other hand, if the threshold value of the memory cell M01 is not sufficiently high, that is, if erasure is insufficient, a channel is formed in the well immediately below the floating gate of the memory cell M01, and current flows. This current is detected by the sense circuit portion in the bit line control circuit shown in FIG. 1, and it is determined that the memory cell M01 is insufficiently erased.

In the same manner, the process proceeds to the verification of the memory cell M0m. If the erase of the memory cell M0m is also determined to be completed, the process proceeds to the verification of the memory cells M10 to M1m connected to the next word line WL1.

That is, the word line WL1 is selected by the row selection circuit 2, and the selected word line WL1 is supplied with a potential of 3V.
Is applied. Further, the bit lines BL0 and BL1 connected to the memory cell M10 are selected by the bit line control circuit 3, and the selected bit line BL0 is supplied with a potential of 1 V and the selected bit line BL1 is supplied with a potential of 0 V, respectively. Applied. Further, the same potential -8 as during erasing is applied to the well.
V is subsequently applied.

In the same manner, verification is performed up to the last memory cell Mnm of the last word line WLn.

If an insufficiently erased memory cell is detected during the execution of the verify operation, the erase operation is executed again. Then, after the completion of the erasing operation, memory cells subsequent to the memory cell that was immediately determined to be insufficiently erased are
Subsequently, an erase verify operation is performed. Until all memory cells have been erased, the erase / erase verify operation is repeatedly executed.

As is apparent from the above description, in the present embodiment, even when a memory cell with insufficient erasure is detected and the erase operation and the erase verify operation are repeatedly performed, the well potential is maintained. , Always constant potential (-8V)
And there is no fluctuation at all. Therefore, power consumption can be reduced. This effect increases as the number of times the erase operation and the erase verify operation are repeatedly executed increases.

[0037]

As described above in detail, the non-volatile semiconductor memory device of the present invention has a structure in which a memory cell array is formed on a well formed in a semiconductor substrate. The method is characterized in that the well potential at the time of verification is set to the same potential as the well potential at the time of data erasing.
The memory cell array is a memory cell array of an EEPROM. According to the nonvolatile semiconductor memory device of the present invention, the well potential is kept constant when the erase operation is shifted to the erase verify operation. Therefore, power consumption can be reduced. The present invention particularly achieves a reduction in power consumption in a memory cell array portion occupying 60% to 70% of a memory chip in terms of area, and the effect of reducing power consumption is very large. is there. Therefore, by applying the present invention, it is possible to achieve a remarkable reduction in power consumption in a product mounted with a nonvolatile semiconductor memory device, and the effect is remarkable.

[Brief description of the drawings]

FIG. 1 is a main part circuit configuration diagram of a flash memory according to an embodiment of the present invention.

FIG. 2 is a diagram showing potentials applied to respective parts at the time of writing, erasing, and reading / verifying in a conventional nonvolatile semiconductor memory device.

FIG. 3 is a diagram showing a state of a memory cell during a write operation.

FIG. 4 is a diagram showing a state of a memory cell during an erase operation.

FIG. 5 is a diagram showing a state of a memory cell during an erase verify operation in a conventional nonvolatile semiconductor memory device.

FIG. 6 is a diagram showing an operation sequence of erase / erase verify.

FIG. 7 is a diagram showing timing waveforms of respective signals at the time of transition from an erase operation to an erase verify operation in a conventional nonvolatile semiconductor memory device.

FIG. 8 is a diagram showing potentials applied to respective parts at the time of writing, erasing, and reading / verifying in a flash memory according to an embodiment of the present invention.

FIG. 9 is a diagram showing timing waveforms of respective signals at the time of transition from an erase operation to an erase verify operation in a flash memory according to an embodiment of the present invention.

FIG. 10 is a diagram showing a state of a memory cell during an erase verify operation in a flash memory according to an embodiment of the present invention.

[Explanation of symbols]

 1 memory cell array 2 row selection circuit 3 bit line control circuit WELL well

Claims (2)

[Claims] In a nonvolatile semiconductor memory device in which a memory cell array is formed on a well formed on a semiconductor substrate, a well potential at the time of erase verification is set to the same potential as a well potential at the time of data erase. A nonvolatile semiconductor memory device characterized by comprising: 2. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cell array is an EEPROM memory cell array.