JP2003091993A - Data storage device, and nonvolatile semiconductor memory device to be used therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To arbitrarily set a data unit exchanged between a nonvolatile memory and this device for data capacity of a cache memory for improving a hit rate. SOLUTION: The data storage device has a nonvolatile memory device (cache memory 1) and a nonvolatile semiconductor memory device (MONOS memory 2), data is stored linking with both memories in accordance with inputted data. The MONOS memory 2 has a memory cell array in which a plurality of memory cells storing data by accumulating electric charges in an electric charge trap in a plurality of ferroelectric films laminated on the semiconductor are arranged in a matrix state and memory cells are connected by a plurality of common lines of a row direction and a column direction. In this device, common lines of this column direction are separated for each cell column so that the number of bits of data unit exchanged between memory devices can be set arbitrarily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a volatile memory device called a so-called cache memory and, for example, a MONO.
A data storage device that achieves high memory operation performance (rewrite speed, rewritable number) even if it is non-volatile by operating in cooperation with a non-volatile memory device that stores data using charge traps such as S type. , A non-volatile semiconductor memory device that can be used for the data storage device.

[0002]

2. Description of the Related Art There are roughly two types of conventional non-volatile RAM. One of them is EE as a non-volatile memory in a cell of a volatile memory such as SRAM or DRAM.
It is a combination of PROMs.

FIG. 11 shows a nonvolatile RA based on SRAM.
It is an equivalent circuit diagram of M cell. This nonvolatile RAM cell has a normal 6-transistor type SRAM cell including word NMOS transistors N ₁ and N ₂ , drive NMOS transistors N ₃ and N ₄ , and load PMOS transistors P ₁ and P ₂ . Storage node N of SRAM cell
An EEPROM cell is connected to D ₁ and ND ₂ .
EEPROM cell, the drain of the memory transistor T ₂ is connected to the storage node ND ₂ of the SRAM cell,
Its source is connected to the reference potential line via the capacitor C ₂ . The capacitor CC ₂ is connected between the floating gate FG and the control gate CG of the memory transistor T ₂ . Floating gate FG
Is connected to the supply line of the store voltage V _ST via the capacitor C _E and the control gate CG via the capacitor CC ₃ . Further, the floating gate FG is connected to the control gate C through the capacitor C _P.
G is connected to the reference potential line via the NMOS transistor T ₁ . The gate of the NMOS transistor T ₁ is connected to the storage node ND ₁ of the SRAM cell and is also connected to the reference potential line via the capacitor C ₁ .

Here, the capacitor CC₃ , CC₂ Is
Capacitor C_E , C_P Designed to be much larger. I
The level of the storage node of the SRAM cell is ND₁ Is L
ND in (low)₂ Is H (high). This RA
Store operation to store M data in EEPROM
Register T₁Is off when the store voltage V_STIs applied
Then, the capacitor CC₃ , CC₂ , C _E Synthetic capacity and key
Capacitor C_P Ratio to capacity (combined capacity >> C_P ) Flow
Memory with boosting gate potential and on state
Transistor T₂ Electrons floating from the channel
It is injected into the gate FG and its threshold voltage Vth is H level.
Become a bell. On the contrary, the storage node ND of the SRAM cell₁ But
Storage node ND at H level₂Is at the L level
The transistor T₁ Is turned on, the store voltage V
_STWhen applied, the floating gate potential is almost boosted.
No electron injection occurs. For this reason,
The threshold voltage Vth of the transistor is maintained at the L level.

Thus, the storage node N of the SRAM cell is
The potential of D ₂ is held in a magnitude relationship with the threshold voltage Vth of the memory transistor T ₂ . Therefore, even if the power supply to the DRAM cell is cut off thereafter, DR
The stored data of the AM cell is held in the EEPROM.

When the power is turned on again or at a desired timing, E
During the recall operation for transferring the EPROM data to the SRAM cell, the potential V _DDA of the power supply node of the SRAM cell is gradually raised from the low potential to the power supply voltage V _DD . EEPRO
The capacitor C _{2 in} M is preset to be sufficiently larger than the capacitor C ₁ . Therefore, the storage nodes ND ₁ , N
The magnitude relationship of the load capacitance of D ₂ is reversed according to ON / OFF of the memory transistor T ₂ . That is, the threshold voltage Vth is low at the L level and the memory transistor T ₂ is low.
There When turned on, the storage node ND ₂ in the capacitor C ₂
Storage node ND ₂ is connected to L
The level and the storage node ND ₁ become H level. On the contrary, when the threshold voltage Vth is high at H level and the memory transistor T ₂ is turned off, the load capacitance becomes high on the storage node ND ₁ side, and as a result, the storage node ND ₁ is at L level,
The storage node ND ₂ becomes H level. EEP like this
The data stored in the ROM (the magnitude of the threshold voltage Vth) is
As it is, the potential of the storage node ND ₂ is determined. As a result, the recall operation causes the SRAM at the time of the store operation.
This means that the stored data is recalled from the EEPROM and reproduced on the storage nodes ND ₁ and ND ₂ .

FIG. 12 shows a DRAM-based non-volatile RA
It is an equivalent circuit diagram of M cell. This non-volatile RAM cell
Are three NMOS transistors T₁ , T₂ , T₃ When,
It has one memory transistor MT. Bit supplementary line
BL_ and power supply voltage V_CCTransistor T between the supply line of
₁ , Memory transistor MT, transistor T ₃ Are in series
It is connected. Control of memory transistor MT
A transistor T between the rugate CG and the bit line BL.
₂ Are connected. Transistor T₁, T₂ Is the word
Controlled by line WL, transistor T₃ Is the recall line
Controlled by RL. Drain of memory transistor MT
The impurity diffusion layer has a large area and its drain
Control gate CG through the dielectric film on the pure substance diffusion layer
Are overlapping. This allows the MOS type of the DRAM cell
Capacitor C₁ Are formed.

This non-volatile RAM cell is usually a 2-transistor (T ₁ , T ₂ ) and 1-capacitor (C ₁ ) type D cell.
Functions as a RAM cell. The store operation of accumulating the electric charge (stored data) stored in the capacitor C ₁ in the floating gate FG of the memory transistor is performed again after the stored data is once read out of the memory cell. Specifically, first, the word line WL is activated, and a potential change slightly appearing on the bit line pair at this time is read out as stored data by a sense amplifier (not shown) connected to the bit line pair BL, BL_. After latching this stored data, one of the bit line pairs is boosted to a high voltage in response to the "1" or "0", and electrons are injected or extracted into the floating gate FG of the memory transistor MT.
For example, when injecting electrons into the floating gate FG of the memory transistor MT, the bit line BL side is set to a high voltage and the auxiliary bit line BL_ is set to the reference voltage 0V. When the word line WL and the recall line RL are activated in this state, the memory transistor is turned on, electrons are injected from the channel to the floating gate FG, and the threshold voltage Vth of the memory transistor MT rises. On the contrary, when the electrons are extracted, the word line is activated with the complementary bit line BL_ set to a high voltage and the bit line BL set to the reference voltage 0V. At this time, the electrons in the floating gate FG are extracted to the drain impurity diffusion layer from the charge extraction portion where the tunnel film provided on the drain side of the memory transistor MT is thin. Although the storage data of the capacitor C ₁ leaks and disappears with time, the same storage data is converted into the threshold voltage difference of the memory transistor MT and stored.

The recall operation is also performed for each cell via the sense amplifier. Specifically, the bit line BL is replaced with the complementary bit line B.
Precharge to a potential higher than L_, and complement bit line BL_
Was a floating state to turn on the transistor T ₁ through T ₃ activates the word line WL and the recall line RL. At this time, ON / OFF of the memory transistor MT is determined according to the electron accumulation state of the floating gate FG. When the memory transistor MT is turned on, the potential of the complementary bit line BL_ rises, and when the memory transistor MT is turned off, the potential of the complementary bit line BL_ does not rise. Data is read by amplifying the potential change of the complementary bit line BL_ by a sense amplifier. The data based on, by performing one of a write operation to a non-charged or charged capacitor C _1, the original stored data is reproduced as a charge storage state of the capacitor C _1.

However, in these SRAM-based or DRAM-based non-volatile RAMs, the number of transistors forming a cell is large and the cell area is large.
It has hardly been put to practical use.

FeRAM is another typical form of non-volatile RAM. However, FeRAM is
The memory cell size is 10 times larger than that of DRAM, and the number of times of reading is limited. For example, FeRAM has a limit of 10 ¹⁰ read times, and SRAM, DRAM are used for applications requiring at least 10 ¹⁵ read times.
Is not suitable for replacement. Therefore, the FeRAM has been limited to a special application such as a memory card, which requires less reading times than a normal RAM.

On the other hand, as described in, for example, Japanese Unexamined Patent Publication No. 5-216775, a flash EEPROM can be used as the main memory of a so-called cache memory system to achieve substantially the same function.

A general configuration of such a cache memory system is shown in FIG. The cache memory is generally composed of a tag memory, a data memory and a comparator. In addition to address bits, the tag memory stores change bits, effective bits, replacement algorithm bits, and the like as necessary. In the data memory, a part of the data in the flash memory, which corresponds to the address bit in the tag memory one to one, is copied and stored. The cache memory is connected to the CPU and the flash memory via a bus line, and addresses and data are communicated with each other. When the address of the flash memory is given to the cache memory, it is compared with the contents of the tag memory by the comparator. If there is a matching address, it is said to be a "hit". In this case, the data corresponding to the hit address is fetched from the data memory and used. If there is no matching address as a result of comparator comparison,
Say "I made a mistake". If a miss occurs, the flash memory is accessed and the obtained data is used.

In the cache memory system, when the data memory is composed of SRAM, for example, power supply is necessary. When the system power is turned off and the power supply to the SRAM is cut off, a control circuit (not shown) receives power supply from the battery and performs a store operation for saving the stored contents in the cache memory to the spare flash memory. To do. Then, when the power is restored, a recall operation is performed to recall the data saved in the spare flash memory back into the cache memory.

Such a cache memory system requires a battery required when the power is turned off, but the entire system can be made non-volatile. When this cache memory system is applied to a computer, the access data has locality, that is, data of the same or adjacent addresses is used repeatedly one after another. Therefore, by storing this frequently used data in the cache memory and changing the data to be stored in the cache memory according to the frequency of use of the data, the rewriting characteristics of the entire system can be improved as compared with the data storage device of the flash memory alone. Can be improved.

[0016]

The minimum unit of data exchanged between the cache memory and the flash memory is called a block (or line). In the cache memory system for improving the rewriting characteristics as described above, the rewriting unit of the flash memory is a block.

By the way, the most common flash memory at present uses an FG type memory transistor as a memory element, and the rewriting unit thereof is, for example, a minimum of 512 bytes.
And a relatively large unit. This is to shorten the rewriting time (= erasing time + writing time) of the flash memory as much as possible.

Generally, the larger the block unit, the higher the hit rate. That is, if some data is referenced,
It is explained by the spatial locality that data near it is likely to be referenced soon. But,
If the size of the block relative to the cache memory capacity is made very large, the hit rate may be lowered on the contrary. This is because the number of blocks that can be held in the cache memory decreases, and thus competition between blocks increases. For example, if data belonging to another block is accessed only once while accessing in a certain block and the data in the original block is subsequently accessed, the number of blocks that can be accommodated in the cache memory is small, When accessing the data that belongs to the block, the original block contents are rewritten,
After that, you will not be able to access it. In such a case, it is necessary to recall the original block contents from the flash memory again, the hit rate becomes low, and the block contents are frequently exchanged between the flash memory and the cache memory, which lowers the efficiency.

From the above reason, for example, several tens of kBytes
It is estimated that the optimum block size that maximizes the hit rate for a cache memory having a capacity of several tens of bytes is several tens of bytes. The block size (minimum 512 Bytes) of the most common flash memory described above is generally too large for the practical capacity size of the cache memory, which is a factor that hinders the improvement of the hit rate. It was Further, it is preferable that the block size is large when the flash memory is used independently. However, in a system that is used in cooperation with the cache memory, the block size being larger than necessary may increase the rewriting time of the flash memory itself. is there.

A first object of the present invention is to arbitrarily set a data unit exchanged with a non-volatile memory device with respect to a data capacity of a volatile memory device such as a cache memory in order to improve a hit rate. It is to provide a data storage device. A second object of the present invention is to provide a non-volatile semiconductor memory device having a configuration easy to use in a system used in cooperation with another memory device such as the data storage device.

[0021]

In order to achieve the above first object, a data storage device according to a first aspect of the present invention has a volatile memory device and a non-volatile semiconductor memory device, and A data storage device that stores data by linking both memory devices according to the stored data, wherein the nonvolatile semiconductor memory device stores charges in charge traps in a plurality of dielectric films stacked on a semiconductor. Then, a plurality of memory cells for storing data are arranged in a matrix, and a memory cell array in which the memory cells are connected by a plurality of common lines in the row direction and the column direction is provided, and the common line in the column direction is
It is separated for each cell column so that the number of bits of a data unit exchanged between memory devices can be arbitrarily set. The volatile memory device preferably includes a data memory for storing data, an address memory for storing the address of the data memory area, and a comparator for comparing the input address with the address in the address memory.

The memory cell of the nonvolatile semiconductor memory device is preferably composed of a so-called MONOS type memory transistor. It also has a non-volatile memory control circuit for writing, erasing or reading. It is desirable that the nonvolatile memory control circuit perform writing by so-called hot electron injection, erasing by hot hole injection due to so-called band-to-band tunnel current, and reading by so-called reverse read method.

Further, the data storage device preferably has a control circuit for controlling between memories. The control circuit, for example, writes the input data to the data memory of the volatile memory device corresponding to the address when there is a matching address in the comparator, and writes the input data in the data memory when there is no matching address in the comparator. Control is performed such that a part of the data is expelled, the input data is written to a free area of the data memory, and the data expelled from the data memory is written to the nonvolatile semiconductor memory device. Further, for example, the control circuit reads the data corresponding to the address from the data memory of the volatile memory device when there is a matching address in the comparator, and the input address when there is no matching address in the comparator. The control for reading the data corresponding to is read from the nonvolatile semiconductor memory device.

In the thus configured data storage device according to the first aspect of the present invention, the unit of writing, erasing or reading of the non-volatile memory device can be set to an arbitrary bit number of 1 bit or more, so that it is volatile. It is possible to set the data size (block size) that maximizes the hit rate in the memory device. Therefore, the access success efficiency of the volatile memory device is high, and the number of times of data communication between the volatile memory device and the non-volatile memory device is reduced. Therefore, the operation time of the entire data storage device for exchanging necessary data with the outside is short. In addition, it can be made non-volatile as a whole only by providing an internal auxiliary power supply if necessary, and the data rewriting speed mainly depends on the characteristics of the volatile memory device. Has become.

In order to achieve the above second object, a nonvolatile semiconductor memory device according to a second aspect of the present invention has a memory cell array including a plurality of memory cells arranged in rows and columns, A cell is laminated between a semiconductor in which a channel is formed and a gate electrode, and has a plurality of dielectric films including charge traps therein, and charges are injected into the charge traps to write or erase data, When reading the stored data, a plurality of common lines in the row and column directions to which necessary voltages are applied respectively connect the memory cells in the memory cell array, and the common lines in the column direction are written and erased at once. Alternatively, it is separated for each cell column so that the number of bits of the data unit to be read can be set arbitrarily.

This non-volatile semiconductor memory device has a structure suitable as, for example, the non-volatile memory device of the data storage device according to the first aspect.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment The first embodiment relates to the nonvolatile semiconductor memory device of the present invention. FIG. 1 is an equivalent circuit diagram of four cells showing a basic configuration of a memory cell array of a nonvolatile semiconductor memory device according to an embodiment of the present invention. 2A to 2C are diagrams showing bias conditions at the time of writing, erasing and reading. FIGS. 3A and 3B are a circuit diagram and a cross-sectional view of a memory transistor showing bias conditions and operations during writing. In addition, FIGS. 4A and 4B are a circuit diagram and a cross-sectional view of a memory transistor showing a bias condition and an operation at the time of erasing.

As shown in FIG. 1, in this memory cell array, each memory cell is composed of one MONOS type memory transistor, and a large number of MONOS type memory transistors are arranged in a matrix. Source lines and bit lines which are shared by the memory cell columns and which are long in the column direction are alternately arranged. Specifically, a source line SL1 for connecting the sources of the memory cells in the first column to each other, a bit line BL1 for connecting the drains of the memory cells in the first column to each other, and a source of the memory cells in the second column to each other. Source line SL2, bit line BL connecting the drains of the memory cells in the second column to each other
2, ... Are arranged in this order in the row direction. As shown in FIGS. 3B and 4B, each bit line and each source line is an N-type impurity region (source / drain region) formed in a substrate SUB made of, for example, a P-type silicon wafer. ) S / D.

In addition, a long word line shared by the memory cell rows is arranged in the row direction. Specifically, the word line WL1
Connect the gates of the memory cells in the first row to each other, and the word line WL2 interconnects the gates of the memory cells in the second row. As shown in FIGS. 3B and 4B, each word line is composed of a gate electrode GE made of, for example, doped polycrystalline silicon.

In the MONOS type memory cell, the gate dielectric film GD formed of three dielectric films is interposed between the gate electrode GE and the substrate SUB. The gate dielectric film GD is
A bottom film BTM made of, for example, silicon oxide and silicon oxynitride, and a dielectric having a higher charge trap density than the bottom film, such as silicon nitride or silicon oxynitride, in order from the lower layer, and a charge storage film mainly serving to store charges. CHS,
For example, it is composed of a top film TOP made of silicon oxide or the like. Here, the bottom film BTM is formed of the accumulated charge and the substrate SUB.
And the top film TOP function as a potential barrier layer between the accumulated charges and the gate electrode GE.

At the time of writing, a positive voltage, for example, 5 V is applied to the bit line BL1 connected to the writing target cell surrounded by the ellipse in FIG. 2A, and the bit lines BL2, ... Source lines SL1, SL
A reference voltage of 0 V is applied to 2, ... In addition, a positive voltage, eg, 9 V, is applied to the word line WL1 to which the cell to be written is connected.
V is applied, and word lines WL2 and
A reference voltage of 0 V is applied to.

Under this bias condition, as shown in FIG. 3B, the electrons supplied from the source to the channel CH are accelerated, some of them become hot electrons on the drain end side, and inside the gate dielectric film GD. Is injected into. As a result, the threshold voltage of the memory transistor rises. By switching the applied voltage between the source and drain, electrons can be injected into the other end in the channel direction,
In this case, 2 bits / cell is stored.

At the time of erasing, a positive voltage, for example, 5 V is applied to the bit line BL1 connected to the cell to be erased surrounded by the ellipse of FIG.
A reference voltage of 0 V is applied to 2, ...
1, SL2, ... Are opened and brought into a floating state. Also, the word line WL to which the cell to be erased is connected
1 is applied with a negative voltage, for example, -5V, and the reference voltage 0V is applied to the word lines WL2, ...

Under this bias condition, as shown in FIG. 4B, the source / drain region S / D to which a positive voltage is applied is applied.
The surface of the (bit line BL) is depleted and the depletion layer has a high voltage, so that a band-to-band tunnel current is generated. Holes h are generated due to the band-to-band tunnel current, and the electric field is accelerated. The holes h that have obtained high energy by the electric field acceleration are attracted to the gate voltage and injected into the charge traps in the charge storage layer CHS. As a result, the accumulated charges in the charge accumulation layer are canceled out, and the threshold voltage of the memory transistor is lowered.

In reading, reverse reading is performed in which the voltage applied between the source and the drain is opposite to that in writing. That is, when reading a cell surrounded by an ellipse in FIG. 2B, a reference voltage 0V is applied to the bit line BL1 on the side where the charges are accumulated, and a positive voltage, for example, 1V is applied to the source line SL1.
Is applied. The bit line BL2 of the column that is not read
, And the source lines SL2, ... Are held at the reference voltage 0V. In addition, the word line W to which the cell to be read is connected
A positive voltage, for example, 3.5V is applied to L1, and a reference voltage of 0V is applied to the word lines WL2, ... In other rows.

Under this bias condition, if electrons are accumulated and the threshold voltage is high, the memory transistor does not turn on. On the contrary, when electrons are not accumulated, or when holes are injected and electrons are canceled and the threshold voltage is low, the memory transistor is turned on. A sense amplifier (not shown) amplifies a change in the current between the bit line and the source line, which changes depending on whether the memory transistor is turned on or off, and outputs it as read data. In this reverse read, even if the number of stored electrons is several hundred, the current between the bit line and the source line effectively changes depending on the presence or absence of the stored electrons. Therefore, as compared with the case of the forward read, there is an advantage that the erasing time for injecting holes in an amount that cancels the accumulated electrons can be significantly shortened, and as a result, the rewriting time is shortened. In addition, when reading another bit of 2-bit storage in the same cell,
The voltage applied to the source and drain is reversed to the above to operate.

FIGS. 5A and 5B show binary threshold voltage Vth distributions of the memory transistor. MONOS
Type nonvolatile memory, the higher stored data “0” has a wide threshold voltage distribution, but the lower stored data “1”
The threshold voltage distribution of is converged in a narrow range. Normally, the stored data “0” is set to the written state and the stored data “1” is set to the erased state, but conversely, the stored data “1” may be set to the written state and the stored data “0” may be set to the erased state. The former is shown as method 1 in FIG. 5 (A), and the latter is shown as method 2 in FIG. 5 (B). Hereinafter, an example of calculating the rewriting time for each of method 1 and method 2 will be shown.

[Method 1] In method 1, as described above, the storage data "0" is in the write state and the storage data "1" is in the erase state. In erasing, the threshold voltage Vth easily converges, so the number of times of pulse application to the gate is set to twice. The erase pulse time Tpe is set to 10 μs, and the charging / discharging time Tce of the word line and the bit line is set to 1 μs at maximum when assuming that the data unit to be exchanged at one time is 8 bits. The time Tve is set to 0.1 μs. Under this assumption, the erase time Te is calculated by the following equation (1).

[Equation 1]

In writing, it is assumed that pulse application is performed four times. The write pulse time Tpw is set to 1 μs, and the charging / discharging time Tcw of the word line and the bit line is 1 μm at maximum when the data unit to be exchanged at one time is 8 bits.
Let s. In addition, the number of verifications is large when the voltage is converged to a high threshold voltage, and the total time Tvw is 1 μm.
Let s. Under this assumption, the write time Tw is calculated by the following equation (2).

[Equation 2]

From the above, the rewriting time in the method 1 is about 34 μs (= 22 μs + 12 μs).

[Method 2] In method 2, as described above, the storage data "1" is in the written state and the storage data "0" is in the erased state. Since it is difficult for the threshold voltage distribution to converge, erasing is performed after setting all the cells to a low threshold voltage in programming before erasing. The pulse is applied only once in the writing before the erasing, and the verify is not performed. The pulse time Tpp for writing before erasure is set to 10 μs, and the charging / discharging time Tcp of the word line and the bit line is set to 1 μs at the maximum, assuming that the data unit to be exchanged at one time is 8 bits.
Under this assumption, the pre-erase write time Tp is calculated by the following equation (3).

[Equation 3]

In erasing, the pulse is applied twice. The erase pulse time Tpe is set to 2 μs, and the charge / discharge time Tce of the word line and the bit line is set to 1 μs at maximum and the verify time Tve is set to 0.1 μs, assuming that the data unit to be exchanged at one time is 8 bits. Under this assumption, the erase time Te is calculated by the following equation (4).

[Equation 4]

In writing, pulse application is performed twice. The write pulse time Tpw is set to 10 μs, and the charging / discharging time Tcw of the word line and the bit line is 1 μs at maximum, assuming that the data unit to be exchanged at one time is 8 bits.
And the verify time Tvw is set to 1 μs. Under this assumption, the write time Tw is calculated by the following equation (5).

[Equation 5]

From the above, the rewriting time in Method 2 is about 41 μs (= 11 μs + 6.2 μs + 24 μs). In this way, the rewriting time is several tens of μs in both cases of method 1 and method 2, and there is not much difference.

Next, as a comparative example, an FG type memory cell generally used conventionally and its memory cell array will be described. 6A and 6B show a memory cell array in which a wiring serving as a source is shared between adjacent cells in the row direction and the column direction. Further, FIGS. 7A and 7B show bias conditions during writing and erasing.

In the memory cell array of FIG. 1 according to the present embodiment, the source line is shared for each column and separated in the row direction. On the other hand, in the memory cell array of FIG. 6A, the common source line SL is shared by every two memory cell rows. Further, in the VG type memory cell array shown in FIG. 6B, since the functions of the source and the drain are switched, all wirings in the column direction are called bit lines. Each bit line BL1, BL2, BL3, ... Is shared by two memory cell columns.

As is well known, the FG type memory cell has a gate structure in which a tunnel film, a floating gate, a dielectric film such as an ONO film, and a control gate are laminated on a semiconductor. At the time of writing, the reference voltage 0V is applied to the source, and the storage data “0” is applied to the drain.
5V or 0V is applied according to "1". Further, a positive voltage, for example, 10V is applied to the control gate. Only when 5 V is applied to the drain under this bias condition, electrons are injected into the floating gate by channel hot electron injection or FN tunneling of the entire surface of the channel, and the threshold voltage of the memory transistor rises.

At the time of erasing, a positive voltage is applied to one of the source and the drain and the other is opened. Further, a negative voltage, for example, -10V is applied to the control gate. Under this bias condition, holes are generated due to the band-band tunnel current on the side to which 5 V is applied. The generated holes are attracted by the gate voltage and injected into the floating gate, which lowers the threshold voltage of the memory transistor.

In the FG type memory cell of this comparative example, the writing time is several μs. In the memory cell array of FIG. 6A, writing can be performed by 1 bit for each cell belonging to the same row, and continuous writing of, for example, 8 bits can be performed. However, in the memory cell array of FIG. 6B, writing can be performed by 1 bit for each cell belonging to the same row, but arbitrary parallel writing of continuous multiple bits cannot be performed. This is because the potential of the bit line connected to a certain write cell regulates the source potential or the drain potential of another cell adjacent in the row direction.

Further, the erasing time of the FG type memory cell of the comparative example is long because it is necessary to inject a large number of holes in order to sufficiently change the potential of the floating gate FG, and is as long as several tens ms. Therefore, the erase for each bit is not used because the erase time is too long.

In the FG type nonvolatile memory of this comparative example,
Since the rewriting time was as long as several tens of ms and the number of rewritings was about 10 ⁶ , it could not be used as a RAM. On the other hand, in the above-mentioned MONOS type non-volatile memory of the present embodiment, the rewriting time is shortened to several tens of μs, and since writing and erasing can be performed for each bit, it can be used as a RAM. Further, rewriting is possible in an arbitrary unit such as 8 bits.

Second Embodiment This embodiment relates to a data storage device (hereinafter referred to as a cache memory system) using the MONOS type nonvolatile memory shown in the first embodiment as a main memory.

FIG. 8 is a block diagram showing a schematic structure of the cache memory system. Further, FIG. 9 is a diagram showing a main configuration when the cache memory system is used in a computer, for example. This cache memory system, as shown in FIG.
It has a MONOS memory 2, an evacuation MONOS memory 3, a control circuit 4, and a battery 5. Cache memory 1, MONOS memory 2, save MONOS memory 3
Can exchange data with each other through the data bus 6. The control circuit 4 includes a cache memory 1,
It controls the MONOS memory 2, the save MONOS memory 3, and the battery 5. The battery 5 is mainly a cache memory 1, a MONOS memory 2 and a save MON.
Power is supplied to the OS memory 3 for a save operation when the system power is cut off.

The cache memory 1 is a tag memory 10,
It includes a comparator 11 and a data memory 12. Here, reference numeral 100 in FIG. 9 indicates a central processing unit (CPU) of the computer. The CPU 100 is connected to the tag memory 10, the comparator 11, the data memory 12, and the MONOS memory 2 through the address bus 7 so that addresses can be output. Also, the CPU 10
0, the data memory 12 and the MONOS memory are connected to each other through the data bus 6 so that data can be exchanged between them.

In addition to the address bits, the tag memory 10 stores a change bit, a valid bit, a replacement algorithm bit, etc., if necessary. If the tag memory is composed of CAM, the address can be searched at once, which is advantageous in terms of speed. Data memory 12
Is a copy of a part of the data in the MONOS memory, which corresponds to the address bit in the tag memory 10 in a one-to-one relationship. The data memory 12 is SRAM, D
It has a memory cell array composed of volatile memory cells such as RAM having a data rewriting capability of the order of ns, and its capacity is, for example, about 1/100 of that of the MONOS memory 2. When the same address as that of the MONOS memory 2 is given to the cache memory 1, the content of the tag memory 10 is compared with that of the comparator 11. If the result of this comparison is a hit, the comparator 11 outputs a hit signal to the control circuit 4, for example, and as a result, access to the MONOS memory 2 is prohibited. Instead, the data corresponding to that address is retrieved from the data memory 12 and used. If the result of comparison by the comparator 11 is a miss, no hit signal is output, so C
The PU 100 can access the MONOS memory and uses the data obtained by the access.

Generally, there are two write methods of the cache memory system, a write through method shown in FIGS. 10A and 10B and a write back method shown in FIGS. 10C and 10D.

[Write-through method] When writing from the CPU, it is immediately written to the flash EEPROM. If it is a cache miss, normally nothing is done to the cache memory (FIG. 10 (B)). When there is a cache hit, when rewriting the cache memory,
There are two ways to invalidate. This system is easy to manage because the consistency between the data in the flash EEPROM and the data in the cache memory is always maintained. But,
Flash EEPR when writing, even if there is a hit
Since writing to the OM is necessary, it is disadvantageous in terms of speed.

[Write-back method] Normally, the flash EEP is executed by writing only to the cache memory.
The data is written to the RO only when the new data drives out the old data in the cache memory and replaces it at the time of a cache miss. In this method, since the flash EEPROM is not accessed at the time of hit, writing is completed at high speed. However, this method is more disadvantageous than the write-through method in that management is difficult because the time in which the contents of the flash EEPROM and the contents of the cache memory do not match.

An example of rewriting time calculation in this embodiment will be described below by taking the case of adopting the write-back method as an example, and will be compared with the case of using the conventional FG memory.

Since writing in the cache memory system in this embodiment is a write-back method, MONOS is used.
The frequency of writing to the memory 2 is greatly reduced. Therefore, the number of rewritable times of this system is orders of magnitude higher than that of the MONOS memory alone.

Further, since the cache memory uses a volatile memory element whose rewriting speed is faster than that of the MONOS memory, the data rewriting speed of this system is MO.
It is faster than the NOS memory alone. Specifically, for example, assuming that the rewriting time of the MONOS memory is 40 μs, the rewriting time of the cache memory is 40 ns, and the cache hit rate η is 90%, the data rewriting time Trw of this system is calculated by the following equation (6). It

[Equation 6]

Here, the miss penalty refers to the time required for recovery processing at the time of miss, and includes cache rewriting time and the like. However, since the rewrite time of the MONOS memory is dominant in the miss penalty, the rewrite time of the MONOS memory is 40 μs in the above formula (6).
Is used as a miss penalty. As described above, the rewriting time of this system is about 10 times faster than that of the MONOS memory.

[Comparative Example] In FIG. 8, if the MONOS memories 2 and 3 are replaced by FG memories, a conventional type cache memory system is obtained. In the calculation of the data rewriting time, the value of the mispenalty of the above formula (6) is changed to 40 ms, which is close to the value in the method 2 calculated in the comparative example of the first embodiment. Since other values in the equation (6) are not changed, the data rewriting time of the conventional system of this comparative example is about 4 ms.
Is calculated. From the above, it can be seen that the rewriting time of the system of the present embodiment is three orders of magnitude shorter than that of the conventional system, and a significant time reduction is realized.

Regarding the data read, the data in the cache memory is simply read if there is a hit, and the data in the MONOS memory is read if there is a miss. In other words, when you make a mistake, the old data in the cache memory is expelled, and the free space in that memory is
The recovery process of writing the same data as that read from the MONOS memory to the outside of the system is not performed because it takes too much time.

Further, in this system, the data memory 12
In the case where is composed of, for example, SRAM, power supply is required. When the system is powered off and the power supply to the SRAM is cut off, the control circuit 4 receives the power supply from the battery 5 and saves the stored contents in the cache memory 1 to the spare MONOS memory 3. Perform store operation. Then, when the power is restored, the backup MONO
A recall operation for recalling the data saved in the S memory 3 back into the flash memory 1 is performed. This system requires a battery when the power is turned off in this way, but the system as a whole is a non-volatile memory system.

In the cache memory system according to this embodiment, high speed rewriting is achieved as described above. Moreover, since the bit line and the source line have a memory array configuration in which each cell column is separated as shown in the first embodiment, the cache memory 1 and the MON are
The minimum unit (block size) of data exchanged with the OS memories 2 and 3 can be arbitrarily set from a minimum of 1 bit. Therefore, for example, the block size can be set to about several tens of bytes so that the hit rate becomes the highest with respect to the cache capacity of several tens of kBytes. Alternatively, if the block size is fixed, the cache capacity can be increased to maximize the hit rate.

Moreover, since the block size is not larger than necessary, the rewriting time of the MONOS memory is also minimized. Therefore, the block size can be set so that the rewriting time of the MONOS memory can be shortened while the hit rate remains the maximum or the hit rate does not decrease so much. Also in this case, the data rewriting time of the system can be shortened.

If the block size is optimized and the bit capacity of the cache memory is increased at the same time, the hit rate can be increased to about 99%, for example. In this case, the rewriting time of the present system calculated from the above equation (6) is 0.436 μs, which is 2 times that in the case of MONOS alone.
Significant speed up to 4 digits can be achieved compared to the conventional type system using digit and FG type memory.

[0069]

According to the data storage device of the present invention,
The data unit to be exchanged with the non-volatile memory device can be arbitrarily set with respect to the data capacity of the volatile memory device such as the cache memory. Therefore, the data hit rate is high, and the data read speed and rewrite speed are fast. . Further, the nonvolatile semiconductor memory device according to the present invention,
For example, it has a suitable configuration as a non-volatile memory device of the above-mentioned data storage device, and can be easily installed in a memory system having a plurality of memories including a volatile memory.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of four cells showing a basic configuration of a memory cell array of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

2A to 2C are equivalent circuit diagrams showing bias conditions at the time of writing, erasing, and reading of the nonvolatile memory cell array according to the embodiment of the present invention.

3A and 3B are a circuit diagram and a cross-sectional view showing a bias condition and an operation during writing in the nonvolatile memory cell according to the embodiment of the present invention.

FIG. 4A and FIG. 4B are a circuit diagram and a cross-sectional view showing a bias condition and an operation at the time of erasing in the nonvolatile memory cell according to the embodiment of the present invention.

5A and 5B are graphs showing binary threshold voltage distributions of memory transistors in the nonvolatile memory cell according to the embodiment of the present invention.

6A and 6B are equivalent circuit diagrams showing, as a comparative example, a memory cell array in which a wiring serving as a source is shared between adjacent cells in a row direction and a column direction.

7A and 7B are diagrams showing bias conditions during writing and erasing in a memory transistor of a comparative example.

FIG. 8 is a block diagram showing a schematic configuration of a cache memory system according to a second embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of main parts when a cache memory system according to a second embodiment of the present invention is used in a computer.

10A to 10D are explanatory diagrams of a write-through method and a write-back method, which are known as write methods of a cache memory system.

FIG. 11 is an equivalent circuit diagram of a conventionally used SRAM-based non-volatile RAM cell.

FIG. 12 is an equivalent circuit diagram of a conventionally used DRAM-based non-volatile RAM cell.

FIG. 13 is a block diagram showing a general configuration of a conventional cache memory system.

[Explanation of symbols]

1 ... Cache memory (volatile memory device), 2, 3 ...
MONOS memory (nonvolatile memory device), 4 ... Control circuit, 5 ... Battery (internal auxiliary power supply), 6 ... Data bus, 7 ... Address bus, 100 ... CPU (control circuit),
BL1 etc .... bit line (column common line), SL1 etc. source line (column direction common line), WL1 etc. word line, S /
D ... Source / drain region, BTM ... Bottom film (first potential barrier layer), CHS ... Charge storage layer, TOP ... Top film (second potential barrier layer), GD ... Gate dielectric film, GE ...
Gate electrode.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11C 16/04 G11C 11/34 Z H01L 21/8247 17/00 641 27/115 H01L 27/10 434 29 / 788 29/78 371 29/792 F-term (reference) 5B005 JJ11 MM01 UU23 UU24 5B015 HH01 HH03 JJ21 KB09 KB36 PP06 QQ16 5B025 AA07 AB03 AC01 AD04 AD05 AD08 AE05 5F083 EP18 EP22 EP49 EP77 ER02 ER11 ER21 ER23 ER27 JA04 LA12 LA20 ZA14 5F101 BA45 BB02 BB05 BC11 BD02 BD33 BE02 BE05 BE07 BG09

Claims (18)

[Claims] 1. A data storage device having a volatile memory device and a non-volatile semiconductor memory device, which stores data in cooperation with both memory devices according to input data, said non-volatile semiconductor memory device. However, a plurality of memory cells that store charges by storing charges in charge traps in a plurality of dielectric films stacked on a semiconductor are arranged in a matrix,
It has a memory cell array in which memory cells are connected by a plurality of common lines in a row direction and a column direction, and the common line in the column direction can arbitrarily set the number of bits of a data unit exchanged between memory devices. A data storage device that is separated for each cell column. 2. The volatile memory device includes a data memory for storing data, an address memory for storing an address of a data memory area, and a comparator for comparing an input address with an address in the address memory. Item 1. The data storage device according to item 1. 3. The data storage device according to claim 2, wherein the address memory is a content address memory. 4. The data storage device according to claim 2, wherein the data memory is composed of a memory element having a faster rewriting speed than the nonvolatile semiconductor memory device. 5. The data storage device according to claim 2, wherein the data memory is composed of a memory element that can be rewritten more times than the nonvolatile semiconductor memory device. 6. A memory transistor constituting a memory cell of the non-volatile semiconductor memory device, wherein a semiconductor has three layers of dielectric films functioning as a first potential barrier layer, a charge storage layer and a second potential barrier layer. The data storage device according to claim 1, which is a MONOS type memory transistor interposed between the gate electrode and the gate electrode. 7. The non-volatile semiconductor memory device according to claim 1, wherein during writing, hot electrons are injected from a channel of the semiconductor into the charge storage layer in a write unit according to a logic of input data. 7. The data storage device according to claim 6, further comprising a non-volatile memory control circuit that controls the applied voltage of the. 8. The non-volatile semiconductor memory device, wherein at the time of erasing, application of the plurality of common lines so that hot holes generated due to a band-to-band tunnel current are injected into the charge storage layer in an erasing unit. 7. The data storage device according to claim 6, further comprising a non-volatile memory control circuit that controls a voltage. 9. The non-volatile semiconductor memory device is configured to apply a plurality of common lines so that a voltage in a direction opposite to that at the time of writing is applied to a source and a drain of the memory transistor in a read unit during a read operation. 7. The data storage device according to claim 6, further comprising a non-volatile memory control circuit that controls a voltage. 10. A control circuit for controlling between memory devices, and a volatile memory device in a specific area of the non-volatile semiconductor memory device when power supply to the volatile memory device from the outside is cut off. 3. An internal auxiliary power supply for supplying power necessary for the operation of saving stored data.
The data storage device described. 11. When there is a matching address in the comparator, the input data is written to the data memory of the volatile memory device corresponding to the address, and when there is no matching address in the comparator, the data memory 11. The control circuit further comprises a control circuit for erasing a part of data in the non-volatile semiconductor memory device, writing the input data in an empty area of the data memory, and writing the data expelled from the data memory in the nonvolatile semiconductor memory device. The data storage device described. 12. When there is a matching address in the comparator, the data corresponding to the address is read from the data memory of the volatile memory device, and when there is no matching address in the comparator, the data is input to the input address. 11. The data storage device according to claim 10, further comprising a control circuit for controlling reading of corresponding data from the nonvolatile semiconductor memory device. 13. A memory cell array including a plurality of memory cells arranged in rows and columns, wherein the memory cells are stacked between a semiconductor in which a channel is formed and a gate electrode, and each of which includes a charge trap therein. It has a dielectric film of, and a plurality of common lines in the row direction and the column direction to which necessary voltages are applied when writing or erasing data or reading the stored data by injecting charges into the charge trap. A non-volatile semiconductor memory device in which memory cells in a memory cell array are connected and a common line in a column direction is separated for each cell column so that the number of bits of a data unit for writing, erasing or reading at one time can be arbitrarily set. . 14. A memory transistor constituting the memory cell comprises a three-layer dielectric film functioning as a first potential barrier layer, a charge storage layer and a second potential barrier layer between a semiconductor and a gate electrode. 14. The non-volatile semiconductor memory device according to claim 13, which is an intervening MONOS type memory transistor. 15. A non-volatile memory control for controlling a voltage applied to the plurality of common lines so that hot electrons are injected from a channel of the semiconductor into the charge storage layer in a write unit according to input data during writing. 15. The nonvolatile semiconductor memory device according to claim 14, further comprising a circuit. 16. A nonvolatile memory control for controlling an applied voltage of the plurality of common lines so that a hot hole generated due to a band-to-band tunnel current at the time of erasing is injected into the charge storage layer in an erasing unit. 15. A circuit further comprising a circuit.
A nonvolatile semiconductor memory device according to claim 1. 17. A non-volatile memory control for controlling a voltage applied to the plurality of common lines at the time of reading so that a voltage in a direction opposite to that at the time of writing is applied to a source and a drain of the memory transistor in a reading unit. 15. The nonvolatile semiconductor memory device according to claim 14, further comprising a circuit. 18. A 2-bit storage is possible by injecting charges independently into each of a source side region and a drain side region of a charge storage layer of the memory transistor, and a voltage in a direction opposite to that at the time of writing is applied between the source and the drain. 15. The non-volatile semiconductor memory device according to claim 14, further comprising a non-volatile memory control circuit that controls the applied voltage of the plurality of common lines so that the memory bit can be independently read by applying the applied voltage to the common line.