KR100916641B1 - Adaptive Frequency Error Compensation Circuit And Wide Band Frequency Synthesizer including The Same - Google Patents

Abstract

The wideband frequency synthesizer compares the frequency of the feedback signal with the output signal and the frequency of the input signal, and outputs the first correction signal based on the comparison result, and compares the frequency and phase of the feedback signal with the input signal. A phase locked loop for outputting a control voltage based on the comparison result, an error compensation circuit for compensating the first correction signal to output the second correction signal such that the control voltage is within a correction allowable range, and a second correction signal and the control voltage And a voltage controlled oscillator for outputting the output signal. Therefore, the wideband frequency synthesizer can generate a stable frequency output signal by correcting errors caused by a correction limit range that may occur in the charge pump and improving spurious characteristics.

Description

Error Compensation Circuit and Wide Frequency Frequency Synthesizer Comprising the Same {Adaptive Frequency Error Compensation Circuit And Wide Band Frequency Synthesizer including The Same}

The present invention relates to a wideband frequency synthesizer, and more particularly, to an error compensation circuit and a wideband frequency synthesizer including the same.

In current communication systems, a wideband frequency synthesizer that provides a stable frequency output signal is essential. In general, a broadband frequency synthesizer includes a voltage controlled oscillator having various operating characteristic curves, an adaptive frequency calibration apparatus for selecting an operating characteristic curve of a voltage controlled oscillator, for excellent phase noise characteristics, and It includes a phase locked loop to lock the frequency of the output signal.

When the adaptive frequency compensator selects one of the operating characteristic curves of the voltage controlled oscillator, the operation of selecting the frequency range ends, and the phase locked loop starts the operation of finely fixing the frequency in the selected frequency range. . At this time, the phase locked loop uses a charge pump to charge or discharge the loop filter to vary the control voltage and provide it to the voltage controlled oscillator so that the voltage controlled oscillator generates an output signal of stable frequency. However, since the charge pump can actually operate only within the correction allowance range between the lower limit control voltage and the upper limit control voltage, when the range of the control voltage outputted by the charge pump is out of the correction allowance range, the wideband frequency synthesizer malfunctions. That is, when the control voltage output by the charge pump is lower than the lower limit control voltage or higher than the upper limit control voltage, even if the phase is not fixed or the phase is fixed, the mismatch of the charge pump becomes large, resulting in spurious characteristics. This worsening problem occurs.

Conventionally, in order to solve this problem, a method of correcting an error by further subdividing an operating characteristic curve of a voltage controlled oscillator or monitoring a control voltage using an analog-to-digital converter has been used. However, the former has the disadvantage of increasing the complexity of the voltage controlled oscillator and deteriorating the system performance, and the latter has the disadvantage of complicating the configuration of the broadband frequency synthesizer. Therefore, there is a need for a wideband frequency synthesizer that can be fully operated by correcting an error even if the control voltage is out of the correction allowable range and can be simply implemented.

In order to solve the above problems, an object of the present invention is to provide a wideband frequency synthesizer and a synthesis method capable of supplying an output signal of a stable frequency by preventing a malfunction by correcting an error due to the correction limit range of the control voltage. .

Another object of the present invention is to provide an error compensation circuit and a compensation method capable of preventing a malfunction of a wideband frequency synthesizer by correcting an error due to a correction limit range of a control voltage.

In order to achieve the above object of the present invention, the wideband frequency synthesizer according to an embodiment of the present invention compares the frequency of the input signal and the feedback signal divided by the output signal and outputs the first correction signal based on the comparison result. An adaptive frequency correction circuit for comparing the frequency and phase of the feedback signal with the input signal and outputting a control voltage based on a result of the comparison, and applying the first correction signal so that the control voltage is within a correction tolerance range. An error compensation circuit for compensating and outputting a second correction signal, and a voltage controlled oscillator for outputting the output signal based on the second correction signal and the control voltage.

In some embodiments, the wideband frequency synthesizer may further include a first divider for dividing and outputting the input signal.

According to an embodiment, the wideband frequency synthesizer has a frequency range selection mode for selecting a frequency range of the output signal and a frequency fixed mode for fixing the frequency of the output signal within the frequency range, wherein the frequency range selection mode After the end of the frequency lock mode may be started.

According to an embodiment, the wideband frequency synthesizer may select an operating characteristic curve of the voltage controlled oscillator corresponding to the frequency range by operating the adaptive frequency correction circuit in the frequency range selection mode.

The adaptive frequency correction circuit may include: a first counter that counts the frequency of the input signal and outputs a first count signal; a second counter that counts the frequency of the feedback signal and outputs a second count signal; And a comparator for comparing the first count signal with the second count signal and outputting comparison signals, and a state machine outputting the first correction signal based on the comparison signals.

According to an embodiment, the wideband frequency synthesizer may fix the frequency of the output signal along the operating characteristic curve by operating the phase locked loop in the frequency locked mode.

According to an embodiment, the phase locked loop compares the frequency and phase of the feedback signal and the input signal, and accumulates electric charges in a capacitor inside an phase-frequency comparator, which outputs an up signal and a down signal based on the comparison result. Or a loop filter for outputting the control voltage by emitting, a charge pump for charging or discharging the loop filter based on the up signal and the down signal, and a second divider for dividing the output signal to output the feedback signal. can do.

According to an embodiment, the phase locked loop is located between the loop filter and the voltage controlled oscillator and is turned on in the frequency locked mode and turned off in the frequency range selection mode, and a reference voltage and the voltage. And a second switch located between the control oscillators and turned off in the frequency fixed mode and turned on in the frequency range selection mode.

In an exemplary embodiment, the error compensation circuit may include a lower limit comparator comparing the control voltage and a lower limit reference voltage to output a lower limit comparison signal, an upper limit comparator comparing the control voltage with an upper limit reference voltage, and outputting an upper limit comparison signal, and the lower limit. A decoder for decoding a comparison signal or the upper limit comparison signal and outputting a compensation signal, and an adder for outputting the second correction signal by performing an addition operation between the first correction signal and the compensation signal.

According to an embodiment, the error compensation circuit is located between the loop filter, the upper limit comparator and the lower limit comparator, and is located between the third switch, the decoder and the adder, which are turned on during an error compensation operation, and the error compensation. And a fourth switch turned on in operation, and a fifth switch positioned between the ground voltage and the adder and turned off in the error compensation operation.

In example embodiments, the compensation signal may include a compensation up signal for increasing a bit value of the second correction signal through the addition operation with the first correction signal, and the addition operation with the first correction signal. It may include a compensation down signal for reducing the bit value of the second correction signal.

The decoder may decode the lower limit comparison signal to output the compensation up signal, and decode the upper limit comparison signal to output the compensation down signal.

In order to achieve the above object of the present invention, the error compensation circuit according to an embodiment of the present invention compares a control voltage and a lower limit reference voltage and outputs a lower limit comparison signal, comparing the control voltage and the upper limit reference voltage. An upper limit comparator for outputting an upper limit comparison signal, a decoder for decoding the lower limit comparison signal or the upper limit comparison signal, and outputting a compensation signal, and performing an addition operation between the first correction signal and the compensation signal to perform a second correction signal. Contains an adder to output.

In example embodiments, the compensation signal may include a compensation up signal for increasing a bit value of the second correction signal through the addition operation with the first correction signal, and the addition operation with the first correction signal. It may include a compensation down signal for reducing the bit value of the second correction signal.

The decoder may decode the lower limit comparison signal to output the compensation up signal, and decode the upper limit comparison signal to output the compensation down signal.

In order to achieve the above object of the present invention, a wideband frequency synthesis method according to an embodiment of the present invention compares the frequency of the input signal and the input signal divided by the output signal in the frequency range selection mode based on the comparison result Outputting a first correction signal, comparing a frequency and a phase of the feedback signal and the input signal in a frequency fixed mode, and outputting a control voltage based on a result of the comparison, so that the control voltage is within a correction tolerance range Compensating the first correction signal to update a second correction signal, and outputting the output signal based on the second correction signal and the control voltage.

According to an embodiment, the wideband frequency synthesis method may further include dividing and outputting the input signal.

The updating of the second correction signal may include outputting a lower limit comparison signal by comparing the control voltage with a lower limit reference voltage, and outputting an upper limit comparison signal by comparing the control voltage with an upper limit reference voltage. And outputting a compensation signal by decoding the lower limit comparison signal or the upper limit comparison signal, and performing an addition operation between the first correction signal and the compensation signal to output a second correction signal. .

In example embodiments, the compensation signal may include a compensation up signal for increasing a bit value of the second correction signal through the addition operation with the first correction signal, and the addition operation with the first correction signal. It may include a compensation down signal for reducing the bit value of the second correction signal.

According to an embodiment, outputting the compensation signal may include decoding the lower limit comparison signal to output the compensation up signal, and decoding the upper limit comparison signal to output the compensation down signal. .

In order to achieve the above object of the present invention, the error compensation method according to an embodiment of the present invention by comparing the control voltage and the lower reference voltage outputting a lower limit comparison signal, by comparing the control voltage and the upper limit reference voltage Outputting an upper limit comparison signal, decoding the lower limit comparison signal or the upper limit comparison signal to output a compensation signal, and outputting a second correction signal by performing an addition operation between the first correction signal and the compensation signal; Steps.

In example embodiments, the compensation signal may include a compensation up signal for increasing a bit value of the second correction signal through the addition operation with the first correction signal, and the addition operation with the first correction signal. It may include a compensation down signal for reducing the bit value of the second correction signal.

According to an embodiment, outputting the compensation signal may include decoding the lower limit comparison signal to output the compensation up signal, and decoding the upper limit comparison signal to output the compensation down signal. .

The wideband frequency synthesizer and the synthesis method according to the embodiment of the present invention can prevent a malfunction by improving the error due to the correction limit range of the control voltage, improve the spurious characteristics, and can be simply implemented.

In addition, the broadband frequency error compensation circuit and the compensation method according to an embodiment of the present invention can prevent the malfunction of the broadband frequency synthesizer and improve the spur characteristics of the broadband frequency synthesizer by correcting an error due to a correction limit range of the control voltage. It can be implemented simply.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Similar reference numerals are used for the components in describing the drawings.

Terms such as first and second may be used to describe various components, but the components are not limited by these terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that another component may be present in the middle. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it may be understood that there is no other component in between. Other expressions describing the relationship between the components may be interpreted as well, such as "between" and "immediately between" or "neighboring to" and "directly neighboring".

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It will be understood that it does not exclude in advance the possibility of the presence or the addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

1 is a block diagram illustrating a wideband frequency synthesizer according to an embodiment of the present invention.

Referring to FIG. 1, the wideband frequency synthesizer 100 includes an adaptive frequency correction circuit 120, a phase locked loop 140, an error compensation circuit 160, a voltage controlled oscillator 180, and a first divider 190. It includes. The wideband frequency synthesizer 100 has a frequency range selection mode for selecting a frequency range of the output signal CKV and a frequency fixed mode for fixing the frequency of the output signal CKV within the selected frequency range. Start frequency locked mode after is finished.

The adaptive frequency correction circuit 120 compares the frequency of the feedback signal CKV / N dividing the output signal CKV and the input signals CKR, CKR / N in the frequency range selection mode, and compares the frequency based on the comparison result. 1 Output the correction signal TRIM1. The phase locked loop 140 compares the frequency and phase of the feedback signal CKV / N and the input signals CKR and CKR / N in the frequency locked mode and outputs a control voltage VC based on the comparison result. The error compensation circuit 160 compensates the first correction signal TRIM1 when the control voltage VC is outside the correction allowance range, and outputs the second correction signal TRIM2. On the other hand, when the control voltage VC is within the correction allowance range, since the compensation voltage is not generated in the error compensation circuit 160, the first correction signal TRIM1 is output as it is as the second correction signal TRIM2. The voltage controlled oscillator 180 outputs the output signal CKV based on the second correction signal TRIM2 and the control voltage VC. At this time, the output signal CKV is divided by a second divider (not shown) in the phase locked loop 140 to become a feedback signal CKV / N, and thus a phase-frequency comparator (not shown) in the phase locked loop 140. And a second counter (not shown) in the adaptive frequency correction circuit 120. The first divider 190 divides the input signal CKR and provides the divided input signal CKR / N to the phase locked loop 140 and the adaptive frequency correction circuit 120. The first divider 190 may not be included in the wideband frequency comparator 100, in which case the input signal CKR may be provided directly to the phase locked loop 140 and the adaptive frequency correction circuit 120.

The wideband frequency synthesizer 100 operates in a frequency range selection mode for selecting a frequency range of the output signal and a frequency fixed mode for finely fixing the frequency of the output signal in the frequency range selected in the frequency range selection mode. The wideband frequency synthesizer 100 forms a loop for selecting a frequency range by operating the adaptive frequency correction circuit 120 in the frequency range selection mode. The adaptive frequency correction circuit 120 generates the first correction signal TRIM1 based on the input signals CKR and CKR / N and the feedback signal CKV / N. In the frequency range selection mode, since the error compensation circuit 160 does not generate a compensation signal, the first correction signal TRIM1 is output to the voltage controlled oscillator 180 as the second correction signal TRIM2. Thereafter, one operating characteristic curve corresponding to the second correction signal TRIM2 is selected among various operating characteristic curves of the voltage controlled oscillator 180.

The wideband frequency synthesizer 100 operates the phase locked loop 140 in the frequency locked mode. The phase locked loop 140 generates the control voltage VC based on the input signals CKR and CKR / N and the feedback signal CKV / N. The phase locked loop 140 fixes the frequency of the output signal CKV by repeatedly performing fine correction along the operating characteristic curve of the voltage controlled oscillator 180 selected in the frequency range selection mode. If the control voltage VC to be output from the charge pump (not shown) is out of the upper limit control voltage and the lower limit control voltage, which is the allowable range of correction, the charge of the output signal may not be fixed or the output signal may be locked. Mismatch of the pump may be increased to deteriorate the spurious characteristic. In order to solve this problem, the error compensation circuit 160 determines whether the control voltage VC is out of the correction allowable range, generates a compensation signal, and adds the compensation signal to the first correction signal TRIM1 to compensate for the second correction signal TRIM2. ). That is, the compensation signal changes the bit value of the second correction signal TRIM2 by raising or lowering the bit value of the second correction signal TRIM2, and the voltage controlled oscillator 180 is changed by the changed second correction signal TRIM2. The capacitor bank value of is changed to update the operating characteristic curve of the voltage controlled oscillator 180. Thereafter, as the operating characteristic curve of the voltage controlled oscillator 180 is repeatedly updated, the frequency range in which the frequency of the output signal can be fixed within the allowable correction range of the control voltage VC of the wideband frequency synthesizer 100 is increased. Can be prevented from malfunctioning of the wideband frequency synthesizer 100 due to the correction limit range of the control voltage VC.

FIG. 2 is a block diagram illustrating an adaptive frequency correction circuit inside the wideband frequency synthesizer of FIG. 1.

2, the adaptive frequency correction circuit 120 includes a first counter 122, a second counter 124, a comparator 126, and a state machine 128.

The first counter 122 receives the input signals CKR and CKR / N, counts the frequencies of the input signals CKR and CKR / N, and outputs the first count signal OUT1. The second counter 124 receives the feedback signal CKV / N, counts the frequency of the feedback signal CKV / N, and outputs the second count signal OUT2. The comparator 126 receives the first count signal OUT1 and the second count signal OUT2, compares the first count signal OUT1 and the second count signal OUT2 by bit unit, and compares the comparison signals End_R. , End_V, Finish). The state machine 128 outputs the first correction signal TRIM1 based on the comparison signals End_R, End_V, and Finish and the state machine enable signal CK_EN.

The adaptive frequency correction circuit 120 operates in the frequency range selection mode. In the frequency range selection mode, since the error compensation circuit 160 does not generate a compensation signal, the first correction signal TRIM1 is directly output as the second correction signal TRIM2 through an adder (not shown) of the error compensation circuit 160. The operating characteristic curve of the voltage controlled oscillator 180 is selected according to the bit value of the second correction signal TRIM2. Therefore, based on a comparison result of the first count signal OUT1 and the second count signal OUT2 that count the input signals CKR, CKR / N and the feedback signal CKV / N along the first frequency locked operation loop. The low state machine 128 generates the first correction signal TRIM1, and since the compensation signal is not generated in the error compensation circuit 160, the first correction signal TRIM1 is output as it is as the second correction signal TRIM2. The operating characteristic curve of the voltage controlled oscillator 180 is selected.

For example, a binary search algorithm can be used to select an operating characteristic curve. Assuming that the first correction signal TRIM1 is a 4-bit signal and the initial bit value of the first correction signal TRIM1 is 1000, the output signal OUT1 of the first counter is the output signal of the second counter ( When higher than OUT2), the first comparison signal End_R is generated, and the state machine 128 performs a first correction signal TRIM1 based on the first comparison signal End_R and the state machine enable signal CK_EN. Is changed to 1100. Since the compensation signal is not generated by the error correction circuit 160, the first correction signal TRIM1 is output as it is through the internal adder as a second correction signal TRIM2, and the capacitor bank of the voltage controlled oscillator 180 is connected to the second. It has a capacitance corresponding to 1100, which is a bit value of the correction signal TRIM2. Subsequently, when the output signal OUT1 of the first counter is lower than the output signal OUT2 of the second counter, the second comparison signal End_V is generated, and the second comparison signal End_V and the state machine enable signal are generated. Based on CK_EN, the state machine 128 changes the first correction signal TRIM1 to 1010. Since the compensation signal is not generated by the error correction circuit 160, the first correction signal TRIM1 is output as it is through the internal adder as a second correction signal TRIM2, and the capacitor bank of the voltage controlled oscillator 180 is connected to the second. It has a capacitance corresponding to the correction signal TRIM2 1010. This is repeated until the frequencies of the input signals CKR, CKR / N and the feedback signal CKV / N are similar, and when the frequencies are similar, the comparator 126 generates a third comparison signal Finish. The final operating characteristic curve is selected by determining the capacitance of the capacitor bank corresponding to the bit value of the second correction signal TRIM2.

3 is a block diagram illustrating a phase locked loop inside the wideband frequency synthesizer of FIG. 1.

Referring to FIG. 3, phase locked loop 140 includes phase-frequency comparator 142, charge pump 146, loop filter 144, second divider 148, first switch 145A, and second Switch 145B.

The phase-frequency comparator 142 receives the input signals CKR, CKR / N and the feedback signal CKV / N to adjust the frequency and phase of the input signals CKR, CKR / N and the feedback signal CKV / N. The pulse string corresponding to the frequency and phase difference between the input signals CKR, CKR / N and the feedback signal CKV / N, that is, the up signal UP and the down signal DN, are compared based on the comparison result. Output If the phase of the input signals CKR, CKR / N is faster than the phase of the feedback signal CKV / N, an up signal UP is output, and the phases of the input signals CKR, CKR / N are fed back. When the signal Lag is slower than the phase of the signal CKV / N, the down signal DN is output. The pulse train has a pulse width that is substantially proportional to the difference in frequency and phase of the input signals CKR, CKR / N and the feedback signal CKV / N.

The charge pump 146 receives the up signal UP and the down signal DN, and provides a charge pump current ICP to the loop filter 144 according to the up signal UP or the down signal DN. The filter 144 is charged or discharged, and the loop filter 144 outputs the control voltage VC by accumulating or releasing charge in an internal capacitor (not shown) according to the charge pump current ICP. The second divider 148 receives the output signal CKV and divides it to output a feedback signal CKV / N. At this time, the feedback signal CKV / N is output to the phase-frequency comparator 142 and the second counter 124 of the adaptive frequency correction circuit 120.

The first switch 145A is located between the loop filter 144 and the voltage controlled oscillator 180 and is turned on in the frequency fixed mode and turned off in the frequency range selection mode to thereby voltage the control voltage VC in the frequency fixed mode. To the control oscillator 180. The second switch 145B is positioned between the reference voltage VREF and the voltage controlled oscillator 180 and is turned off in the frequency fixed mode and turned on in the frequency range selection mode to thereby convert the reference voltage VREF in the frequency range selection mode. To the voltage controlled oscillator 180. Providing the reference voltage VREF to the voltage controlled oscillator 180 in the frequency range selection mode allows the reference voltage VREF to be selected based on the operating characteristic curve of the voltage controlled oscillator 180 in the frequency range selection mode. For sake.

4 is a block diagram illustrating an error compensation circuit inside the wideband frequency synthesizer of FIG. 1.

Referring to FIG. 4, the error compensation circuit 1160 includes a lower limit comparator 162, an upper limit comparator 164, a decoder 166, an adder 168, a third switch 169A, a fourth switch 169B, and The fifth switch 169C is included.

The lower limit comparator 162 receives the control voltage VC and the lower limit reference voltage VREF_LOW and outputs the lower limit comparison signal COM_LOW by comparing the control voltage VC with the lower limit reference voltage VREF_LOW. The upper limit comparator 164 receives the control voltage VC and the upper limit reference voltage VREF_HIGH and outputs an upper limit comparison signal COM_HIGH by comparing the control voltage VC with the upper limit reference voltage VREF_HIGH. The control voltage VC is input from the loop filter 144 of the phase locked loop 140 to the lower limit comparator 162 and the upper limit comparator 164 via the third switch 169A, and the upper limit reference voltage VREF_HIGH The lower limit reference voltage VREF_LOW is a value of an upper limit and a lower limit of the correction allowable range of the charge pump 146, respectively, and is a value that may vary depending on the configuration of the charge pump 146. The lower limit comparison signal COM_LOW is activated when the control voltage VC is lower than the lower limit reference voltage VREF_LOW. The upper limit comparison signal COM_HIGH is activated when the control voltage VC is higher than the upper limit reference voltage VREF_HIGH. Is activated. When the control voltage VC has a value between the upper limit reference voltage VREF_HIGH and the lower limit reference voltage VREF_LOW, both the upper limit comparison signal COM_HIGH and the lower limit comparison signal COM_LOW are deactivated.

The decoder 166 receives the lower limit comparison signal COM_LOW or the upper limit comparison signal COM_HIGH and decodes the lower limit comparison signal COM_LOW or the upper limit comparison signal COM_HIGH to output the compensation signal COMP. The adder 168 outputs the second correction signal TRIM2 to the voltage controlled oscillator by performing an addition operation between the first correction signal TRIM1 and the compensation signal COMP. At this time, the compensation signal COMP decodes the lower limit comparison signal COM_LOW to increase the bit value of the second correction signal TRIM2, and decodes the correction up signal COMP_UP and the upper limit comparison signal COM_HIGH to decode the second limit signal. A correction down signal COMP_DN for outputting a bit value of the correction signal TRIM2 is output. That is, the lower limit comparison signal COM_LOW or the upper limit comparison signal COM_HIGH is decoded and output as a compensation signal COMP having a bit value, and the first correction signal TRIM1 and the compensation signal COMP determined in the frequency range selection mode. An addition operation is performed in between to output a second correction signal TRIM2 having a bit value corresponding to an operating characteristic curve of the voltage controlled oscillator 180.

The third switch 169A is positioned between the loop filter 144, the upper limit comparator 164, and the lower limit comparator 164, and is turned on during an error compensation operation to raise the control voltage VC to the upper limit comparator 164 and the lower limit comparator. Provided at 162. The fourth switch 169B is positioned between the decoder 166 and the adder 168 and is turned on during an error compensation operation to provide the adder with the compensation signal COMP to the adder 168 so that the first correction signal TRIM1 in the adder 168. ) And add operation between the compensation signal COMP. The fifth switch 169C is positioned between the ground voltage GND and the adder 168. When the fifth switch 169C is turned off during the error compensation operation and the error compensation operation is not necessary, the first switch signal TRIM1 and the compensation signal ( The addition operation is not performed between the COMPs so that the first correction signal TRIM1 determined in the frequency range selection mode is output as it is to the voltage controlled oscillator 180 as the second correction signal TRIM2.

5 is a block diagram illustrating an error compensation circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the error compensation circuit 200 includes a lower limit comparator 220, an upper limit comparator 240, a decoder 260, and an adder 280.

The lower limit comparator 220 receives the control voltage VC and the lower limit reference voltage VREF_LOW and compares the control voltage VC with the lower limit reference voltage VREF_LOW to output the lower limit comparison signal COM_LOW. The upper limit comparator 240 receives the control voltage VC and the upper limit reference voltage VREF_HIGH and outputs an upper limit comparison signal COM_HIGH by comparing the control voltage VC with the upper limit reference voltage VREF_HIGH. The control voltage VC is input to the lower limit comparator 220 and the upper limit comparator 240 from a loop filter (not shown) of the phase locked loop (not shown), and the upper limit reference voltage VREF_HIGH and the lower limit reference voltage VREF_LOW are The upper and lower limits of the correction allowable range of the charge pump (not shown) are values that may vary depending on the charge pump. The lower limit comparison signal COM_LOW is activated when the control voltage VC is lower than the lower limit reference voltage VREF_LOW, and the upper limit comparison signal COM_HIGH is activated when the control voltage VC is higher than the upper limit reference voltage VREF_HIGH. do. When the control voltage VC has a value between the upper limit reference voltage VREF_HIGH and the lower limit reference voltage VREF_LOW, the upper limit comparison signal COM_HIGH and the lower limit comparison signal COM_LOW are deactivated.

The decoder 260 receives the lower limit comparison signal COM_LOW or the upper limit comparison signal COM_HIGH and decodes the lower limit comparison signal COM_LOW or the upper limit comparison signal COM_HIGH to output the compensation signal COMP. The adder 280 outputs the second correction signal TRIM2 to the voltage controlled oscillator by performing an addition operation between the first correction signal TRIM1 and the compensation signal COMP. At this time, the decoder 260 decodes the lower limit comparison signal COM_LOW to decode the compensation up signal COMP_UP for increasing the bit value of the second correction signal TRIM2 and the upper limit comparison signal COM_HIGH to decode the second correction. The compensation down signal COMP_DN which reduces the bit value of the signal TRIM2 is output. That is, the lower limit comparison signal COM_LOW or the upper limit comparison signal COM_HIGH is decoded and output as a compensation signal COMP having a bit value, and between the first correction signal TRIM1 having a bit value and the compensation signal COMP. An addition operation is performed to output a second correction signal TRIM2 having a bit value corresponding to an operating characteristic curve of the voltage controlled oscillator.

6 is a block diagram illustrating a wideband frequency synthesis method according to an embodiment of the present invention.

Referring to FIG. 6, the wideband frequency synthesis method 300 compares a frequency of an input signal with a feedback signal that divides an output signal in a frequency range selection mode and outputs a first correction signal based on the comparison result (S310). ), Comparing the frequency and phase of the feedback signal and the input signal in the frequency fixed mode and outputting a control voltage based on the comparison result (S320), compensating the first correction signal so that the control voltage is within a correction tolerance range, Updating the second correction signal (S330); and outputting an output signal based on the second correction signal and the control voltage (S340). The frequency range selection mode is an operation mode for selecting a range of frequencies of an output signal, the frequency fixing mode is an operation mode for fixing a frequency of an output signal within a selected frequency range, and the frequency range selection mode is terminated. The frequency locked mode is then started.

First, in the frequency range selection mode, the frequency of the feedback signal and the input signal is compared and the first correction signal is output based on the comparison result (S310). Since the first correction signal is not compensated in the frequency range selection mode, the first correction signal is output as it is as the second correction signal. Thereafter, the frequency range selection mode ends, and the frequency fixed mode starts along the operating characteristic curve selected by the second correction signal. In the frequency fixed mode, the frequency of the output signal is fixed by comparing the frequency and phase of the feedback signal with the input signal and outputting the control voltage based on the comparison result (S320). At this time, it is determined whether the control voltage is within the correction allowable range. If the control voltage is within the allowable correction range, an output signal having a fixed frequency is output according to the operating characteristic curve at this time (S340). On the other hand, when the control voltage is outside the correction allowable range, the second correction signal is updated (S330) so that the control voltage is within the correction allowable range. As such, by updating the second correction signal, the operating characteristic curve of the voltage controlled oscillator is changed so that the control voltage is within the correction tolerance range. Therefore, the wideband frequency synthesis method 300 may prevent a malfunction due to the correction limit range of the control voltage.

7 is a block diagram illustrating an error compensation method according to an embodiment of the present invention.

Referring to FIG. 7, the error compensation method 400 outputs a lower limit comparison signal by comparing a control voltage and a lower limit reference voltage (S410), and outputs an upper limit comparison signal by comparing the control voltage with an upper limit reference voltage ( (S420), decoding the lower limit comparison signal or the upper limit comparison signal to output a compensation signal (S430), and outputting a second correction signal by performing an addition operation between the first correction signal and the compensation signal (S440). Include.

The lower limit comparison signal is output by comparing the control voltage with the lower limit reference voltage (S410), and the upper limit comparison signal is output (S420) by comparing the control voltage with the upper limit reference voltage. Thereafter, the lower limit comparison signal or the upper limit comparison signal is decoded to generate a compensation signal (S430). In this case, the compensation signal decreases the bit value of the second correction signal through an addition operation of the first correction signal and the compensation up signal that increases the bit value of the second correction signal through an addition operation with the first correction signal. And a compensation down signal. That is, the lower limit comparison signal is decoded and output as the compensation up signal, and the upper limit comparison signal is decoded and output as the compensation down signal. Thereafter, an addition operation is performed between the compensation signal and the first correction signal to output the second correction signal (S440).

Although the present invention has been described with reference to the embodiments shown in the drawings, the configuration of the frequency synthesizer and the configuration of the error compensating circuit are merely exemplary, and those skilled in the art will not depart from the spirit of the present invention. It can be modified and changed in various ways.

According to the present invention, the wideband frequency synthesizer and the synthesis method can generate a stable frequency output signal by preventing a malfunction and improving the spurious characteristics by correcting an error due to a correction limit range of the control voltage. In addition, the error compensating circuit and the compensating method may correct the error due to the correction limit range of the control voltage, thereby preventing malfunction of the wideband frequency synthesizer and improving the spur characteristics, thereby allowing the wideband frequency synthesizer to generate an output signal having a stable frequency. . Therefore, the wideband frequency synthesizer, the wideband frequency synthesis method, the error compensation circuit, and the error compensation method according to the present invention can be applied to a circuit and a communication system requiring an output signal having a stable frequency.

Although described above with reference to the preferred embodiment of the present invention, those skilled in the art that various modifications and changes within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below It will be appreciated that it can be changed.

1 is a block diagram illustrating a wideband frequency synthesizer according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an adaptive frequency correction circuit inside the wideband frequency synthesizer of FIG. 1.

3 is a block diagram illustrating a phase locked loop inside the wideband frequency synthesizer of FIG. 1.

4 is a block diagram illustrating an error compensation circuit inside the wideband frequency synthesizer of FIG. 1.

5 is a block diagram illustrating an error compensation circuit according to an exemplary embodiment of the present invention.

6 is a block diagram illustrating a wideband frequency synthesis method according to an embodiment of the present invention.

7 is a block diagram illustrating an error compensation method according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: wideband frequency synthesizer 120: adaptive frequency correction circuit

140: phase locked loop 160: error compensation circuit

180: voltage controlled oscillator

Claims (11)

An adaptive frequency correction circuit for comparing the frequency of the input signal with the feedback signal divided by the output signal and outputting a first correction signal based on the comparison result; A phase locked loop comparing the feedback signal with a frequency and a phase of the input signal and outputting a control voltage based on a result of the comparison; An error compensating circuit for compensating the first correction signal to output a second correction signal such that the control voltage is within a correction tolerance range; And And a voltage controlled oscillator for outputting the output signal based on the second correction signal and the control voltage. 2. The wideband frequency synthesizer of claim 1, further comprising a first divider for dividing and outputting the input signal. The frequency range selection mode of claim 1, further comprising a frequency range selection mode for selecting a range of frequencies of the output signal and a frequency fixed mode for fixing the frequency of the output signal within the frequency range. And said frequency locked mode is started afterwards. 4. The wideband frequency synthesizer of claim 3, wherein the operating characteristic curve of the voltage controlled oscillator corresponding to the frequency range is selected by operating the adaptive frequency correction circuit in the frequency range selection mode. 5. The wideband frequency synthesizer of claim 4, wherein the phase locked loop is operated in the frequency locked mode to fix the frequency of the output signal along the operating characteristic curve. The circuit of claim 1, wherein the error compensation circuit is A lower limit comparator comparing the control voltage with a lower limit reference voltage and outputting a lower limit comparison signal; An upper limit comparator comparing the control voltage with an upper limit reference voltage and outputting an upper limit comparison signal; A decoder configured to decode the lower limit comparison signal or the upper limit comparison signal and output a compensation signal; And And an adder for outputting the second correction signal by performing an addition operation between the first correction signal and the compensation signal. 7. The circuit of claim 6 wherein the error compensation circuitry A third switch located between the loop filter, the upper limit comparator and the lower limit comparator, and turned on in an error compensation operation; A fourth switch located between the decoder and the adder and turned on in the error compensation operation; And And a fifth switch located between a ground voltage and the adder and turned off in the error compensation operation. The method of claim 6, wherein the compensation signal A compensation up signal for increasing a bit value of the second correction signal through the addition operation with the first correction signal; And And a compensation down signal for reducing a bit value of the second correction signal through the addition operation with the first correction signal. The wideband frequency synthesizer of claim 8, wherein the decoder decodes the lower limit comparison signal to output the compensation up signal, and decodes the upper limit comparison signal to output the compensation down signal. A lower limit comparator for comparing the control voltage with the lower limit reference voltage and outputting a lower limit comparison signal; An upper limit comparator comparing the control voltage with an upper limit reference voltage to output an upper limit comparison signal; A decoder configured to decode the lower limit comparison signal or the upper limit comparison signal and output a compensation signal; And And an adder for outputting a second correction signal by performing an addition operation between the first correction signal and the compensation signal. The method of claim 10, wherein the compensation signal A compensation up signal for increasing a bit value of the second correction signal through the addition operation with the first correction signal; And A compensation down signal for reducing a bit value of the second correction signal through the addition operation with the first correction signal, And the decoder decodes the lower limit comparison signal to output the compensation up signal, and decodes the upper limit comparison signal to output the compensation down signal.

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