JPH1127144A - Frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fraction division type frequency synthesizer which performs stable phase error compensation, is inexpensive even though it has an excellent spurious characteristic and has low power consumption by configuring a phase error compensation circuit of a fraction dividing system synthesizer with a simple circuit. SOLUTION: This synthesizer configures a loop filter 5 with a serial circuit of resistance 101 and a capacitor 100, one end of the capacitor 100 is connected to an output of a charge pump 4, the other end of the capacitor 100 is connected to one end of the resistance 101, the other end of the resistance 101 is connected to the ground, and an output from a phase error compensation circuit 9 is supplied to a connection point that connects the capacitor 100 and the resistance 101. Thereby, direct current that is leaked from the circuit 9 flows through only the resistance 101 of the filter 5, stable phase comparison gain is acquired and reliable phase error compensation can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer used for a local oscillator of a wireless communication device. More specifically, the present invention relates to a fractional frequency division type frequency synthesizer in which a phase error generated by a frequency division number switching circuit in a frequency synthesizer is compensated by a phase error compensation circuit.

[0002]

2. Description of the Related Art In a radio communication device for mobile communication,
In order to quickly switch and transmit / receive many frequency channels, a fractional frequency dividing frequency synthesizer is used as a local oscillator of a wireless communication device.

FIG. 7 shows a conventional technique disclosed in Japanese Patent Laid-Open No. 9-512.
68 shows an example of the configuration of a fractional frequency synthesizer shown at 68. In FIG. 7, 1 is a crystal oscillator that oscillates a reference frequency, 2 is a reference divider that divides the output of the crystal oscillator 1 to generate a reference frequency, 3 is a phase comparator,
Is a charge pump that converts the output of the phase comparator 3 into a current or voltage and outputs the current or voltage, 5 is a loop filter that filters the output signal of the charge pump, and 6 is a voltage controlled oscillator (Oscillation frequency controlled by the output of the loop filter 5) VCO), 7 is a variable frequency divider, 8 is a frequency division number switching circuit,
9 is a phase error compensation circuit, and 12 is a clock generation circuit.

In the prior art shown in FIG. 7, a signal (frequency fTCXO) generated by a crystal oscillator 1 is frequency-divided by a reference frequency divider 2 by a frequency division number Nc to obtain a reference frequency fref.
(Fref = fTCXO / Nc) is obtained. The phase comparator 3 outputs the reference frequency fref and the output of the variable frequency divider 7 (frequency f
The phase of v) is compared, and the resulting phase error is output to the charge pump 4. The charge pump 4 converts the phase error into a current, and converts the current into a voltage in the loop filter 5. The VCO 6 outputs a frequency (fout) according to the voltage from the loop filter 5. The variable frequency divider 7 divides the output frequency (fout) from the VCO 6 according to the frequency division number N1 generated by the frequency division number switching circuit 8 and feeds it back to the phase comparator 3.

As described above, the fractional frequency dividing frequency synthesizer of the prior art switches the frequency dividing number of the variable frequency divider 7 to realize the frequency dividing number N1 equivalently including the fractional number, and realizes the integral frequency division of the reference frequency fref. 1 is obtained. The frequency dividing number N1 is obtained by the following equation. N1 = N + fr fr = m / M Here, N, m, and M are integers, and fr is a fraction smaller than 1.

FIG. 8 shows a configuration of a frequency division number switching circuit 8 in the prior art. The frequency division number switching circuit 8 includes an integrator 202 and an adder 203. The integrator 202 includes an adder 200 having a carry-out output and a register 201. The register 201 latches the clock generated by the clock generation circuit 12 and outputs its output to the adder 200.
And to the phase error compensating circuit 9 as phase error data Eθ (n). The clock generation circuit 12 operates to refer to the content of the reference frequency divider 2 and generate a clock in the middle of the clock cycle of the reference frequency divider 2.

Next, the operation of the frequency division number switching circuit 8 will be described. In FIG. 8, N is an integer part of a division number to be set, and if fr is a part below the decimal point, the division number to be set is N
+ Fr. In the case of the above conventional example, the fractional part f
The increment step of r is 1 / M, and fr = m / M for an arbitrary set value m (m is an integer of 0 ≦ m ≦ M). The adder 200 adds m to the output of the register 201. When the addition result reaches M and an overflow occurs,
Output carry-out signal CO. When an integer m is given to the input of the integrator 202 constituted by the adder 200 and the register 201, an overflow occurs once every M / m clocks, and the carry-out signal CO is output. This is set to 1 and added to the frequency division number N in the adder 203, and the frequency division number is output to the variable frequency divider 7. As a result, the frequency division number for m / (m-1) times of M / m clocks is N, and for the remaining one time is N + 1. Therefore, the average frequency division number is N + m / M, and the desired frequency division number can be obtained by setting m arbitrarily.

FIG. 9 is a diagram showing the operation of the frequency division number switching circuit 8 when M = 4 and m = 1. FIG. 9A shows a clock output from the clock generation means 12. Adder 200
M = 1 and the output of the register 201 are applied to the input terminal of As shown in the waveform shown in FIG. 9B, each time the output clock CLK of the clock generation circuit 12 is applied to the register 201, the addition result of the adder 200 increases by one, and when the value reaches four. The adder 200 outputs the carry-out signal CO (FIG. 9C), and the adder 2
The result of adding 00 is reset to 0. When this operation is performed, as shown in FIG.
Only once, the output of the adder 203 is incremented by +1 and the average frequency division number is N + ／. However, when the above configuration is adopted, a phase error Q (n) as shown in FIG. The relationship between the phase error Q (n) and the phase error data Eθ (n) is expressed by the following equation. 2πEθ (n) / M = Q (n)

FIG. 10 shows an input waveform of the phase comparator 3 and an output waveform of the charge pump 4. Although the N + 1 frequency division is performed once every four times and the N + ／ frequency division is performed, the phase error Q (between the waveforms of FIG. 10A and FIG. n) occurs. Output frequency fout of VCO6
And the reference frequency fref, there is a relation of fout = (N + ／) fref 1 / fref = (N + ／) １ ／ 1 / fout, so that a phase error of fout / 4 occurs every time N division is performed. However, every time the N + 1 frequency division is performed, a phase error of -3fout / 4 occurs. The result of this time integration corresponds to the phase error Q (n).

In the prior art, the charge pump is of a current output type, and the output gain of the charge pump 4 is set to IP / 2.
When π is set, a rectangular wave having an amplitude of IP and a width equal to the phase error is generated at the output of the charge pump 4 due to the phase error. This rectangular wave has a cycle M times the cycle of the output of the reference frequency divider 2 or the output of the variable frequency divider 7 and is input to the VCO 6 via the loop filter 5 and modulates the output of the VCO 6 so that the reference frequency fref 1 / M is generated.

FIG. 11 is a diagram for explaining a method of canceling a phase error. FIG. 11A shows the phase error data Eθ (n). FIG. 11B shows a phase error compensation signal current waveform at the output of the phase error compensation circuit 9.
FIG. 11C shows a rectangular current waveform generated at the output of the charge pump 4 due to a phase error caused by performing fractional frequency division. FIG. 11D shows a residual signal current waveform after performing the phase error compensation. This residual signal current waveform is shown in FIG.
11B is a current waveform obtained by superimposing the waveforms of FIG. 11C and FIG. FIG. 11E shows an output voltage waveform VL of the loop filter 5 when the current shown in FIG.
Is shown. Also shown here is a state in which the conventional frequency synthesizer is synchronized with the output frequency fout, and at this time, the control voltage of the VCO 6 for outputting the output frequency fout of the VCO 6 is VVCO.

The phase error Q1 (n) generated as described above
In the prior art, a phase error compensating circuit 9 is provided to cancel the phase error, and a phase error compensating signal from the phase error compensating circuit 9 is applied to the output point of the charge pump 4. FIG. 12 is a diagram showing details of the phase error compensating circuit 9 in the related art. The phase error compensating circuit 9 includes a pulse width adjusting circuit 108 that generates a rectangular wave having a pulse width proportional to the phase error data Eθ (n) using 2 / fTCXO as a unit of the pulse width;
It comprises an attenuator 109 for adjusting the amplitude of the rectangular wave output from the pulse width adjusting circuit 108, and an output buffer 111 for converting the rectangular wave output from the attenuator 109 into a rectangular wave having an amplitude of the current value. The phase error compensation signal generated by the phase error compensation circuit 9 having this configuration has a rectangular wave having a certain width and a current amplitude (hereinafter, referred to as a unit rectangular wave). The attenuator 109 has a current integral value of the unit rectangular wave so as to have the same current integral value as the rectangular wave due to the phase error when the phase error is ４fout.
Is set by the output buffer unit 111. Assuming that the amplitude of the phase error compensation signal is Ic, the phase error can be compensated if the relationship with the amplitude Ip of the rectangular wave due to the phase error is represented by the following equation. That is, this condition is when the current-time product of the phase error compensation signal is equal to the current-time product of the phase error. Ip / 4fout = 2Ic / fTCXO

The pulse width adjusting circuit 1 converts such a unit rectangular wave into a pulse width.
08, the pulse width is changed by arranging the same number as the phase error data Eθ (n). In this way, the rectangular wave caused by the phase error and the current integrated value of the phase error compensation signal are output to be equal.
As shown in (d), the remaining signals are canceled out. The frequency component of the residual signal has a much higher frequency distribution than the frequency component of the rectangular wave generated due to the phase error. It is easy to remove this residual signal by the low-pass characteristic of the PLL. As shown in FIG. 11E, the output voltage waveform VL of the loop filter 5 is the sum of the residual signal and Vvco. Under the locked condition, almost no current flows through the loop filter 5, so that Vvco becomes equal to the voltage Vc across the capacitor C100.

[0014]

As described above, since the prior art phase error compensating circuit is directly connected to the output of the charge pump, a minute DC current leaks from the output buffer section of the phase error compensating circuit. In such a case, a leakage current always occurs in the charge pump to compensate for this, and the gain of the charge pump tends to be unstable. For this reason, the amplitude of the rectangular wave generated by the phase error easily changes, and accurate phase error compensation cannot be performed by the phase error compensation signal. As a result, spurious is generated in the output of the frequency synthesizer. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the charge pump can be configured so that the DC current leaking from the phase error compensation circuit flows only through the resistance of the loop filter. An object of the present invention is to provide a frequency synthesizer which eliminates the need to compensate for leakage current of a compensation circuit, can obtain a stable phase comparison gain, and performs reliable phase error compensation.

[0016]

The phase error compensating means in the frequency synthesizer according to the first invention of the present invention is a pulse width adjusting means for generating a rectangular wave according to the data of the phase error generated by the frequency dividing number switching means. An attenuator for attenuating the amplitude, and an output buffer for supplying a rectangular wave attenuated by the attenuator to a loop filter, wherein the loop filter is configured by a series circuit of a resistor and a capacitor. The other end of the capacitor is connected to one end of the resistor, the other end of the resistor is connected to the ground, and the output from the phase error compensation means is supplied to the connection point connecting the capacitor and the resistor. Is done.

In the frequency synthesizer according to the second aspect of the present invention, the output buffer in the phase error compensating means includes a PNP transistor, a first resistor connected between an emitter of the PNP transistor and a power supply, and a second resistor. , A third resistor and a capacitor connected between the base of the PNP transistor and the power supply, and a fourth resistor connected between the base of the PNP transistor and the ground, and the output of the attenuator is a first resistor. The output of the output buffer is supplied to the connection point of the resistor and the second resistor.
It is configured to be supplied from the collector of the NP transistor to the loop filter.

Further, the phase error compensating means in the frequency synthesizer according to the third invention of the present invention comprises: a pulse width adjusting means for generating a rectangular wave according to the phase error data generated by the frequency dividing number switching means; An attenuator, and an output buffer for supplying a rectangular wave attenuated by the attenuator to the loop filter.The loop filter is configured by a series circuit of a resistor and a capacitor, and one end of the capacitor is connected to an output of the charge pump. The other end of the capacitor is connected to one end of the resistor, the other end of the resistor is connected to the power supply, and an output from the phase error compensating means is supplied to a connection point connecting the capacitor and the resistor.

In the frequency synthesizer according to the fourth aspect of the present invention, the output buffer in the phase error compensating means includes:
An NPN transistor, a first resistor connected between the emitter of the NPN transistor and ground, and a second resistor.
, A third resistor and a capacitor connected between the base of the NPN transistor and ground, and the N
A fourth resistor is connected between the base of the PN transistor and the power supply, the output of the attenuator is supplied to a connection point between the first resistor and the second resistor, and the output of the output buffer is looped from the collector of the NPN transistor. It is configured to be supplied to a filter.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a diagram showing a configuration of the frequency synthesizer according to the first embodiment of the present invention. The frequency synthesizer according to the present invention shown in FIG. 1 is different from the conventional frequency synthesizer shown in FIG.
Is different from the conventional phase error compensation circuit. FIG.
In the configuration of the present invention shown in FIG. 1, 1 is a crystal oscillator 1 that oscillates a reference frequency, 2 is a reference divider that divides the output of the crystal oscillator 1 to generate a reference frequency, 3 is a phase comparator,
Reference numeral 4 denotes a charge pump that converts the output of the phase comparator 3 into a current or voltage and outputs the current or voltage. Reference numeral 5 denotes a loop filter. Reference numeral 6 denotes a voltage controlled oscillator (VCO) whose oscillation frequency is controlled by the output of the loop filter 5. A frequency divider, 8 is a frequency division number switching circuit, 9 is a phase error compensation circuit, and 12 is a clock generation circuit.

FIG. 2 shows a phase error compensating circuit 9 according to the present invention.
FIG. 3 is a diagram showing details of a loop filter 5; The phase error compensating circuit 9 in the present embodiment includes the pulse width adjusting circuit 1
08, an attenuator 109 and an output buffer 110. The pulse width adjustment circuit 108 generates a rectangular wave having a pulse width proportional to the phase error data Eθ (n).
The output buffer 1 adjusts the amplitude of the rectangular wave output from the
Reference numeral 10 converts a rectangular wave output from the attenuator 109 into a rectangular wave having a current amplitude. Output buffer 110
Is a PNP transistor 104 and a resistor 102 connected between the emitter of the PNP transistor 104 and a power supply.
And the resistor 103, the resistor 105 and the capacitor 10 connected between the base of the PNP transistor 104 and the power supply.
7 and a resistor 106 connected between the base of the PNP transistor 104 and the ground. The output of the attenuator 109 is input to the connection point between the resistors 102 and 103, and the output of the output buffer 110 is supplied from the collector of the PNP transistor 104. Output buffer 11
Numeral 0 is composed of a grounded base amplifier circuit.

Next, the operation of the phase error compensation circuit 9 will be described with reference to FIG. FIG. 3 is a diagram showing a time waveform of a signal of each unit in FIG. 2 when the phase error data Eθ (n) = 1 in a state where the frequency of the frequency synthesizer according to the present embodiment is locked at fout. FIG. 3A is a diagram illustrating a state in which the pulse width adjustment circuit 108 generates a rectangular wave P1 having a width proportional to the phase error amount output from the frequency division number switching circuit 8. The amplitude of the rectangular wave P1 is determined by the pulse width determination circuit 1.
08 is the same as the logic level V1 of the circuit used. FIG. 3B shows that the rectangular wave P1 having the voltage amplitude of V1 output from the pulse width adjustment circuit 108 is attenuator 1
FIG. 9 is a diagram showing a state where the amplitude is attenuated to an appropriate amplitude Vin at 09 and a DC component is cut off to form a rectangular wave P2.

FIG. 3C is a diagram showing an AC component waveform P3 of the current flowing through the emitter of the PNP transistor 104 when the attenuation waveform P2 output from the attenuator 109 is applied to the intersection of the resistors 102 and 103. The current value Iea of the AC component waveform P3 is the current value Iea shown in FIG.
Vi is set by the attenuator 109 so that the current value becomes equal to c.
It is obtained from n as shown by the following equation. Iea = Vin (R2 + R3) / R2R3 where R2 is the resistance value of the resistor 102, and R3 is the resistor 103
Is the resistance value.

The current expressed by the following equation is the resistance 102,
The current flows through the resistor 103 as the bias current Ied. Ied = {(V0 × R5 / (R4 + R5)) − 0.6)}
/ (R2 + R3) where R2 is the resistance value of the resistor 102 and R3 is the resistor 103
R4 is the resistance value of the resistor 105, and R5 is the resistance value of the resistor 10.
6, a resistance value V0 is a power supply voltage.

FIG. 3D shows a PNP transistor 104.
FIG. 7 is a diagram showing a state in which a current Ie having a combined current waveform in which a DC component Ied and an AC component Iea flowing through the emitter of FIG. FIG. 3E shows the PNP transistor 10.
4 is a diagram showing a current waveform Ir1 flowing through a resistor 101 of a loop filter 5 connected to a collector No. 4; FIG. Ir1
Is the current from the charge pump 4 and the phase error compensation circuit 9
Is a combined current. Current I
The voltage drop Vr1 generated at the resistor 101 when r1 flows through the resistor 101 is as follows: Vr1 = R1 × Ir1. Here, R1 is the resistance value of the resistor 101. In FIG. 2, the other end of the resistor 101 is connected to the ground. With such a connection, the average voltage of the VCO can be compensated by increasing the current value Ir1 flowing through the resistor 101 to offset the decrease in current caused by discharging the capacitor from the charge pump.

FIG. 3F shows a voltage waveform VL at the output point of the loop filter 5. The voltage across the capacitor is Vc1, and the voltage drop across the resistor 101 is Vc1.
Assuming that r1 is represented by VL = Vc1 + Vr1, since the frequency synthesizer is synchronized with the generated fout, the voltage Vc1 across the capacitor is adjusted by the PLL circuit so that the DC component becomes equal to Vvco. as a result,
The VL in the present embodiment and the VL in the prior art shown in FIG. 11 have exactly the same waveform. Therefore, in the configuration of the present embodiment, phase error compensation is performed without any problem.

Since all the DC current leaking from the phase error compensation circuit 9 flows through the resistor 101, the charge pump 4
Need not compensate for this DC current. Therefore, the phase comparison gain is stabilized, and phase error compensation is reliably performed.

Embodiment 2 FIG. 4 is a diagram illustrating a configuration of the frequency synthesizer according to the second embodiment of the present invention. The frequency synthesizer of the present invention shown in FIG. 4 is different from the frequency synthesizer of the present invention shown in FIG. 1 in that an NPN transistor is used in the phase error compensation circuit 9 and one end of a capacitor of the loop filter 5 is connected to a power supply. Is different. In the configuration of the present invention shown in FIG. 4, 1 is a crystal oscillator that oscillates a reference frequency, 2 is a reference divider that divides the output of the crystal oscillator 1 to generate a reference frequency, 3 is a phase comparator, 4 is a charge pump for converting the output of the phase comparator 3 into a current or a voltage and outputting it, 5 is a loop filter,
6 is a voltage controlled oscillator (VCO) whose oscillation frequency is controlled by the output of the loop filter 5, 7 is a variable frequency divider, 8 is a frequency division number switching circuit, 9 is a phase error compensation circuit, and 12 is a clock generation circuit. .

FIG. 5 shows a phase error compensating circuit 9 according to the present invention.
FIG. 3 is a diagram showing details of a loop filter 5; The phase error compensating circuit 9 in the present embodiment includes the pulse width adjusting circuit 1
08, an attenuator 109 and an output buffer 110. The pulse width adjustment circuit 108 generates a rectangular wave having a pulse width proportional to the phase error data Eθ (n).
The output buffer 1 adjusts the amplitude of the rectangular wave output from the
Reference numeral 10 has a function of converting a rectangular wave output from the attenuator 109 into a rectangular wave having a current amplitude. The output buffer 110 includes an NPN transistor 114 and its N
The resistor 102 and the resistor 103 connected between the emitter of the PN transistor 114 and the ground, and the resistor 1 connected between the base and the ground of the NPN transistor 114
05, capacitor 107 and NPN transistor 1
14 and a resistor 106 connected between the power supply and the base. The output of the attenuator 109 is input to the connection point between the resistors 102 and 103, and the output of the output buffer 110 is supplied from the collector of the NPN transistor 114.

Next, the operation of the phase error compensation circuit 9 will be described with reference to FIG. FIG. 6 is a diagram showing a time waveform of a signal of each unit in FIG. 5 when the phase error data Eθ (n) = 1 in a state where the frequency of the frequency synthesizer according to the present embodiment is locked at fout. FIG. 6A is a diagram illustrating a state in which the pulse width adjustment circuit 108 generates a rectangular wave P1 having a width proportional to the phase error amount output from the frequency division number switching circuit 8. The amplitude of the rectangular wave P1 is determined by the pulse width determination circuit 1.
08 is the same as the logic level Vl of the circuit used. FIG. 6B shows that the rectangular wave P1 having the voltage amplitude of V1 output from the pulse width adjustment circuit 108 is attenuator 1
FIG. 9 is a diagram showing a state where the amplitude is attenuated to an appropriate amplitude Vin at 09 and a DC component is cut off to form a rectangular wave P2.

FIG. 6C is a diagram showing an AC component waveform P3 of the current flowing through the emitter of the NPN transistor 114 when the attenuation waveform P2 output from the attenuator 109 is applied to the intersection of the resistors 102 and 103. The current value Iea of the AC component waveform P3 is Ic shown in FIG.
Attenuator 109 so that the current value becomes the same as Vin
Is obtained from the following equation. However, this current Iea has a waveform obtained by inverting the output voltage waveform of the amplitude adjusting attenuator 109. Iea = Vin (R2 + R3) / R2R3 where R2 is the resistance value of the resistor 102, and R3 is the resistor 103
Is the resistance value.

The current represented by the following equation is the resistance 102,
The current flows through the resistor 103 as the bias current Ied. Ied = {(V0 × R5 / (R4 + R5)) − 0.6)}
/ (R2 + R3) where R2 is the resistance value of the resistor 102 and R3 is the resistor 103
R4 is the resistance value of the resistor 105, and R5 is the resistance value of the resistor 10.
6, a resistance value V0 is a power supply voltage.

FIG. 6D shows an NPN transistor 114.
FIG. 7 is a diagram showing a state in which a current Ie having a combined current waveform in which a DC component Ied and an AC component Iea flowing to the emitter of FIG. FIG. 6E shows the resistance 10 of the loop filter 5 connected to the collector of the NPN transistor 114.
FIG. 3 is a diagram showing a current waveform Ir1 flowing through the circuit No. 1; Ir1 is
This is a combined current of the current from the charge pump 4 and the current from the collector of the phase error compensation circuit 9. Current Ir1
When voltage flows through the resistor 101, the voltage drop Vr1 generated in the resistor 101 is as follows: Vr1 = R1 × Ir1. Here, R1 is the resistance value of the resistor 101. In FIG. 5, the other end of the resistor 101 is connected to a power supply. By connecting in this manner, the resistance 101
, The average voltage of the VCO can be compensated by canceling the increase in current caused by charging the capacitor from the charge pump.

FIG. 6F is a diagram showing the voltage waveform VL at the output point of the loop filter 5. The voltage across the capacitor is Vc1, and the voltage drop across the resistor 101 is Vc1.
Assuming that r1, VL = VDD− (Vc1 + Vr1). Since the frequency synthesizer is synchronized with the generated fout, the voltage Vc1 across the capacitor is adjusted by the PLL circuit so that the DC component becomes equal to Vvco. . As a result, the VL in the present embodiment and the VL in the prior art shown in FIG. 11 have exactly the same waveform. Therefore, in the configuration of the present embodiment, phase error compensation is performed without any problem.

Since all the DC current leaking from the phase error compensation circuit 9 flows through the resistor 101, the charge pump 4
Need not compensate for this DC current. Therefore, the phase comparison gain is stabilized, and phase error compensation is reliably performed.

[0036]

The phase error compensating means in the frequency synthesizer according to the first invention of the present invention comprises: a pulse width adjusting circuit for generating a rectangular wave in accordance with the phase error data generated by the frequency dividing number switching means; An attenuator, and an output buffer for supplying a rectangular wave attenuated by the attenuator to the loop filter.The loop filter is configured by a series circuit of a resistor and a capacitor, and one end of the capacitor is connected to an output of the charge pump. The other end of the capacitor is connected to one end of the resistor, the other end of the resistor is connected to the ground, and the output from the phase error compensation means is supplied to the connection point connecting the capacitor and the resistor. DC current leaking from the phase error compensating means flows only through the resistance of the loop filter. Therefore, it is not necessary for the charge pump to compensate for the leakage current of the phase error compensating means, so that a stable phase comparison gain can be obtained, and it is possible to perform a reliable phase error compensation. Further, the present invention provides
This is sometimes effective when using a PNP transistor formed on an IC.

In the frequency synthesizer according to the second aspect of the present invention, the output buffer in the phase error compensating means includes a PNP transistor, a first resistor connected between the emitter of the PNP transistor and a power supply, and a second resistor. , A third resistor and a capacitor connected between the base of the PNP transistor and the power supply, and a fourth resistor connected between the base of the PNP transistor and the ground, and the output of the attenuator is a first resistor. The output of the output buffer is supplied to the connection point of the resistor and the second resistor.
Since it is configured to be supplied from the collector of the NP transistor to the loop filter, an appropriate signal for performing phase error compensation can be generated, and a stable phase comparison gain can be obtained.
Reliable phase error compensation can be performed. Since the DC current leaking from the phase error compensating means flows only through the resistance of the loop filter, the charge pump does not need to compensate for the leak current of the phase error compensating circuit, thereby simplifying the circuit configuration.

The phase error compensating means in the frequency synthesizer according to the third invention of the present invention comprises: a pulse width adjusting circuit for generating a rectangular wave according to the phase error data generated by the frequency dividing number switching means; An attenuator, and an output buffer for supplying a rectangular wave attenuated by the attenuator to the loop filter.The loop filter is configured by a series circuit of a resistor and a capacitor, and one end of the capacitor is connected to an output of the charge pump. The other end of the capacitor is connected to one end of the resistor, the other end of the resistor is connected to the power supply, and the output from the phase error compensation means is supplied to the connection point connecting the capacitor and the resistor. DC current leaking from the phase error compensating means flows only through the resistance of the loop filter. Therefore, it is not necessary for the charge pump to compensate for the leakage current of the phase error compensating means, so that a stable phase comparison gain can be obtained, and it is possible to perform a reliable phase error compensation. Further, the present invention provides
This is sometimes effective when an NPN transistor formed on an IC is used.

The output buffer in the phase error compensating means in the frequency synthesizer according to the fourth aspect of the present invention comprises:
An NPN transistor, a first resistor connected between the emitter of the NPN transistor and ground, and a second resistor.
, A third resistor and a capacitor connected between the base of the NPN transistor and ground, and the N
A fourth resistor is connected between the base of the PN transistor and the power supply, the output of the attenuator is supplied to a connection point between the first resistor and the second resistor, and the output of the output buffer is looped from the collector of the NPN transistor. Since it is configured to be supplied to the filter, it is possible to generate an appropriate signal for performing phase error compensation, obtain a stable phase comparison gain, and perform reliable phase error compensation. Further, since the DC current leaking from the phase error compensation circuit flows only through the resistance of the loop filter, it is not necessary for the charge pump to compensate for the leakage current of the phase error compensating means, thereby simplifying the circuit configuration.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a frequency synthesizer according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating configurations of a phase error compensation circuit and a loop filter according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a time waveform illustrating an operation of the phase error compensation circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration of a frequency synthesizer according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a phase error compensation circuit and a loop filter according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a time waveform illustrating an operation of the phase error compensation circuit according to the second embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of a frequency synthesizer according to the related art.

FIG. 8 is a diagram illustrating a configuration of a frequency division number switching circuit according to the related art.

FIG. 9 is a diagram showing a phase error generated by switching a fraction in a frequency synthesizer according to the related art and a time waveform showing an operation of a division number switching circuit.

FIG. 10 is a diagram showing a time waveform indicating a rectangular wave appearing in a charge pump output due to a phase error generated by frequency division switching in the related art.

FIG. 11 is a diagram showing a time waveform showing phase error compensation performed in the related art.

FIG. 12 is a diagram illustrating a configuration of a phase error compensation circuit according to the related art.

[Explanation of symbols]

1 crystal oscillator, 2 reference frequency divider, 3 phase comparator, 4
Charge pump, 5 loop filter, 6 VCO, 7
Variable frequency divider, frequency division number switching circuit, 9 phase error compensation circuit, 12 clock generation circuit, 100 capacitor (capacitance value C1), 101 resistor (resistance value R1), 102
Resistance (resistance R2), 103 resistance (resistance R3),
104, 114 transistor, 105 resistor (resistance value R4), 106 resistor (resistance value R5), 107 capacitor (capacitance value C2), 108 pulse width adjustment circuit,
9 attenuator, 110 output buffer, 200 adder, 201 register, 202 integrator, 203 adder

Claims (4)

[Claims] 1. A frequency dividing number switching means for generating an integral frequency dividing number of a reference clock using a reference clock, a voltage controlled oscillating means, and an output of the voltage controlled oscillating means. A variable frequency dividing means for dividing by a given frequency dividing number, a phase comparing means for detecting and outputting a phase error between the reference clock and an output signal of the variable frequency dividing means, and an output of the phase comparing means as an input, A charge pump for outputting a signal for controlling the voltage-controlled oscillation means, a loop filter for smoothing the output of the charge pump and supplying a signal for controlling the voltage-controlled oscillation means, and an output from the frequency division number switching means And a phase error compensating means for supplying a signal for compensating a phase error to the loop filter by the phase error compensating means. The phase error compensating means is generated by the frequency division number switching means. Pulse width adjusting means for generating a rectangular wave according to the data of the phase error, an attenuator for attenuating the amplitude thereof, and an output buffer for supplying a rectangular wave attenuated by the attenuator to a loop filter, the loop filter comprising: One end of the capacitor is connected to the output of the charge pump, the other end of the capacitor is connected to one end of the resistor, the other end of the resistor is connected to ground, An output from the phase error compensator is supplied to a connection point connecting a capacitor and the resistor. 2. An output buffer in the phase error compensating means,
A PNP transistor, a first resistor and a second resistor connected between the emitter of the PNP transistor and a power supply, a third resistor and a capacitor connected between the base of the PNP transistor and the power supply, and the PNP transistor The output of the attenuator is supplied to a connection point between the first resistor and the second resistor, and the output of the output buffer is connected to the collector of the PNP transistor. 2. The frequency synthesizer according to claim 1, wherein the signal is supplied to the loop filter. 3. A division number switching means for generating an integer division number of the reference clock using a reference clock, a voltage controlled oscillation means, and an output of the voltage controlled oscillation means, wherein the division number switching means outputs A variable frequency dividing means for dividing by a given frequency dividing number, a phase comparing means for detecting and outputting a phase error between the reference clock and an output signal of the variable frequency dividing means, and an output of the phase comparing means as an input, A charge pump for outputting a signal for controlling the voltage-controlled oscillation means, a loop filter for smoothing the output of the charge pump and supplying a signal for controlling the voltage-controlled oscillation means, and an output from the frequency division number switching means And a phase error compensating means for supplying a signal for compensating a phase error to the loop filter by the phase error compensating means: the phase error compensating means is generated by the frequency dividing number switching means. Pulse width adjusting means for generating a rectangular wave according to the data of the phase error, an attenuator for attenuating the amplitude thereof, and an output buffer for supplying a rectangular wave attenuated by the attenuator to a loop filter, wherein the loop filter includes: , A resistor and a series circuit of a capacitor, one end of the capacitor is connected to the output of the charge pump, the other end of the capacitor is connected to one end of the resistor, the other end of the resistor is connected to the power supply An output from the phase error compensating means is supplied to a connection point connecting the capacitor and the resistor. 4. An output buffer in the phase error compensating means,
An NPN transistor, a first resistor connected between the emitter of the NPN transistor and ground, and a second resistor.
, A third resistor and a capacitor connected between the base of the NPN transistor and ground, and the N
A fourth resistor connected between a base of the PN transistor and a power supply, an output of the attenuator is supplied to a connection point between the first resistor and the second resistor, and an output of the output buffer is connected to the NPN transistor 4. The frequency synthesizer according to claim 3, wherein said loop filter is supplied from said collector to said loop filter.