JP3808447B2 - PLL circuit and control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a PLL circuit and a control method therefor, and more particularly to a PLL circuit used in a mobile phone device using a plurality of frequency bands and a control method therefor.
[0002]
[Prior art]
For example, a phase locked loop (PLL) circuit of a cellular phone device that uses a single frequency band includes a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator (hereinafter referred to as VCO (Voltage Controlled Oscillator)). These are included in a closed loop.
[0003]
When a reference signal having a predetermined frequency and a feedback signal that is a part of the oscillation signal of the VCO are input, the phase comparator outputs an error signal corresponding to the phase difference between the reference signal and the feedback signal. The charge pump circuit generates a control voltage by charging or discharging a capacitor in the loop filter by flowing a current to the loop filter based on the input error signal or by drawing a current from the loop filter. This control voltage is input to the control terminal of the VCO to control the frequency (phase) of the oscillation signal (see, for example, Patent Document 1).
[0004]
FIG. 7 is a configuration diagram of an example of a PLL circuit of a conventional dual-band mobile phone device. In the figure, an example of a PLL circuit of a mobile phone device that uses both the 800 MHz band and the 1.5 MHz band is shown.
[0005]
Referring to the figure, a PLL circuit 100 includes a PLL IC 101, an 800 MHz band loop filter (LPF) 111, an 800 MHz band VCO 112, a 1.5 GHz band loop filter (LPF) 113, and an 800 MHz band VCO 114. It is comprised including.
[0006]
Furthermore, the PLL / IC 101 includes a changeover switch 102, a phase comparator 103, an 800 MHz band charge pump 104, and a 1.5 GHz band charge pump 105.
[0007]
Then, the changeover switch 102 switches the oscillation frequency to the 800 MHz band or the 1.5 GHz band. The operation of the PLL circuit 100 is the same as that of the single frequency band PLL circuit.
[0008]
By the way, as an example, a VCO used in a dual-band mobile phone device that uses both the 800 MHz band and the 1.5 MHz band oscillates both the 800 MHz band and the 1.5 MHz band. Sensitivity is different.
[0009]
Here, the voltage sensitivity will be described. In general, the voltage sensitivity can be obtained by the following equation (1).
[0010]
Kv = Δf / ΔV (1)
Here, Kv represents voltage sensitivity, ΔV represents the amount of change in the control voltage of the VCO, and Δf represents the amount of change in the oscillation frequency when the control voltage of the VCO changes by ΔV. From this equation (1), data of Δf with respect to ΔV of the VCO unit is acquired, and the voltage sensitivity Kv is obtained.
[0011]
For example, the frequency configuration of PDC (Personal Digital cellular) is 810 MHz to 885 MHz in the 800 MHz band and 1477 to 1501 MHz in the 1.5 GHz band. For this reason, the oscillation frequency of the VCO in the 800 MHz reception band needs to change by 75 MHz. Further, the VCO oscillation frequency in the 1.5 GHz reception band needs to change by 24 MHz.
[0012]
Therefore, when the change amount of the control voltage is the same in the dual-band VCO in the 1.5 GHz band and the 800 MHz band, it is necessary to design the VCO in the 800 MHz band with higher voltage sensitivity.
[0013]
On the other hand, when the voltage sensitivity is different, the PLL lock time is also different. Therefore, in order to make the PLL lock time constant in both bands, the charge pump and the LPF need two systems for the 800 MHz band and the 1.5 MHz band as shown in FIG.
[0014]
As an example of this type of two VCO PLL circuit, different oscillations can be achieved by selectively switching the output current of the charge pump built in the PLL IC and the operation control terminals of the two voltage controlled oscillators. There is a configuration for obtaining a frequency (see Patent Document 2). However, the technique described in Patent Document 2 does not control the output current of the charge pump based on a certain relational expression stored in the storage unit as in the present invention. Therefore, this technique is another invention that is completely different from the present invention in terms of structure, operation, and effect.
[0015]
[Patent Document 1]
JP 2001-53601 A (paragraph 0003)
[0016]
[Patent Document 2]
JP 2001-332971 A (paragraphs 0010 to 0012)
[0017]
[Problems to be solved by the invention]
As described above, when using a VCO having a plurality of oscillation frequencies with different voltage sensitivities, for example, two types of oscillation frequencies, the charge pump and the LPF are for the first frequency band and the second frequency band. Two lines were required.
[0018]
Therefore, an object of the present invention is to provide a PLL circuit capable of making the lock time of a PLL constant with a single charge pump and LPF configuration even when a VCO having a plurality of oscillation frequencies having different voltage sensitivities is used. It is to provide a control method.
[0019]
[Means for Solving the Problems]
A PLL circuit according to the present invention includes a phase comparator that outputs an error signal depending on a phase difference between a phase reference signal and a feedback signal, a charge pump that generates an output current based on the error signal, and a control based on the output current. A PLL circuit including a loop filter that outputs a voltage, and a voltage-controlled oscillator that is controlled by the control voltage and that oscillates at a plurality of different frequencies that outputs an oscillation signal as the feedback signal. By inputting the voltage sensitivity of the voltage controlled oscillator to the relational expression regarding the voltage sensitivity, the lock time of the PLL circuit, and the current value of the charge pump, a charge pump output current for controlling the lock time of the PLL circuit is generated between different frequency bands. means viewed including the relationship information between the lock time of the voltage sensitivity and PLL circuit of the voltage controlled oscillator, Ji Characterized in that it comprises a storage unit and the relationship information between the lock time of the current value and the PLL circuit Jiponpu is stored.
[0020]
The PLL circuit control method according to the present invention includes a phase comparator that outputs an error signal depending on a phase difference between a phase reference signal and a feedback signal, a charge pump that generates an output current based on the error signal, and the output A control method for a PLL circuit, comprising: a loop filter that outputs a control voltage based on a current; and a voltage-controlled oscillator that is controlled by the control voltage and that oscillates at a plurality of different frequencies that outputs an oscillation signal as the feedback signal. The method controls the lock time of the PLL circuit between different frequency bands by inputting the voltage sensitivity of the voltage control oscillator into the relational expression regarding the voltage sensitivity of the voltage control oscillator, the lock time of the PLL circuit and the current value of the charge pump. look including the step of generating a charge pump output current, lock voltage sensitivity and PLL circuit of the voltage controlled oscillator Time and the relationship of the information, the relationship information between the lock time of the current value and the PLL circuit of the charge pump is characterized in that it comprises a storage unit to be stored.
[0021]
More specifically, the present invention relates to a mobile phone device.
1. The storage unit stores a relational expression between the voltage sensitivity of the VCO and the lock time of the PLL input from the outside, and a relational expression between the current value of the CP and the lock time.
2. A first calculator for calculating the voltage sensitivity of the VCO from the oscillation frequency of the two VCOs at the time of PLL lock and the control voltage is provided.
3. It has the 2nd arithmetic unit which outputs a calculation result to CP by inputting and comparing the calculation result in a 1st arithmetic unit with the relational expression memorize | stored in the memory | storage part.
4). A CP is provided for switching the output current based on the result output from the second arithmetic unit.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a configuration diagram of the best mode of a PLL circuit of a cellular phone device according to the present invention. Referring to FIG. 1, a PLL circuit 1 includes a PLL / IC 11, a loop filter (LPF) 12, and a VCO unit 13.
[0023]
The PLL / IC 11 includes an analog / digital converter (hereinafter referred to as A / D) 21, a storage unit 22, a computing unit 23, an A / D 24, a computing unit 25, an A / D 26, and a phase comparator. 27 and a charge pump (hereinafter referred to as CP) 28.
[0024]
The A / D 24 converts the frequency signal when the PLL is locked into a digital signal. The A / D 26 converts the control (CTL) voltage signal of the VCO when the PLL is locked into a digital signal.
[0025]
The storage unit 22 stores information on a relational expression 41 between the voltage sensitivity of the VCO and the lock time and a relational expression 42 between the current of the CP and the lock time obtained in advance by a combination of the PLLIC 1, the VCO unit 13, and the LPF 12. The A / D 21 converts the information of the relational expressions 41 and 42 inputted from the outside into digital data and outputs it to the storage unit 22.
[0026]
The computing unit 25 calculates voltage sensitivity from the two frequency f1 and f2 information at the time of PLL operation input from the A / D 24 and the two control voltages Vctl1 and Vctl2 at the time of PLL operation.
[0027]
The computing unit 23 obtains a CP current value that satisfies the design value of the lock time by inputting the calculation result of the computing unit 25 to the relational expressions 41 and 42 in the storage unit 22.
[0028]
The CP 28 has a switch (to be described later) for switching the load resistance value based on the calculation result of the calculator 23, and switches the control voltage of the VCO.
[0029]
The phase comparator 27 compares Ref F, which is a phase reference signal of the PLL, with the phase of the output signal of the VCO, and outputs the comparison result to the CP 28 and the A / D 24.
[0030]
The VCO unit 13 includes a changeover switch 31, an 800 MHz band VCO 32, and a 1.5 GHz band VCO 33.
[0031]
The changeover switch 31 switches between the 800 MHz band and the 1.5 GHz band VCO. The switching signal 51 is input from the outside. The 800 MHz band VCO 32 is a VCO for oscillating the 800 MHz band, and the 1.5 GHz band VCO 33 is a VCO for oscillating the 1.5 GHz band.
[0032]
As described above, the voltage sensitivity is obtained by the computing unit 25, and the voltage sensitivity is inputted to the relational expressions 41 and 42 in the storage unit 22 by the computing unit 23 to obtain the CP current value, and based on the CP current value. Even if the charge pump 28 charges or discharges the LPF 12 and has two types of VCOs having different voltage sensitivities, the PLL CP and LPF can be locked with only one system regardless of the voltage sensitivity of the VCO. Can do.
[0033]
Next, a relational expression 41 between the voltage sensitivity of the VCO and the lock time and a relational expression 42 between the current of the CP and the lock time will be described. FIG. 2 is a graph 61 showing the relationship between the voltage sensitivity of the VCO and the lock time, and FIG. 3 is a graph 71 showing the relationship between the current of the CP and the lock time.
[0034]
Referring to FIG. 2, Formula 41 represents the relationship between the voltage sensitivity of the VCO and the lock time when the current reference value of CP28 is I (A). In the figure, as an example, a linear function having a negative slope is displayed as Expression 41. Further, the design value LT (sec) (constant) of the lock time is displayed as Expression 43.
[0035]
Referring to FIG. 3, Equation 42 represents the relationship between the CP current and the lock time when the reference voltage sensitivity is KVCO (Hz / V). In the figure, as an example, a linear function having a negative slope is displayed as Expression 42. Expression 43 represents the design value LT (sec) of the lock time described above, and Expression 44 represents the current reference value I (A) of the CP 28 described above.
[0036]
A table of graphs 61 and 71 including these formulas 41 to 44 is stored in the storage unit 22.
[0037]
Next, an example of the configuration of the CP 28 will be described. FIG. 4 is a configuration diagram of an example of the CP 28. Referring to the figure, CP 28 includes a PNP transistor 81, an NPN transistor 82, resistors 83 and 84 connected in parallel to the emitter of the PNP transistor 81, and a switch 83 connected between the resistor 83 and the other end of the resistor 84, The resistor 86 and the switch 87 connected to the emitter of the NPN transistor 82, the resistor 88 connected to the other end of the switch 87, the DC power supply 89, the capacitor 90, and the DC power supply 89 and the capacitor 90 are connected. The resistor 91 includes a resistor 92 connected between the base of the PNP transistor 81 and the phase comparator 27, and a resistor 93 connected between the base of the NPN transistor 82 and the phase comparator 27.
[0038]
The collectors of the PNP transistor 81 and the NPN transistor 82 are connected to each other, and a signal at the connection point is output to the LPF 12. The other ends of the resistors 86 and 88 are grounded. On the other hand, the other ends of the DC power supply 89 and the capacitor 90 are also grounded, and the connection point between the resistor 91 and the capacitor 90 and the connection point between the resistor 83 and the switch 85 are connected.
[0039]
Next, an example of the operation of the PLL circuit according to the present invention will be described. 5 and 6 are flowcharts showing an example of the operation of the PLL circuit according to the present invention. FIG. 5 shows the operation of the PLL / IC 11, and FIG. 6 shows a part of the operation of the PLL / IC 11 and the operation of the VCO unit 13.
[0040]
First, the procedure for storing the formula in the storage unit will be described. Referring to FIG. 5, the equation 41 of the VCO voltage sensitivity vs. lock time in the graph 61 obtained in advance, the equation 42 of the CP current vs. lock time in the graph 71, and the design value 43 of the design value of the lock time of the PLL are expressed as A / D21 (S1), the A / D21 converts those equations (analog data) into digital data (S2), and the digital data is stored in the storage unit 22 (S3).
[0041]
Next, a procedure for calculating the CP current value I1 will be described. Either the 800 MHz band VCO 32 or the 1.5 GHz band VCO 33 is connected by the changeover switch 31. Referring to FIG. 5, when the PLL is locked (S11), the control voltages Vctl1 and Vctl2 of the VCO 32 are detected (S12). The detection method is to measure two voltages Vctl1 and Vctl2 at the input terminal 31a of the switch 31 when the PLL is locked.
[0042]
In parallel with step S12, the oscillation frequencies f1 and f2 of the VCO 32 when the PLL is locked are detected (S13). As a detection method, two oscillation frequencies f1 and f2 at the time of PLL lock are measured at the common output terminal 34 of the VCO 32 and the VCO 33.
[0043]
The control voltages Vctl1 and Vctl2 detected in step 12 are converted into digital data by the A / D 26 (S14). In parallel with this, the oscillation frequencies f1 and f2 detected in step 13 are input to the A / D 24 via the phase comparator 27, where they are converted into digital data (S14).
[0044]
Next, the control voltages Vctl1, Vctl2 and the oscillation frequencies f1, f2 converted into digital data are input to the calculator 25 (S15). The computing unit 25 calculates the voltage sensitivity Kv by substituting the input control voltages Vctl1, Vctl2 and the oscillation frequencies f1, f2 into the above equation (1) (S16). Then, the voltage sensitivity Kv calculated by the calculator 25 is input to the calculator 23 (S17).
[0045]
The computing unit 23 executes the following processing. First, the voltage sensitivity Kv is input to the equation 41 (see FIG. 2) of the graph 61 stored in the storage unit 22, and the lock time LT1 is obtained (S18). Next, the lock time LT1 is plotted on the graph 71, and the intersection point P1 (see FIG. 3) of the current reference value I (A) of CP28 with the equation 44 is obtained (S19). Next, in the graph 71, the equation 42 is translated to the intersection P1 (S20). Next, the CP current I1 is obtained from the intersection P2 between the expression 45 obtained by translating the expression 42 and the expression 43 of the lock time design value (S21). The obtained CP current I1 is input to CP28.
[0046]
Referring to FIG. 4, when the phase of the oscillation frequency of the VCO is advanced from the reference frequency Ref F at CP 28, the NPN transistor 82 operates to discharge the LPF 12. On the other hand, when the oscillation frequency of the VCO is delayed in phase from the reference frequency Ref F, the PNP transistor 81 operates to charge the LPF 12.
[0047]
Returning to FIG. 6, when the CP current reference value I is equal to or greater than the CP current I1 (YES in S22), the switch 85 in the CP 28 is turned on and the resistors 83 and 84 are connected in parallel to The DC voltage and the emitter of the PNP transistor 81 are connected. Similarly, the switch 87 is turned on, and the resistors 86 and 88 are connected in parallel and connected to the emitter of the NPN transistor 82 (S23).
[0048]
On the other hand, when CP current I is less than CP current reference value I1 (NO in S22), switch 85 is turned off, resistor 83 is connected, and the DC voltage from DC power supply 89 and the emitter of PNP transistor 81 are connected. The As a result, the LPF 12 can be charged. Similarly, the switch 87 is turned off and the resistor 86 is connected to the emitter of the NPN transistor 82 (S24).
[0050]
As described above, when the LPF 12 is charged / discharged by the CP 28 and the difference between the oscillation frequency of the VCO and the reference frequency Ref_F is eliminated by the phase comparator 27 in the PLL / IC 11, the PLL is locked.
[0051]
The relational expression between the voltage sensitivity of the VCO and the lock time is shown below.
[0052]
ωn = (Kv * Kφ / Nt) / τ
= (Kv / Kφ) / (Nt * τ) (2)
Kv = 2π * Δf / ΔV (3)
t = ωnt / ωn = ωnt / (Kv * Kφ) / (Nt * τ)
= Ωnt * Nt * τ / (Kv * Kφ) (4)
Here, ωn is a natural angular frequency, Kv is a VCO modulation sensitivity, Δf / ΔV is a VCO voltage sensitivity, Kφ is a phase comparator sensitivity, Nt is a frequency division ratio, τ is a time constant, and t is a lock time.
[0053]
Therefore, the CP current can be kept constant even for VCOs having different voltage sensitivities by decreasing the CP current if the voltage sensitivity is high and increasing the CP current if the voltage sensitivity is low. Become. Therefore, in the case of the dual band of the 800 MHz band and the 1.5 GHz band, the CP current should be lowered at 800 MHz and the CP current should be increased at 1.5 GHz.
[0054]
That is, the voltage sensitivity of the VCO stored in the PLL IC is compared with the voltage sensitivity of the VCO in which the PLL is operating, and the CP output current becomes one by switching the CP output current. Moreover, it becomes possible to realize one system of LPF.
[0055]
In the present embodiment, the VCO having two types of oscillation frequencies has been described. For example, if the switch 31 in the VCO unit 13 in FIG. The present invention can also be applied to those having oscillation frequencies of more than one type.
[0056]
【The invention's effect】
As described above, according to the present invention, the lock time of the PLL circuit can be obtained by inputting the voltage sensitivity of the voltage control oscillator into the relational expression relating to the voltage sensitivity of the voltage control oscillator, the lock time of the PLL circuit, and the current value of the charge pump. Including a means for generating a charge pump output current that keeps constant, even when a VCO having a plurality of oscillation frequencies with different voltage sensitivities is used, the PLL lock time is made constant with a single charge pump and LPF configuration. It becomes possible to do.
[0057]
More specifically, first, in a dual-type mobile phone device having a plurality of oscillation frequency bands and different VCO voltage sensitivities for each band, it is possible to achieve a stable lock time at all times. is there. This is because the current of the CP can be switched according to the measured voltage sensitivity using a means for measuring the voltage sensitivity in the PLL / IC.
[0058]
Secondly, there is an effect of miniaturization in a dual-type mobile phone device having a plurality of oscillation frequency bands and having a different VCO voltage sensitivity for each band. This is because the loop of the PLL and VCO can be changed from a two-system configuration to a one-system configuration by switching the CP current value according to the voltage sensitivity of the VCO, so that the number of parts can be reduced. Because of that.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a preferred embodiment of a PLL circuit of a cellular phone device according to the present invention.
FIG. 2 is a graph 61 showing the relationship between the voltage sensitivity of the VCO and the lock time.
FIG. 3 is a graph 71 showing a relationship between a CP current and a lock time;
4 is a configuration diagram of an example of a CP 28. FIG.
5 is a flowchart showing an example of the operation of the PLL circuit according to the present invention. FIG. 6 is a flowchart showing an example of the operation of the PLL circuit according to the present invention. FIG. 7 is a conventional dual-band mobile phone. It is a block diagram of an example of the PLL circuit of an apparatus.
[Explanation of symbols]
1 PLL circuit 11 PLL / IC
12 Loop filter (LPF)
13 VCO part 21, 24, 26 Analog-digital converter (A / D)
22 storage units 23, 25 computing unit 27 phase comparator 28 charge pump (CP)
31 changeover switch 32 800 MHz band VCO
33 1.5 GHz band VCO
81 PNP transistor 82 NPN transistor 83, 84 Resistor 86, 88 Resistor 85, 87 Switch 89 DC power supply 90 Capacitor 91, 92, 93 Resistor

Claims (10)

A phase comparator that outputs an error signal depending on the phase difference between the phase reference signal and the feedback signal, a charge pump that generates an output current based on the error signal, and a loop filter that outputs a control voltage based on the output current; A voltage controlled oscillator that is controlled by the control voltage and that oscillates at a plurality of different frequencies that outputs an oscillation signal as the feedback signal,
Charge pump output that controls the lock time of the PLL circuit between different frequency bands by inputting the voltage sensitivity of the voltage control oscillator to the relational expression regarding the voltage sensitivity of the voltage control oscillator, the lock time of the PLL circuit, and the current value of the charge pump means for generating a current viewing including,
Information on the relational expression between the voltage sensitivity of the voltage controlled oscillator and the lock time of the PLL circuit;
A PLL circuit comprising a storage unit for storing information on a relational expression between a current value of a charge pump and a lock time of the PLL circuit. 2. The PLL circuit according to claim 1 , further comprising a first computing unit that calculates voltage sensitivity of the voltage controlled oscillator from the oscillation frequency and control voltage of each of the two voltage controlled oscillators when the PLL circuit is locked. By inputting the voltage sensitivity of the voltage controlled oscillator to the relational expression, claims, characterized in that it comprises a second calculator for calculating the charge pump output current value for controlling the lock time of the PLL circuit between different frequency bands The PLL circuit according to 1 or 2 . 4. The PLL circuit according to claim 3, wherein the charge pump includes a switch for switching an output current based on a calculation result of the second arithmetic unit. 5. The PLL circuit according to claim 1 , wherein the PLL circuit is used in a mobile phone device. A phase comparator that outputs an error signal depending on a phase difference between a phase reference signal and a feedback signal; a charge pump that generates an output current based on the error signal; and a loop filter that outputs a control voltage based on the output current; A voltage-controlled oscillator that is controlled by the control voltage and that oscillates at a plurality of different frequencies that outputs an oscillation signal as the feedback signal.
  Charge pump output that controls the lock time of the PLL circuit between different frequency bands by inputting the voltage sensitivity of the voltage control oscillator to the relational expression regarding the voltage sensitivity of the voltage control oscillator, the lock time of the PLL circuit, and the current value of the charge pump Generating a current,
Information on the relational expression between the voltage sensitivity of the voltage controlled oscillator and the lock time of the PLL circuit;
A control method for a PLL circuit, comprising: a storage unit for storing information on a relational expression between a current value of the charge pump and a lock time of the PLL circuit. 7. The control of a PLL circuit according to claim 6, further comprising a first calculator for calculating the voltage sensitivity of the voltage controlled oscillator from the oscillation frequency and the control voltage of each of the two voltage controlled oscillators when the PLL circuit is locked. Method. 2. A second arithmetic unit for calculating a charge pump output current value for controlling a lock time of a PLL circuit between different frequency bands by inputting voltage sensitivity of a voltage controlled oscillator into the relational expression. 8. A method for controlling a PLL circuit according to 6 or 7. 9. The method of controlling a PLL circuit according to claim 8, wherein the charge pump includes a switch for switching an output current based on a calculation result of the second arithmetic unit. 10. The PLL circuit control method according to claim 6, wherein the PLL circuit control method is used in a mobile phone device.

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