KR100905836B1 - Phase Lock Loop improved loop stability - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a phase locked loop that improves loop stability by compensating a change in current magnitude of a charge pump caused by ambient temperature or process change, thereby maintaining a constant current magnitude of a charge pump. And in a phase locked loop including a phase / frequency detector, a charge pump, a loop filter, and an output divider, a change in the magnitude of the current applied from the charge pump to the loop filter is maintained so that a constant current magnitude is maintained. It further comprises a pump current control unit for controlling the charge pump to improve the loop stability of the phase locked loop.

Phase locked loops, charge pumps, pump currents, analog-to-digital converters,

Description

Phase Lock Loop improved loop stability

1 is a block diagram showing the configuration of a conventional phase locked loop;

2 is a circuit diagram schematically showing the structure of a charge pump and a loop filter in a conventional phase locked loop;

3 is a graph illustrating a relationship between a change in current magnitude of a charge pump and a change in characteristics of a phase locked loop in a phase locked loop;

4 is a block diagram showing a phase locked loop according to the present invention;

5 is a block diagram showing an implementation of a pump current controller in a phase locked loop according to the present invention;

6 is an actual circuit diagram of a charge pump and a pump current controller in a phase locked loop according to the present invention; and

7 is a graph showing the characteristics of the phase locked loop according to the present invention.

Explanation of symbols on the main parts of the drawings

40: voltage controlled oscillator 41: reference frequency generator

42: reference divider 43: phase / frequency detector

44: charge pump 45: loop filter

46: output divider 47: pump current controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase lock loop used as a frequency oscillation source for providing a stable frequency signal in a frequency synthesizer or a wireless transceiver, and more particularly, to maintain a constant magnitude of a charge pump regardless of an external condition change. The present invention relates to a phase locked loop having improved loop stability.

A phase locked loop basically detects a phase difference between a reference signal and an output signal and adjusts the phase of the output signal to be in phase with the reference signal according to the detected phase difference to generate a stable frequency signal. Since is obtained, it is mainly used as a frequency source of a radio circuit.

1 is a block diagram showing the configuration of a conventional phase locked loop.

Referring to FIG. 1, the phase locked loop may include a voltage controlled oscillator 10 that generates a predetermined frequency signal and the frequency signal varies according to a control voltage, and a reference signal generator that generates a constant frequency stable to temperature changes. 11) a reference divider 12 which divides the frequency signal of the reference signal generator 11 to generate a reference signal, and a reference signal output from the reference divider 12 and an output signal of a phase locked loop. Phase / frequency detector 13 for comparing the phase and frequency of the feedback value and detecting the difference, and converting the difference detected by the phase / frequency detector 13 into a control voltage to the voltage controlled oscillator 10. The charge pump 14 and loop filter 15 to be applied and the frequency generated from the voltage controlled oscillator 10 are divided into comparable frequency bands to the phase / frequency detector 13. Output minutes for applying the baekgap comprises a period (16).

In the phase locked loop, the phase / frequency detector 13 outputs the phase / frequency difference between the reference frequency and the feedback value as an up / down (UP / DN) signal having a pulse shape, and the charge pump 14 The source current or sinking current is provided according to the up / down signal output from the phase / frequency detector 13, and the loop filter 15 is provided by the charge pump 14 while removing noise existing on the loop. The control voltage of the voltage controlled oscillator 10 is varied by changing the amount of charge represented by accumulating the current to be stored in the capacitor.

FIG. 2 is a circuit diagram showing the basic structure of the charge pump 14 and the loop filter 15. The charge pump 14 includes a source current source 141, a sinking current source 142, and the phase / frequency detector 13. Switching operation according to the up / down signal output from the output of the source current of the source current source 141 or the sinking current of the sinking current source 142 is composed of a switch (143,144), the loop filter 25 is Usually implemented as a low pass filter using capacitors (C1, C2) and resistor (R).

When the UP signal is applied to the charge pump 14, the switch 143 is turned on, and the source current is accumulated in the capacitors C1 and C2 of the loop filter 15 at the source current source 141. The voltage Vctrl is increased due to the increase in the amount of charge. On the contrary, when the down (DN) signal is applied to the charge pump 14, the switch 144 is turned on to provide a sinking current, and the control voltage is reduced due to the amount of charge accumulated in the capacitors C1 and C2 of the loop filter 25. (Vctrl) is lowered.

However, in the charge pump 14, the source current and the sinking current must have the same and constant current magnitudes. In reality, the current magnitudes depend on the change in the ambient temperature or the manufacturing process, which is large in performance of the PLL. affect.

More specifically with reference to the graph of FIG. 3, where A, B, and C each represent the magnitude of the current provided by the charge pump 14, where A <B <C. First, Figure 3 (a) is a graph showing the change in the open loop gain and phase margin of the phase-locked loop for each current size of the charge pump, it can be seen that the open loop gain increases as the current magnitude increases, It can be seen that the phase margin changes with the change in the open loop gain. Here, phase margin is an item related to stability of the entire system in relation to locking of the PLL. When phase margin is large, the stability of the system is improved, but the locking time is delayed. That is, the phase margin increases and decreases as the current magnitude changes, thereby affecting the stability and lock time of the system.

In addition, Figure 3 (b) is a graph showing the closed loop frequency response characteristics, it is preferable that the closed loop frequency response to maintain a constant value, as shown, the phase margin when the current magnitude of the charge pump is changed As the peaking occurs in the closed loop frequency response, the oscillation occurs in the closed loop step response, as shown in FIG. 3 (c), resulting in poor overall system performance of the PLL.

Therefore, in order to increase the system performance of the PLL, a means for controlling the current magnitude of the charge pump to be maintained is required, but the conventional PLL is not prepared for this.

The present invention has been proposed to solve the above problems, the object of which is to improve the loop stability by maintaining a constant current size of the charge pump by compensating for the change in the current size of the charge pump caused by the ambient temperature or process changes Provide a phase locked loop.

In order to achieve the object of the present invention as described above, the present invention, a voltage controlled oscillator for varying the oscillation frequency in accordance with the input control voltage; A reference signal generator for generating a constant frequency stable to temperature changes; A phase / frequency detector for comparing the phase and frequency of the reference signal output from the reference signal generator with the output signal of the voltage controlled oscillator and detecting the difference; A charge pump providing a source current or a sinking current in accordance with the phase and frequency difference detected by the phase / frequency detector; A loop filter varying a charge amount according to a source current and a sinking current of the charge pump to vary a control voltage of the voltage controlled oscillator; An output divider for dividing the output signal of the voltage controlled oscillator at a low frequency to enable phase and frequency comparison and providing it to the phase / frequency detector; And a pump current controller for checking the change in the magnitude of the current applied from the charge pump to the loop filter and controlling the charge pump to maintain a constant current magnitude.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, in describing in detail the operating principle of the preferred embodiment of the present invention, if it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In addition, the same reference numerals are used for parts having similar functions and functions throughout the drawings.

In addition, throughout the specification, when a part is 'connected' to another part, it is not only 'directly connected' but also 'indirectly connected' with another element in between. Include. In addition, the term 'comprising' a certain component means that the component may be further included, without excluding the other component unless specifically stated otherwise.

4 is a block diagram illustrating a phase locked loop with improved loop stability according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the phase locked loop according to the present invention includes a voltage controlled oscillator 40, a reference signal generator 41, a reference divider 42, a phase / frequency detector 43, and a charge pump. 44, the loop filter 45, the output divider 46, and the pump current control part 47 are included.

The configuration of the voltage controlled oscillator 40, the reference signal generator 41, the reference divider 42, the phase / frequency detector 43, the loop filter 45, and the output divider 46 is described above. And the operation may be the same as before. That is, the feedback signal obtained by dividing the reference signal generated through the reference signal generator 41 and the reference divider 42 and the output signal of the voltage controlled oscillator 40 obtained through the output divider 46 at a low frequency. After detecting the phase difference and the frequency difference by the phase / frequency detector 43, the control of controlling the voltage controlled oscillator 40 through the charge pump 44 and the loop filter 45 to control the detected phase difference and the frequency difference. By converting and applying the signal, the frequency change of the voltage controlled oscillator 40 is compensated for to oscillate at a constant frequency. In the above configuration, the reference divider 42 may be omitted as necessary.

In the above-described operation of the phase locked loop, the current magnitude of the charge pump 44 is changed by external conditions so that the characteristics of phase margin, closed loop frequency / step response are changed, and thus the overall characteristics are not changed. By optimizing the loop stability by maintaining the open loop gain of the charge pump 44 constant through the pump current controller 47, the charge pump 44 and the pump current controller 47 will be described below. Describe the composition and operation.

In the above phase locked loop, a source current or sinking current is provided to the loop filter 45 at the charge pump 44, wherein the pump current controller 47 is connected to the loop filter 45 from the charge pump 44. The charge pump 44 is controlled so that a change in the magnitude of the applied current is checked so that a constant current magnitude is maintained accordingly.

FIG. 5 is a circuit diagram showing an embodiment of the pump current controller 47 according to the present invention. As shown in the drawing, the pump current controller 47 is simply a current magnitude (ADCIN) output from the charge pump 44. ) May be implemented as an analog-to-digital converter 471 that converts a predetermined bit into a digital signal Y [0: 3] and applies it to a switch array provided in the charge pump 44. In this case, the analog-to-digital converter 471 is the actual current magnitude transmitted from the charge pump 44 to the analog-to-digital converter 471 and the current magnitude appearing according to the operation change of the switch array provided in the charge pump 44. Designed for change relationships That is, when the magnitude of the current input from the charge pump 44 increases, the switch array operates in a direction in which the magnitude of the current of the charge pump 44 decreases, on the contrary, the magnitude of the current of the charge pump 44 decreases. In this case, the switch array is operated in a direction in which the current magnitude of the charge pump 44 increases.

6 is a detailed circuit diagram showing an example of the configuration of the charge pump 44 in the phase locked loop according to the present invention.

Referring to FIG. 6, the charge pump 44 includes a bias circuit unit 61, a switch array unit 62, and an output unit 63.

The bias circuit unit 61 is for configuring the source current source and the sinking current source, and is implemented to connect a plurality of current mirror circuits to generate a desired source current and a sinking current. In particular, the bias circuit unit 61 is implemented to output a plurality of source currents and sinking currents having different current magnitudes by mirroring the reference currents at different ratios.

The switch array unit 62 is implemented as a plurality of switch elements for selectively applying a plurality of source currents and sinking currents generated by the bias circuit unit 61 to the output unit 63.

The output unit 63 filters the source current or sinking current transmitted from the switch array unit 62 according to the up / down signals UPB and DN applied from the phase / frequency detector 43. The output current is converted into a voltage and applied to the analog-to-digital converter 471. UPB of the up / down signals applied to the output unit 63 means a value inverting the up signal.

In FIG. 6, detailed circuits of the bias circuit unit 61, the switch array unit 62, and the output unit 63 are illustrated, but the detailed circuits are only examples and are not intended to limit the scope of the present invention.

Next, FIG. 7 is a circuit diagram illustrating an implementation example of the analog-to-digital converter 471. The comparison is performed to check the level of the current magnitude by comparing the current magnitude output from the charge pump 43 with a plurality of reference values. The first logic circuit unit 72 expressing the unit 71, the level of the current magnitude confirmed by the comparison unit 71 as a digital signal of a predetermined bit, and the digital signal output from the first logic circuit unit 72. It includes a second logic circuit portion 73 for converting the signal into a signal for controlling the switch array portion 62 of the charge pump 43.

 The comparison unit 71 compares the voltage signal ADCIN corresponding to the magnitude of the generated current of the charge pump transferred from the output unit 63 of the charge pump 43 with a plurality of reference voltages having different levels, respectively. It includes a comparator of. The plurality of comparators compare the input voltage signal ADCIN with a reference voltage, respectively, and output a '1' signal when the voltage signal ADCC is greater than the corresponding reference voltage and a '0' signal when the voltage signal ADCIN is greater than the reference voltage.

The first logic circuit unit 72 is implemented by a combination of a plurality of logic elements (AND gate, inverter, OR gate, etc.), and compares the comparison unit 71 to indicate the level of the voltage signal ADCIN. Converts to a digital signal of the set number of bits. For example, when set to 3 bits, '000', '001', '010', etc. are output according to the level of the current magnitude.

The second logic circuit unit 72 is implemented by a combination of a plurality of AND gates and a plurality of inverters. The second logic circuit unit 72 outputs a digital signal representing a current magnitude output from the first logic circuit unit 72 to the current of the charge pump 43. It converts into switch control signals of the switch array unit 72 so that the size becomes constant. For example, when there are four switches to be controlled by the switch array unit 62, and the digital signal output from the first logic circuit unit 71 is 3 bits, the second logic circuit unit 72 may be configured as the three switches. Converts a bit digital signal into a 4-bit switch control signal. In Fig. 7, among the switch control signals output from the second logic circuit portion 72, Y0B, Y1B, Y2B, Y3B are applied to a switch for switching the source current of the switch array portion 62 shown in Fig. 6, Y0, Y1, Y2, and Y3 are applied to a switch for switching the sinking current of the switch array unit 62.

 Although the detailed circuits of the comparison unit 71, the first logic circuit unit 72, and the second logic circuit unit 73 are illustrated in FIG. 7, this is only an example and is not intended to limit the present invention. In particular, the comparator 71, the first logic circuit 71, and the second logic circuit 73 may be implemented in various forms according to the resolution of the current magnitude, the number of bits of the digital signal, and the number of bits of the switch control signal. have.

According to the charge pump 44 and the pump current controller 47 described above, the source transferred from the charge pump 44 to the loop filter 45 corresponding to the phase or comparison difference detected by the phase / frequency detector 43. The magnitudes of the currents and sinking currents are always constant regardless of external conditions, in particular ambient temperature or process variations, thus making the current gain of the charge pump 44 constant, thereby improving the stability of the entire PLL loop.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those skilled in the art.

According to the above, the present invention is directed to a phase locked loop for providing a stable frequency signal, characterized by a change in external conditions in a charge pump used to convert the detected phase difference and frequency difference into a control voltage of a voltage controlled oscillator. The loop stability of the phase locked loop can be improved by compensating for the change in current magnitude and keeping it constant.

Claims (5)

delete A voltage controlled oscillator varying an oscillation frequency in accordance with an input control voltage; A reference signal generator for generating a constant frequency stable to temperature changes; A phase / frequency detector for comparing the phase and frequency of the reference signal output from the reference signal generator with the output signal of the voltage controlled oscillator and detecting the difference; A charge pump providing a source current or a sinking current in accordance with the phase and frequency difference detected by the phase / frequency detector; A loop filter varying a charge amount according to a source current and a sinking current of the charge pump to vary a control voltage of the voltage controlled oscillator; An output divider for dividing the output signal of the voltage controlled oscillator at a low frequency to enable phase and frequency comparison and providing it to the phase / frequency detector; And And a pump current controller which checks a change in the magnitude of the current applied from the charge pump to the loop filter and controls the charge pump to maintain a constant current magnitude. The charge pump A bias circuit unit outputting a plurality of source currents and sinking currents having different current magnitudes; A switch array unit including a plurality of switch elements for selectively outputting a plurality of source currents and sinking currents generated by the bias circuit unit; And And an output unit for outputting a source current or a sinking current transmitted from the switch array unit to a loop filter according to a phase / frequency difference signal applied from the phase / frequency detector. The method of claim 2, wherein the output unit And converting the source current or the sinking current output to the loop filter into a voltage signal and applying the same to the pump current controller. The method of claim 3, wherein the pump current control unit Phase with improved loop stability, characterized in that the analog-to-digital converter converts the current output from the charge pump to a digital signal in accordance with the control rule of the charge pump to apply as a switch control signal to the switch array of the charge pump Synchronous loop. The method of claim 4, wherein the analog-to-digital converter A comparison unit comparing a plurality of reference voltages with a voltage corresponding to the magnitude of the current applied by the charge pump; A first logic circuit unit for representing a comparison result of the comparison unit as a digital signal having a predetermined number of bits; And a second logic circuit part for converting the digital signal output from the first logic circuit part into a switch control signal for controlling the switch array part of the charge pump.

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