KR100900141B1 - Method for manufacturing of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, the method comprising: forming a gate over a semiconductor substrate in a cell region and a peripheral circuit region to secure a gap between gates of a cell region, a buffer oxide film, and a first nitride film over the gate; Forming a second nitride film over the first nitride film, forming a second nitride film over the first nitride film, and forming a spacer on the gate sidewall; Forming a landing plug contact hole that exposes a semiconductor substrate in a cell region using a landing plug contact mask and forming a landing plug contact hole. Can be prevented, and the contact resistance (Rc) can be reduced to prevent the tWR failure.

Landing Plug Contact, Chemical Dry Etching (CDE)

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Figure 2 is a photograph for explaining the problem of the manufacturing method of a semiconductor device according to the prior art.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a landing plug contact (LPC) of a semiconductor device.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, an isolation layer 14 defining an active region 12 is formed in a semiconductor substrate 10 in which a cell region A and a peripheral circuit region B are divided.

Next, a first photoresist layer (not shown) is formed on the semiconductor substrate 10, and the first photoresist layer is exposed and developed with a mask defining a recess gate region to form a first photoresist pattern (not shown). do.

Next, the semiconductor substrate 10 is etched using the first photoresist pattern as a mask to form a recess gate region (not shown), and the first photoresist pattern is removed.

Next, a gate oxide film (not shown) is formed inside the recess gate region, and a polysilicon film (not shown), a tungsten film (not shown), and a hard mask film (not shown) are sequentially formed on the gate oxide film. Form.

Next, the hard mask layer, the tungsten layer, and the polysilicon layer are etched by a photolithography process using a gate mask (not shown) to form a hard mask layer pattern 16a, a tungsten layer pattern 16b, and a polysilicon layer pattern ( A gate 16 made of 16c is formed.

Next, a buffer oxide film 18, a first nitride film 20, and a sacrificial oxide film 22 are formed on the gate 16.

In this case, the first nitride film 20 is formed to a thickness of 70 ~ 120 Å, the sacrificial oxide film 22 is formed of a TEOS (Tetra Ethyle Ortho Silicate) film.

Next, the sacrificial oxide layer 22, the first nitride layer 20, and the buffer oxide layer 18 in the peripheral circuit region B are etched to form spacers 24b on the sidewalls of the gate 16. do.

Referring to FIG. 1B, a second photoresist layer (not shown) is formed over the entire surface, and the second photoresist layer is exposed and developed with a cell open mask (not shown) to form a second photoresist layer pattern 26. do.

Next, the sacrificial oxide layer 22 is removed by performing a wet etching process on the cell region A. FIG.

Next, the second photosensitive film pattern 26 is removed.

Referring to FIG. 1C, a second nitride film 28 is formed on the entire surface of the semiconductor substrate 10. In the cell region A, the second nitride film 28, the first nitride film 20, and the buffer oxide film 18 may be formed. The spacer 24a is formed, and in the peripheral circuit region B, a spacer 24c having a structure of the second nitride film 28 / sacrificial oxide film 22 / first nitride film 20 / buffer oxide film 18 is formed.

In this case, the second nitride film 28 is formed to a thickness of 130 kPa ~ 160 kPa.

Then, the interlayer insulating film 30 is formed over the entire surface.

In this case, the interlayer insulating film 30 is formed of a BPSG (Boro-Phospho-Silicate-Glass) film containing boron (B) and phosphorus (P).

Next, an annealing process is performed on the interlayer insulating film 30 to densify the film.

Next, the planarization process is performed on the interlayer insulating film 30 until the second nitride film 28 is exposed.

Referring to FIG. 1D, a landing plug contact hole 32 exposing the semiconductor substrate 10 is formed using a landing plug contact mask (not shown).

2 is a photograph illustrating a problem of a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 2, the first and second nitride films 20 and 28 are at least for preventing damage to the active region 12 and diffusion of boron (B) and phosphorus (P) in the interlayer insulating film 30, respectively. Since the thickness must be formed to be greater than (70Å, 130,) of the gap, the gap between the gate 16 can not be secured when the landing plug contact hole 32 is not open (not open) phenomenon that is a problem that is caused There is this.

In addition, since the gap between the gates 16 is narrow, the contact resistance Rc becomes high, which causes a problem of time of writing recovery (tWR).

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device capable of securing a gap between gates before forming a landing plug contact hole.

Method for manufacturing a semiconductor device according to the present invention for achieving the above object,

Forming a gate over the semiconductor substrate in the cell region and the peripheral circuit region;

Forming a buffer oxide film and a first nitride film on the gate;

Selectively removing the first nitride film of the cell region by an isotropic etching process;

Forming a second nitride film on the first nitride film and completing spacers on the sidewalls of the gate;

Forming a planarized interlayer insulating film over the entire surface;

Forming a landing plug contact hole exposing a semiconductor substrate in the cell region using a landing plug contact mask

Characterized in that it comprises a.

In the method for manufacturing a semiconductor device according to the present invention,

The first nitride film is formed to a thickness of 70 ~ 120 Å,

After forming the first nitride film

Forming a sacrificial oxide film on the first nitride film;

Forming a photoresist film on the entire surface;

Exposing and developing the photoresist with a cell open mask to form a photoresist pattern;

Removing the sacrificial oxide layer by performing a wet etching process

It further comprises a,

delete

The isotropic etching process is performed by chemical dry etching (CDE; Chemical Dry Etching) process,

The isotropic etching process is used as an etching gas of CxHyFz: O₂: Ar = 1: 10: 100, (where 1≤x≤10, 0≤y≤10, 1≤z≤10, x, y, z Is an integer)

The isotropic etching process is carried out at a temperature of 150 ~ 200 ℃,

Etch selectivity ratio of the first nitride film and the buffer oxide film is 10: 1,

The first nitride film is characterized in that removed by a thickness of 10 ~ 30Å.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 3A, an isolation layer 104 defining an active region 102 is formed in a semiconductor substrate 100 in which a cell region C and a peripheral circuit region D are divided.

Next, a first photoresist layer (not shown) is formed on the semiconductor substrate 100, and the first photoresist layer is exposed and developed with a mask defining a recess gate region to form a first photoresist pattern (not shown). do.

Next, the semiconductor substrate 100 is etched using the first photoresist pattern as a mask to form a recess gate region (not shown), and the first photoresist pattern is removed.

Next, a gate oxide film (not shown) is formed inside the recess gate region, and a polysilicon film (not shown), a tungsten film (not shown), and a hard mask film (not shown) are sequentially formed on the gate oxide film. Form.

Next, the hard mask film, the tungsten film, and the polysilicon film are etched by a photolithography process using a gate mask (not shown) to form a hard mask film pattern 106a, a tungsten film pattern 106b, and a polysilicon film pattern ( A gate 106 composed of 106c is formed.

Next, a buffer oxide film 108, a first nitride film 110, and a sacrificial oxide film 112 are formed on the gate 106.

In this case, the first nitride film 110 may be formed to have a thickness of about 70 kPa to about 120 kPa in order to prevent damage to the active region 102 during the wet etching process on the subsequent cell region C.

In addition, the sacrificial oxide film 112 may be formed of a TEOS (Tetra Ethyle Ortho Silicate) film.

Next, the sacrificial oxide film 112, the first nitride film 110, and the buffer oxide film 108 in the peripheral circuit region D are etched to form a spacer 114b on the sidewall of the gate 106. .

Referring to FIG. 3B, a second photoresist film (not shown) is formed over the entire surface, and the second photoresist film is exposed and developed with a cell open mask (not shown) to form a second photoresist pattern 116. do.

Next, the sacrificial oxide layer 112 is removed by performing a wet etching process on the cell region C.

Referring to FIG. 3C, the first nitride layer 110 of the cell region C is selectively removed by an isotropic etching process.

In this case, the isotropic etching process is preferably carried out by a chemical dry etching (CDE) process in order to minimize the physical damage of the buffer oxide film (108).

Here, in the chemical dry etching process, a gas in which the ratio of CxHyFz: O₂: Ar is mixed at 1: 10: 100 is preferably used as an etching gas. (Where 1 ≦ x ≦ 10, 0 ≦ y ≦ 10, 1 ≦ z ≦ 10, and x, y, z are integers)

In addition, the chemical dry etching process may reduce the etching rate of the first nitride layer 110 and maintain the etching selectivity with the buffer oxide layer 108 at 10: 1 or more to damage the buffer oxide layer 108. In order to prevent it, it is preferable to carry out at the temperature of 150-200 degreeC.

In addition, the first nitride film 110 may be removed by a thickness of 10 kPa to 30 kPa.

Next, the second photoresist pattern 116 is removed.

Referring to FIG. 3D, a second nitride film 118 is formed on the entire surface of the semiconductor substrate 100 to form a structure of the second nitride film 118, the first nitride film 110, and the buffer oxide film 108 in the cell region C. Referring to FIG. The spacer 114a is formed, and in the peripheral circuit region D, a spacer 114c having a structure of the second nitride film 118, the sacrificial oxide film 112, the first nitride film 110, and the buffer oxide film 108 is formed.

In this case, the second nitride film 118 may have a thickness of about 130 μs to 160 μs to prevent diffusion of boron (B) and phosphorus (P) in the interlayer insulating film 120 during an annealing process on the subsequent interlayer insulating film 120. It is preferable to form.

Next, an interlayer insulating film 120 is formed over the entire surface.

In this case, the interlayer insulating film 120 may be formed of a BPSG (Boro-Phospho-Silicate-Glass) film containing boron (B) and phosphorus (P).

Next, the film quality is densified by performing an annealing process on the interlayer insulating film 120.

Next, the planarization process is performed on the interlayer insulating film 120 until the second nitride film 118 is exposed.

Referring to FIG. 3E, a landing plug contact hole 122 exposing the semiconductor substrate 100 is formed using a landing plug contact mask (not shown).

Accordingly, in the method of manufacturing a semiconductor device according to the present invention, the gap between the gates 106 may be secured by selectively removing the first nitride film 110 by an isotropic etching process for the cell region C. As a result, when the landing plug contact hole 122 is formed, it may be prevented from being open, and the contact resistance Rc may be reduced to prevent a bad time of writing recovery (tWR).

In addition, since the first nitride film 110 is partially removed from the cell region C and the gap between the gates 106 is secured, the thickness of the second nitride film 118 in the peripheral circuit region D is increased. Margins can be improved.

As described above, in the method of manufacturing a semiconductor device according to the present invention, the nitride film of the cell region is selectively removed by an isotropic etching process to secure the gap between gates, thereby preventing the opening of the landing plug contact hole. It is possible to prevent and reduce the contact resistance (Rc) to provide an effect that can prevent the tWR failure.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (9)

Forming a gate over the semiconductor substrate in the cell region and the peripheral circuit region; Sequentially forming a buffer oxide film and a first nitride film over the gate; Removing the first nitride film of the cell region to a predetermined thickness by an isotropic etching process; Forming a second nitride film on the first nitride film and completing spacers on the sidewalls of the gate; Forming a planarized interlayer insulating film over the entire surface; And Forming a landing plug contact hole exposing the semiconductor substrate in the cell region using a landing plug contact mask Method of manufacturing a semiconductor device comprising a. The method of manufacturing a semiconductor device according to claim 1, wherein the first nitride film is formed to a thickness of 70 kPa to 120 kPa. The method of claim 1, wherein after forming the first nitride film Forming a sacrificial oxide film on the first nitride film; Forming a photoresist film on the entire surface; Exposing and developing the photoresist with a cell open mask to form a photoresist pattern; And Removing the sacrificial oxide layer by performing a wet etching process Method of manufacturing a semiconductor device further comprising. delete The method of claim 1, wherein the isotropic etching process is performed by a chemical dry etching (CDE) process. The method of claim 1, wherein the isotropic etching process uses CxHyFz: O ₂ : Ar = 1: 10: 100 as an etching gas. y≤10, 1≤z≤10, x, y, z are integers) The method of claim 1, wherein the isotropic etching process is performed at a temperature of 150 ° C. to 200 ° C. 6. The method of claim 1, wherein the first nitride layer: the buffer oxide layer has an etching selectivity of 10: 1. The method of claim 2, wherein the first nitride film is removed by a thickness of about 10 μm to about 30 μm.

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