KR100894097B1 - Method of programming NAND flash memory device using self-boosting - Google Patents

Abstract

In the method of programming a NAND flash memory device according to an embodiment of the present invention, a source select transistor, a plurality of memory cells, and a drain select transistor are connected in series between a bit line and a cell source line to form a unit cell string, and a plurality of unit cell strings are provided. A method of programming a NAND flash memory device arranged in one block, the method comprising: applying a first voltage lower than a power supply voltage to a cell source line and a source select line connected to a gate of a source select transistor; Applying a power supply voltage to the drain select line connected to the gate, applying a second voltage lower than the first voltage to the selected bit line, and applying a power supply voltage to the unselected bit line, program the selected word line. Run the program by applying voltage.

Self Boosting, Local Self Boosting, Program Disturbance, Inter-Band Tunneling, Breakdown, Hot Electron

Description

Method of programming NAND flash memory device using self-boosting}

1 is a diagram illustrating a cell array of a general NAND flash memory device.

FIG. 2 is a cross-sectional view of the cell string cut along the line A-A 'of FIG. 1.

3 and 4 are cross-sectional views illustrating a method of programming a NAND flash memory device according to an embodiment of the present invention.

5 is a cross-sectional view illustrating a method of programming a NAND flash memory device according to another exemplary embodiment of the present invention.

6 is a table showing biases applied to the programming method of the NAND flash memory device according to the present invention.

The present invention relates to a method of operating a NAND flash memory device, and more particularly, to a method of programming a NAND flash memory device using self-boosting.

Flash memory devices are widely used in many electronic applications in which nonvolatile memory devices are employed. Generally, flash memory devices use one transistor cell, which provides high memory density, high reliability, and low power consumption. Generally, flash memory devices are used in portable computers, personal digital assistants (PDAs), digital cameras, portable telephones, and the like. In addition, program code, system data such as basic input / output systems (BIOS), and other firmware may also be stored in flash memory devices. Among flash memory devices, especially NAND flash memory devices have been recently used in a wider range in that high memory density can be obtained at relatively low cost.

In general, NAND flash memory devices include cell arrays. Each cell array includes a plurality of cell strings. As an example, three cell strings 110, 120, and 130 are shown in FIG. 1. Each cell string includes two select transistors and four cell transistors. For example, the cell string 110 includes two select transistors 111 and 116 and four cell transistors 112, 113, 114 and 115. The cell string 120 includes two select transistors 121 and 126 and four cell transistors 122, 123, 124 and 125. Although four cell transistors are exemplarily shown, in practice, 16 or 32 cell transistors may be connected in series, and more may be connected in series. Each cell string is connected to a corresponding bit line by each of the select transistors 111 and 121, and each of the select transistors 111 and 121 is controlled by the drain select line DSL. Each cell string is also connected to the cell source line CSL by respective select transistors 116 and 126. The source select line SSL is used to control the gates of the select transistors 116 and 126. The word line WL0 is connected to the control gates of the cell transistors 115 and 125. The word line WL1 is connected to the control gates of the cell transistors 114 and 124. The word line WL2 is connected to the control gates of the cell transistors 113 and 123. The word line WL3 is connected to the control gates of the cell transistors 112 and 122.

In such a NAND flash memory device, when the cell transistor 113 of the cell string 110 is to be programmed as an example, a program voltage is applied to the word line WL2 of the cell transistor 113 and the cell string ( The channel region of 110 is grounded. To ground the channel region, 0 V is applied (grounded) to the corresponding bit line BL1. The selection transistor 111 is turned on. Electrons in the channel region are then injected into the floating gate of the cell transistor 113. As electrons accumulate in the floating gate, the floating gate becomes negative and the threshold voltage rises. However, the word line WL2 to which the program voltage is applied is also connected to the control gates of the cell transistors 123 and 133 of the other cell strings 120 and 130. Thus, these cell transistors 123 and 133 may also be programmed undesirably. This undesired programming of unselected cells on the selected wordline is referred to as "program disturb."

Various methods have been proposed to suppress such program disturb, one of which is known as self boosting. For example, when programming the cell transistor 113 of the cell string 110, 0 V is applied to the selected bit line BL1, but a power supply voltage Vcc is applied to the unselected bit line BL2. The power supply voltage Vcc is also applied to the drain select line DSL to turn on the select transistors 111 and 121. On the other hand, 0V is applied to the source select line SSL to turn off the select transistors 116 and 126. Assuming that the cell transistors 122, 123, 124, and 125 are in an erased state, the channel in the cell string 120 is precharged by the difference between the power supply voltage Vcc and the threshold voltage of the selection transistor 121. -charge). When the channel potential in the cell string 120 reaches a sufficiently high value, the select transistor 121 is turned off and the channel of the cell transistors 122, 123, 124, and 125 is in a floating state. In this state, a program voltage, for example, a voltage of approximately 18 V is applied to the word line WL2, and a pass voltage, for example, a voltage of approximately 10 V is applied to the remaining word lines WL0, WL1, and WL3. As a result, the channel potentials of the cell transistors 122, 123, 124, and 125 are boosted to increase. The degree of increase is determined by the coupling ratio. By this increased channel potential, even if a program voltage or a pass voltage is applied, the potential difference with the channel becomes small, and hence program disturb is sufficiently suppressed.

A cross-sectional view of the cell string 120 shown along the line A-A 'in FIG. 1 is shown in FIG. Referring to FIG. 2, the N + impurity region 200 is used as a drain of the select transistor 126 and is also used as a source region of the adjacent cell transistor 125. When the cell transistors 111, 112 or 113 of the cell string 110 are programmed using the self-boosting method described above, 0 V is applied to the gate of the selection transistor 126, and the control gate of the adjacent cell transistor 125 is provided. An intermediate pass voltage is applied. Accordingly, the channel of the cell transistor 125 is boosted, and the boosted channel voltage of the cell transistor 125 is braked in the drain region 200 of the selection transistor 126 by band-to-band tunneling. Cause down. This breakdown causes discharge in the boosted channel region of cell transistor 125 and other cell transistors 122, 123, and 124 of the same cell string 120, thereby reducing channel potential and thus self-boosting. The effect is reduced, increasing the likelihood of program disturb. In addition, the electrons generated by the breakdown are accelerated toward the boosted channel region of the cell transistor 125 to become a hot electron, and the hot electrons are injected into the floating gate of the cell transistor 125 to form the cell transistor 125. The threshold voltage may be varied. These problems can be suppressed by widening the spacing between the select transistor 126 and the word line WL0, but this is in contrast to the trend of increasing the density of devices, especially in the case of multilevel cells, which have recently increased in usage. The adoption of high program voltages is increasing the likelihood of program disturb.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of programming a NAND flash memory device such that characteristic degradation of a cell transistor adjacent to a selection transistor does not occur during programming using self-boosting.

In order to achieve the above technical problem, a program method of a NAND flash memory device according to the present invention includes a unit cell string in which a source select transistor, a plurality of memory cells and a drain select transistor are connected in series between a bit line and a cell source line. A method of programming a NAND flash memory device in which a plurality of unit cell strings are arranged to form a block, the method comprising: lowering a power supply voltage to a source line of the cell source line and a source select line connected to a gate of the source select transistor Apply a first voltage, apply a power supply voltage to the drain select line connected to the gate of the drain select transistor, apply a second voltage lower than the first voltage to the selected bit line, and apply to the unselected bit line. With the power supply voltage applied, the selected word line Applying a voltage to the ram performs a program.

The first voltage may be 0.6 times the power supply voltage.

The second voltage may be 0.5 times the power supply voltage.

The pass voltage may be applied to the unselected word lines.

Among the unselected word lines, a read voltage is applied to at least one of the two word lines adjacent to the selected word line, and a pass voltage greater than the read voltage and smaller than the program voltage is applied to the remaining word lines. Can be.

A power supply voltage may be applied to a word line shared by the cell transistors closest to the source selection transistor.

The power supply voltage may be 3V, the first voltage may be 1.8V, and the second voltage may be 1.5V.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

3 and 4 are cross-sectional views illustrating a method of programming a NAND flash memory device according to an embodiment of the present invention. Specifically, FIG. 3 illustrates a cross-sectional structure of a cell string including a memory cell (hereinafter, referred to as a selected cell transistor) to be programmed, and FIG. 4 illustrates a cross-sectional view of a cell string including an unselected cell transistor sharing a word line with the selected cell transistor. The structure is shown. When programming a cell transistor in the cell string 110 of FIG. 1, the cell string shown in FIG. 3 becomes the cell string 110 of FIG. 1 and the cell string shown in FIG. 4 becomes the cell string 120 of FIG. 1. .

First, referring to FIG. 3, a program for the cell transistor 315 closest to the selection transistor 316 is first performed. Specifically, a voltage corresponding to approximately 0.6 times the power supply voltage Vcc is applied to the cell source line CSL. When the power supply voltage Vcc is 3V, 1.8V is applied to the cell source line CSL. A voltage corresponding to approximately 0.6 times the power supply voltage Vcc is also applied to the source selection line SSL connected to the gate of the selection transistor 316 connected to the cell source line CSL. A power supply voltage Vcc, for example, 3V is applied to the drain select line DSL connected to the gate of the select transistor 311 connected to the selected bit line. The drain voltage V _D corresponding to approximately 0.5 times the power supply voltage Vcc is applied to the bit line, that is, the drain of the selection transistor 311. When the power supply voltage Vcc is 3V, the drain voltage V _D is approximately 1.5V.

When 1.8V is applied to the source select line SSL and the cell source line CSL, the select transistor 316 may be at a threshold voltage of the select transistor 316 at 1.8V applied to the source select line SSL. It can deliver only 1.1V, a voltage as small as 0.7V. However, since the drain voltage V _D applied to the bit line becomes 1.5 V, the selection transistor 316 is turned off. A potential of 1.5V is maintained in the channel of the cell transistors 312, 313, 314, and 315. Under such a condition, the program voltage V _PGM , for example, 18V is applied to the word line WL0 of the selection cell transistor 315, and the word lines WL1, WL2, and WL3 of the remaining cell transistors 314, 313, and 312 are applied. ) Is applied a medium pass voltage (V _PASS ), for example 10V. Then, the electrons in the channel of the cell transistor 315 are injected into the floating gate FG0 of the cell transistor 315 by the program voltage V _PGM and the channel potential difference. As a result, the threshold voltage of the cell transistor 315 is increased. Is increased.

Next, referring to FIG. 4, while performing the program process described with reference to FIG. 3, the cell source line CSL, the source select line SSL, and the drain select line DSL are selected cell strings 310. And a bias of the same condition as that of the selected cell string 310 is applied. A voltage corresponding to approximately 0.6 times the power supply voltage Vcc is also applied to the cell source line CSL of the cell string 320 that is not specifically selected. For example, when the power supply voltage Vcc is 3V, 1.8V is applied to the cell source line CSL. Similarly, a voltage corresponding to approximately 0.6 times the power supply voltage Vcc is also applied to the source selection line SSL of the unselected cell string 320. In addition, a power supply voltage Vcc, for example, 3V is applied to the drain selection line DSL of the unselected cell string 320. On the other hand, the bit line of the unselected cell string 320, that is, the drain of the select transistor 321, is applied to the power supply voltage Vcc, for example, approximately 3 V, unlike the bit line of the selected cell string 310.

As 3V is applied to the unselected bit line and the drain select line DSL of the select transistor 321, the channel region of the cell transistors 322, 323, 324, and 325 is at the threshold of the select transistor 321 at 3V. It is precharged with a voltage value, for example a bias of 2.3V minus approximately 0.7V. In this process, when the channel region is precharged from 1.8V applied to the cell source line CSL to a size of 1.1V, which is a value of minus a threshold voltage of the selection transistor 326, for example, approximately 0.7V. Is turned off. Subsequently, as the channel region is precharged to 2.3V, the selection transistor 321 is also turned off, so that the channel region is in a floating state. In this state, a program voltage V _PGM , for example, 18V is applied to the selected word line WL0, and a medium pass voltage V _PASS , for example, 10V, is applied to the remaining word lines WL1, WL2, and WL3. The channel region of the cell transistors 322, 323, 324, 325 is then boosted to a certain size, eg 8V, by capacitive coupling. Accordingly, even when a high voltage such as 18 V is applied to the control gate of the cell transistor 325, the potential corresponding to the difference between the voltage and the channel potential is not sufficient to generate electron tunneling, thus preventing program disturb.

In particular, in the process of performing the program for the cell transistor 315, a voltage of 1.8 V is applied to both the source selection line SSL and the cell source line CSL, which is the same as that of the conventional 0V. The deviation from the program voltage V _PGM applied to the cell transistor 325 sharing the word line WL0 is reduced. As a result, interband tunneling is suppressed and breakdown in the drain region of the select transistor 326 is suppressed. As the breakdown is suppressed, the generation of hot electrons is also suppressed so that the threshold voltages of adjacent cell transistors 325 fluctuate. Does not occur.

5 is a cross-sectional view illustrating a method of programming a NAND flash memory device according to another exemplary embodiment of the present invention. This embodiment is a case where Local Self Boosting is applied.

Referring to FIG. 5, when the cell transistors 322, 323, and 324 of the unselected cell string 320 are already programmed, the floating gates of the programmed cell transistors 322, 323, and 324 are not included in the floating gate. Electrons are injected. As a result of the negative charge injected into the floating gate, precharging in the channel is not completed. Therefore, the initial potential in the channel region of the cell string 320 is low, and as a result, the possibility of program disturb is increased because self-boosting is not effectively generated in the channel region.

In order to suppress this phenomenon, a method of applying local self-boosting has been proposed. That is, when the program voltage V _PGM , for example, 18 V is applied to the word line WL0 of the cell transistor 325, the read voltage V _READ , for example 0 V, is applied to the word line WL1 of the adjacent cell transistor 324. The pass voltage V _PASS , for example, 10V is applied to the remaining word lines WL2 and WL3. The cell transistor 324 to which 0 V is applied is turned off, so that the channel potential of the cell transistor 325 is not affected by, or is almost affected by, self-boosting in the channel region of the other cell transistors 322, 323, and 324. You will not receive. Therefore, the channel region of the cell transistor 325 is self-boosted to a sufficient size by the program voltage V _PGM , and as a result, program disturb is prevented.

Even when such a local self-boosting is applied, the selected cell is applied to the bit line of the unselected cell string 320, that is, the drain of the selection transistor 321 during the program process as described with reference to FIG. 3. Unlike the bit line of the string 310, a power supply voltage Vcc, for example, approximately 3V is applied. As 3V is applied to the unselected bit line and the drain select line DSL of the select transistor 321, the channel region of the cell transistors 322, 323, 324, and 325 is at the threshold of the select transistor 321 at 3V. It is precharged with a voltage value, for example a bias of 2.3V minus approximately 0.7V. In this process, when the channel region is precharged from 1.8V applied to the cell source line CSL to a size of 1.1V, which is the size of a threshold voltage of the selection transistor 326, for example, minus approximately 0.7V. 326 is turned off. Subsequently, as the channel region is precharged to 2.3V, the selection transistor 321 is also turned off, so that the channel region is in a floating state. In this state, a program voltage V _PGM , for example, 18V is applied to the selected word line WL0, and a medium pass voltage V _PASS , for example, 10V, is applied to the remaining word lines WL1, WL2, and WL3. The channel region of the cell transistors 322, 323, 324, 325 is then boosted to a certain size, eg 8V, by capacitive coupling. Accordingly, even when a high voltage such as 18 V is applied to the control gate of the cell transistor 325, the potential corresponding to the difference between the voltage and the channel potential is not sufficient to generate electron tunneling, thus preventing program disturb.

In this case, since a voltage of 1.8V is applied to both the source selection line SSL and the cell source line CSL in the process of performing the program for the cell transistor 315, when the existing 0V is applied. In comparison, a deviation from the program voltage V _PGM applied to the cell transistor 325 sharing the same word line WL0 is reduced. As a result, interband tunneling is suppressed and breakdown in the drain region of the select transistor 326 is suppressed. As the breakdown is suppressed, the generation of hot electrons is also suppressed so that the threshold voltages of adjacent cell transistors 325 fluctuate. Does not occur. In addition, in order to apply local self-boosting, an additional bias generation circuit is required when a voltage applied to the word line WL1 of the cell transistor 324 is applied with a read voltage, for example, 0V. Since higher voltages can be used, the use of additional bias generation circuits is unnecessary.

6 is a table showing biases applied to the programming method of the NAND flash memory device according to the present invention.

Referring to FIG. 6, first, a portion indicated by "A" is used for self-boosting, and a portion denoted by "B" is used for local self-boosting. First, a power supply voltage Vcc, for example, 3V is commonly applied to the drain select line DSL. 0.5 times the supply voltage Vcc is applied to the selected bit line, that is, 1.5V. A power supply voltage Vcc, for example, 3V is applied to the unselected bit lines. 0.6 times, for example, 1.8V, of the power supply voltage Vcc is applied to the source selection line SSL and the cell source line CSL, respectively.

In the case of using self-boosting (A), in order to program at least one of the cell transistors sharing the WL0 word line, a program voltage V _PGM is applied to the WL0 word line, and the remaining WL1, WL2 and WL3 words are applied. The pass voltage V _PASS is applied to the lines. In order to program at least one of the cell transistors sharing the WL1 word line, a program voltage V _PGM is applied to the WL1 word line, and a pass voltage V _PASS is applied to the remaining WL0, WL2, and WL3 word lines. ) Is applied.

When using local self-boosting (B), in order to program at least one of the cell transistors sharing the WL1 word line, a program voltage V _PGM is applied to the WL1 word line, and a read voltage is applied to the WL0 word line. (V _READ ) is applied, and a pass voltage V _PASS is applied to the remaining WL2 and WL3 word lines. In some cases, the read voltage V _READ may be applied to the WL2 word line instead of the pass voltage V _PASS . As mentioned above, a break in the drain region of the selection transistor is applied by applying a relatively low read voltage V _READ to the gate of the cell transistor closest to the selection transistor adjacent to the cell source line CSL, that is, the word line WL0. Down occurrence is suppressed. To program at least one of the cell transistors sharing the WL2 word line, the program voltage V _PGM is applied to the WL2 word line, the read voltage V _READ is applied to the WL1 word line, and the rest of the cell transistors. The pass voltage V _PASS is applied to the WL0 and WL3 word lines. In some cases, a read voltage V _READ may be applied to the WL3 word line. In either case, the power source voltage Vcc may be applied to the word line WL0 instead of the pass voltage V _PASS .

As described so far, according to the program method of the NAND flash memory device according to the present invention, a bias of a predetermined magnitude is applied to the source selection line and the cell source line, and different sizes are applied to the selected bit line and the unselected bit line. Applying the bias provides the advantage of effectively suppressing program disturb and suppressing breakdown in the drain region of the select transistor adjacent to the cell source line. In addition, an additional bias generation circuit for local self-boosting is unnecessary, especially in the case of a multilevel cell structure applying a high program voltage, which can suppress program disturb more effectively.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (7)

A NAND flash memory comprising a source cell transistor, a plurality of memory cells and a drain select transistor connected in series between a bit line and a cell source line to form a unit cell string, and a plurality of unit cell strings are arranged to form a block. In the program method of the device, A first voltage lower than a power supply voltage is applied to the cell source line and a source select line connected to the gate of the source select transistor, a power supply voltage is applied to a drain select line connected to the gate of the drain select transistor, and a selected bit A program of a NAND flash memory device which performs a program by applying a program voltage to a selected word line while applying a second voltage lower than the first voltage to a line and applying the power supply voltage to an unselected bit line. Way. The method of claim 1, And the first voltage is 0.6 times the power supply voltage. The method of claim 1, And the second voltage is 0.5 times the power supply voltage. The method of claim 1, A method for programming a NAND flash memory device in which a pass voltage is applied to an unselected word line. The method of claim 1, A read voltage is applied to at least one of the two word lines adjacent to the selected word line among the unselected word lines, and a pass voltage greater than the read voltage and smaller than the program voltage is applied to the remaining word lines. Program method of NAND flash memory device. The method of claim 5, And applying a power supply voltage to a word line shared by a cell transistor closest to the source select transistor. The method of claim 1, The power supply voltage is 3V, the first voltage is 1.8V, the second voltage is 1.5V programming method of the NAND flash memory device.

Images