KR100891515B1 - Stack type package - Google Patents

Stack type package Download PDF

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Publication number
KR100891515B1
KR100891515B1 KR1020050128604A KR20050128604A KR100891515B1 KR 100891515 B1 KR100891515 B1 KR 100891515B1 KR 1020050128604 A KR1020050128604 A KR 1020050128604A KR 20050128604 A KR20050128604 A KR 20050128604A KR 100891515 B1 KR100891515 B1 KR 100891515B1
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South Korea
Prior art keywords
package
printed circuit
circuit board
extra
laminated
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KR1020050128604A
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Korean (ko)
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KR20070067375A (en
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김성호
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주식회사 하이닉스반도체
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Priority to KR1020050128604A priority Critical patent/KR100891515B1/en
Publication of KR20070067375A publication Critical patent/KR20070067375A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

개시된 적층형 패키지는, 일측에 솔더 볼이 실장된 페이스 다운 타입의 하부 패키지와, 하부 패키지 상에 접착제를 매개로 적층된 페이스 다운 타입의 상부 패키지와, 상부 패키지 양측단부 각각에 결합되며, 상부 패키지와 전기적으로 연결된 콘택용 인쇄회로기판 및 콘택용 인쇄회로기판과 하부 패키지를 전기적으로 연결하는 와이어를 포함함으로써, 상하부 패키지의 적층에 사용되는 인쇄회로기판을 패키지 측단부로 이동시킴에 의해 패키지 전체 두께를 줄일 수 있는 효과를 제공한다.The disclosed laminated package includes a face down type bottom package having solder balls mounted on one side, a face down type top package laminated on a bottom package via an adhesive agent, and coupled to upper ends of both sides of the top package. By including the electrically connected contact printed circuit board and the wire for electrically connecting the contact printed circuit board and the lower package, the overall thickness of the package by moving the printed circuit board used for stacking the upper and lower packages to the package side end It provides a reduction effect.

Description

적층형 패키지{Stack type package}Stack type package

도 1은 본 발명의 일 실시예에 따른 적층형 패키지를 나타낸 단면도,1 is a cross-sectional view showing a stacked package according to an embodiment of the present invention;

도 2는 도 1의 서브 와이어를 솔더로 대체한 모습을 나타낸 단면도,FIG. 2 is a cross-sectional view illustrating a state in which the subwire of FIG. 1 is replaced with solder; FIG.

도 3은 도 2의 상부 기판 상에 부가 기판을 더 적층한 모습을 나타낸 단면도,3 is a cross-sectional view illustrating a state in which an additional substrate is further stacked on the upper substrate of FIG. 2;

도 4는 도 2의 상부 기판 상에 엑스트라 기판을 더 적층한 모습을 나타낸 단면도.4 is a cross-sectional view illustrating a state in which an extra substrate is further stacked on the upper substrate of FIG. 2.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100,200,300... 적층형 패키지 110... 하부 패키지100,200,300 ... Stackable Package 110 ... Bottom Package

120... 상부 패키지 130... 콘택용 인쇄회로기판120 ... top package 130 ... printed circuit board for contacts

140... 와이어 150... 서브 와이어140 ... wire 150 ... sub wire

151... 솔더 160... 보호막151 ... solder 160 ... shield

180... 부가 패키지 181... 삽입 솔더 볼180 ... Supplementary Package 181 ... Insert Solder Ball

190... 엑스트라 패키지 191... 엑스트라 콘택용 인쇄회로기판190 ... Extra Packages 191 ... Printed Circuit Boards for Extra Contacts

192... 엑스트라 솔더 볼192 ... Extra Solder Ball

본 발명은 적층형 패키지에 관한 것으로서, 특히 FBGA 적층형 패키지에서 인쇄회로기판의 삽입 위치를 변경함에 의해 전체 두께를 줄일 수 있는 적층형 패키지에 관한 것이다.The present invention relates to a laminated package, and more particularly to a laminated package that can reduce the overall thickness by changing the insertion position of the printed circuit board in the FBGA laminated package.

반도체 패키지는 웨이퍼 공정에 의해 만들어진 개개의 다이를 실제 전자 부품으로써 사용할 수 있도록 전기적 연결을 해주고, 외부의 충격으로부터 보호되도록 밀봉 포장한 것을 말하며, 최근 고용량, 고집적, 초소형화된 반도체 제품에 대한 요구에 부응하기 위해 다양한 반도체 패키지들이 개발되고 있다.A semiconductor package is a package that is electrically sealed so that individual dies made by a wafer process can be used as actual electronic components, and is sealed to protect against external shocks. Various semiconductor packages are being developed to meet this.

이러한 다양한 반도체 패키지 중 고용량, 고집적화 등을 만족시키기 위하여 다수의 칩을 적층한 적층형 패키지가 출현하였다.In order to satisfy high capacity, high integration, and the like among various semiconductor packages, a stacked package in which a plurality of chips are stacked has appeared.

그런데, 이러한 적층형 패키지의 경우, 특히 FBGA 적층형 패키지의 경우, 인쇄회로기판을 사이에 두고 상하부에 솔더 볼을 매개로 패키지가 적층되는데, 이와 같은 구조의 적층형 패키지의 경우, 그 두께가 두꺼워져 현재 추세인 초소형화에 부합하지 못하는 문제점이 있다.However, in the case of such a laminated package, particularly in the case of the FBGA laminated package, the package is laminated via the solder ball on the upper and lower sides with the printed circuit board in between, the thickness of the laminated package of such a structure, the current trend is increased There is a problem that does not meet the miniaturization of phosphorus.

본 발명은 상기의 문제점을 해결하기 위하여 창출된 것으로서, 초소형화에 부합되도록 개선된 적층형 패키지를 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a laminated package that is improved to meet miniaturization.

상기의 목적을 달성하기 위한 본 발명의 적층형 패키지는, 일측에 솔더 볼이 실장된 하부 패키지; 상기 하부 패키지 상에 접착제를 매개로 적층된 상부 패키지; 상기 상부 패키지 양측단부 각각에 결합되며, 상기 상부 패키지와 전기적으로 연결된 콘택용 인쇄회로기판; 및 상기 콘택용 인쇄회로기판과 상기 하부 패키지를 전기적으로 연결하는 와이어를 포함한 것이 바람직하다.Laminated package of the present invention for achieving the above object, the lower package is mounted solder ball on one side; An upper package laminated on the lower package via an adhesive; A printed circuit board coupled to each of both ends of the upper package and electrically connected to the upper package; And a wire for electrically connecting the contact printed circuit board and the lower package.

여기서, 상기 상부 패키지와 상기 콘택용 인쇄회로기판의 전기적 연결은 서브 와이어 및 솔더 중 어느 하나에 의한 것이 바람직하다.Here, the electrical connection of the upper package and the contact printed circuit board is preferably by any one of a sub wire and a solder.

또한, 상기 서브 와이어 및 상기 솔더 중 어느 하나와, 상기 와이어는 보호막에 의하여 코팅된 것이 바람직하다.In addition, any one of the sub-wire and the solder, and the wire is preferably coated by a protective film.

또한, 상기 상부 패키지 상에는 부가 패키지가 적층되며, 상기 콘택용 인쇄회로기판과 상기 부가 패키지는 삽입 솔더 볼에 의하여 서로 전기적으로 연결된 것이 바람직하다.In addition, an additional package is stacked on the upper package, and the contact printed circuit board and the additional package are preferably electrically connected to each other by insert solder balls.

또한, 상기 상부 패키지 상에는 상기 콘택용 인쇄회로기판이 결합된 상부 패키지와 동일한 형태의 엑스트라 콘택용 인쇄회로기판이 결합된 엑스트라 패키지가 적층되며, 상기 상부 패키지와 상기 엑스트라 패키지 사이의 전기적 연결은 상기 콘택용 인쇄회로기판과 상기 엑스트라 콘택용 인쇄회로기판 사이에 삽입된 엑스트라 솔더볼에 의한 것이 바람직하다.Further, on the upper package, an extra package in which an extra contact printed circuit board of the same type as the upper package in which the contact printed circuit board is coupled is stacked, and an electrical connection between the upper package and the extra package is performed. It is preferable to use an extra solder ball inserted between the printed circuit board for the circuit and the printed circuit board for the extra contact.

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 일 실시예에 따른 적층형 패키지를 나타낸 단면도이다.1 is a cross-sectional view showing a stacked package according to an embodiment of the present invention.

도면을 참조하면, 적층형 패키지(100)는 일측에 솔더 볼(111)이 실장된 하부 패키지(110)와, 하부 패키지(110) 상에 접착제(170)에 의하여 접착된 상부 패키지(120)와, 이 상부 패키지(120) 양측단부에 접착제(135)에 의하여 결합된 콘택용 인쇄회로기판(130) 및 콘택용 인쇄회로기판(130)과 하부 패키지(110)를 전기적으로 연결하는 와이어(140)를 포함한다.Referring to the drawings, the stacked package 100 includes a lower package 110 in which solder balls 111 are mounted on one side, an upper package 120 bonded by an adhesive 170 on the lower package 110, and The contact printed circuit board 130 and the wire 140 for electrically connecting the contact printed circuit board 130 and the lower package 110 to each other end of the upper package 120 by an adhesive 135 are connected. Include.

상부 패키지(120)과 콘택용 인쇄회로기판(130)은 서브 와이어(150)나 도 2와 같이 솔더(151)에 의하여 전기적으로 연결된다. The upper package 120 and the contact printed circuit board 130 are electrically connected by the sub wire 150 or the solder 151 as shown in FIG. 2.

이때, 서브 와이어(151)에 의하여 전기적 연결을 하는 경우, 이 서브 와이어(151)를 외부로부터 보호하기 위하여 보호막(160)을 코팅한다.In this case, when the electrical connection is made by the sub wire 151, the protective film 160 is coated to protect the sub wire 151 from the outside.

그리고 콘택용 인쇄회로기판(130)과 하부 패키지(110)을 전기적으로 연결하는 와이어(140)의 경우에도 외부로부터 보호하기 위하여 보호막(160)을 코팅한다.In addition, even in the case of the wire 140 electrically connecting the printed circuit board 130 and the lower package 110 for a contact, the protective film 160 is coated to protect it from the outside.

한편, 상부 패키지(120) 상부에는 도 3과 같이 부가 패키지(180)가 더 적층될 수 있으며, 이때 부가 패키지(180)와 콘택용 인쇄회로기판(130)은 삽입 솔더 볼(181)에 의하여 상호 전기적으로 연결된다. Meanwhile, the additional package 180 may be further stacked on the upper package 120 as shown in FIG. 3, wherein the additional package 180 and the contact printed circuit board 130 are mutually connected by the insertion solder balls 181. Electrically connected.

그리고 상부 패키지(120) 상에는 도 4와 같이 콘택용 인쇄회로기판(130)이 결합된 상부 패키지(120)와 동일한 형태의 엑스트라 패키지(190)가 적층될 수 있다.An extra package 190 having the same shape as the upper package 120 to which the contact printed circuit board 130 is coupled may be stacked on the upper package 120 as shown in FIG. 4.

이 엑스트라 패키지(190)도 역시 양측단부 각각에 엑스트라 콘택용 인쇄회로기판(191)이 결합되어 있으며, 상부 패키지(120)와 엑스트라 패키지(190)의 전기적 연결은 상부 패키지(120)에 결합된 콘택용 인쇄회로기판(130)과 엑스트라 패키지(190)에 결합된 엑스트라 콘택용 인쇄회로기판(191) 사이에 삽입된 엑스트라 솔더 볼(192)에 의한다.The extra package 190 is also coupled to the printed circuit board 191 for an extra contact on each side end, and the electrical connection between the upper package 120 and the extra package 190 is a contact coupled to the upper package 120. By the extra solder ball 192 inserted between the printed circuit board 130 and the extra contact printed circuit board 191 coupled to the extra package 190.

이와 같은 구조의 적층형 패키지에 의하면, 종래 다수의 패키지 적층 시, 패키지들 사이에 인쇄회로기판을 개재하던 방식을, 적층되는 패키지 중 상부에 마련되는 패키지 양측단부 각각에 인쇄회로기판을 결합시킴으로써, 전체적인 패키지의 두께를 줄여 적층형 패키지의 초소형화에 부합할 수 있게 된다.According to the stacked package having such a structure, when a plurality of packages are stacked, a printed circuit board is interposed between packages, and the printed circuit board is coupled to each of both ends of the package provided on the upper side of the stacked packages. The thickness of the package can be reduced to meet the miniaturization of stacked packages.

상술한 바와 같이 본 발명의 적층형 패키지에 의하면, 다수의 패키지 적층 시, 인쇄회로기판을 패키지 양측단부 각각에 결합시킴으로써, 패키지 전체 두께를 줄일 수 있는 효과를 제공한다.As described above, according to the stacked package of the present invention, by stacking a plurality of packages, by coupling a printed circuit board to each of both ends of the package, an overall package thickness can be reduced.

본 발명은 상기에 설명되고 도면에 예시된 것에 의해 한정되는 것은 아니며, 다음에 기재되는 청구의 범위 내에서 더 많은 변형 및 변용예가 가능한 것임은 물론이다.It is to be understood that the invention is not limited to that described above and illustrated in the drawings, and that more modifications and variations are possible within the scope of the following claims.

Claims (5)

일측에 솔더 볼이 실장된 하부 패키지; A lower package in which solder balls are mounted at one side; 상기 하부 패키지 상에 제1 접착제를 매개로 적층된 상부 패키지; An upper package laminated on the lower package via a first adhesive; 상기 상부 패키지 양쪽 측면들로부터 각각 이격되며 상기 상부 패키지의 상면과 평행하게 배치된 콘택용 인쇄회로기판;A printed circuit board for contact spaced apart from both sides of the upper package and disposed in parallel with an upper surface of the upper package; 상기 상부 패키지 및 상기 콘택용 인쇄회로기판을 결합하는 제2 접착제; 및 A second adhesive bonding the upper package and the contact printed circuit board; And 상기 콘택용 인쇄회로기판과 상기 하부 패키지를 전기적으로 연결하는 와이어를 포함하는 것을 특징으로 하는 적층형 패키지.And a wire for electrically connecting the contact printed circuit board and the lower package. 제1항에 있어서,The method of claim 1, 상기 상부 패키지 및 상기 콘택용 인쇄회로기판의 전기적 연결은 서브 와이어 및 솔더 중 어느 하나에 의한 것을 특징으로 하는 적층형 패키지.And the electrical connection between the upper package and the contact printed circuit board is made by any one of a sub wire and a solder. 제2항에 있어서,The method of claim 2, 상기 서브 와이어 및 상기 솔더 중 어느 하나와, 상기 와이어는 보호막에 의하여 코팅된 것을 특징으로 하는 적층형 패키지.Any one of the sub wire and the solder and the wire is a laminated package, characterized in that the coating by a protective film. 제1항에 있어서,The method of claim 1, 상기 상부 패키지 상에는 부가 패키지가 적층되며, 상기 콘택용 인쇄회로기판과 상기 부가 패키지는 삽입 솔더 볼에 의하여 서로 전기적으로 연결된 것을 특 징으로 하는 적층형 패키지.An additive package is stacked on the upper package, wherein the contact printed circuit board and the additional package are electrically connected to each other by inserting solder balls. 제1항에 있어서,The method of claim 1, 상기 상부 패키지 상에는 상기 콘택용 인쇄회로기판이 결합된 상부 패키지와 동일한 형태의 엑스트라 콘택용 인쇄회로기판이 제3 접착제에 의하여 결합 된 엑스트라 패키지가 적층 되며, 상기 상부 패키지와 상기 엑스트라 패키지 사이의 전기적 연결은 상기 콘택용 인쇄회로기판과 상기 엑스트라 콘택용 인쇄회로기판 사이에 삽입된 엑스트라 솔더볼에 의한 것을 특징으로 하는 적층형 패키지.On the upper package, an extra package in which an extra contact printed circuit board of the same type as the upper package to which the contact printed circuit board is coupled is laminated by a third adhesive is laminated, and an electrical connection between the upper package and the extra package is formed. And an extra solder ball inserted between the contact printed circuit board and the extra contact printed circuit board.
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