KR100883526B1 - Top plate of wafer chuck and its manufacturing method - Google Patents
Top plate of wafer chuck and its manufacturing method Download PDFInfo
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- KR100883526B1 KR100883526B1 KR1020070008994A KR20070008994A KR100883526B1 KR 100883526 B1 KR100883526 B1 KR 100883526B1 KR 1020070008994 A KR1020070008994 A KR 1020070008994A KR 20070008994 A KR20070008994 A KR 20070008994A KR 100883526 B1 KR100883526 B1 KR 100883526B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
Abstract
본 발명은 반도체 웨이퍼용 척의 탑 플레이트 및 그 제조 방법에 관한 것으로, 탑 플레이트의 표면 혹은 이면에 금을 증착 방법을 사용하여 코팅하고, 측면에는 규소를 증착 방법으로 코팅함으로써, 두께가 얇아서 열변형이 발생되지 않도록 함과 아울러 절연저항치를 테라(T)급으로 향상시키는 반도체 웨이퍼용 척의 탑 플레이트 및 그 제조 방법을 제공하는 데 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a top plate of a semiconductor wafer chuck and a method of manufacturing the same, wherein gold is coated on the surface or the back surface of the top plate using a vapor deposition method, and silicon is coated on the side surface by a vapor deposition method, so that the heat deformation is reduced. The present invention provides a top plate of a chuck for a semiconductor wafer and a method of manufacturing the same, which prevents generation and improves an insulation resistance value to a terra (T) level.
반도체, 웨이퍼, 척, 탑 플레이트, 금, 크롬, 규소 Semiconductor, Wafer, Chuck, Top Plate, Gold, Chromium, Silicon
Description
도 1은 본 발명에 따른 반도체 웨이퍼용 척의 탑 플레이트 구조를 나타내는 단면도1 is a cross-sectional view showing a top plate structure of a chuck for a semiconductor wafer according to the present invention.
도 2는 습도변화에 따른 절연저항치를 나타내는 그래프2 is a graph showing the insulation resistance value according to the humidity change
도 3은 온도변화에 따른 평면도를 나타내는 도면3 is a plan view showing the change in temperature
도 4는 200℃에서 온도분포를 나타내는 도면4 is a diagram showing a temperature distribution at 200 ° C.
본 발명은 반도체 웨이퍼를 고정하는 척의 탑 플레이트 및 그 제조 방법에 관한 것으로, 보다 상세하게는 척의 표면과 이면 저항치를 낮추기 위하여 금을 증착 방법을 사용하여 도포하고, 측면은 절연저항치를 높이기 위하여 규소를 증착 방법을 사용하여 도포함으로써, 도포 층의 두께가 얇고 견고하도록 하여 열팽창에 의한 파손이 발생하지 않도록 함과 아울러 절연저항치가 기가(G) 단위에서 테라(T) 단위가 되도록 하는 반도체 웨이퍼용 척의 탑 플레이트 및 그 제조방법에 관한 것이다.The present invention relates to a top plate of a chuck for fixing a semiconductor wafer and a method of manufacturing the same. More particularly, gold is applied using a deposition method to lower the surface and back surface resistance of the chuck, and the side surface is formed of silicon to increase the insulation resistance. Coating using a deposition method makes the thickness of the coating layer thin and strong so that breakage due to thermal expansion does not occur, and the insulation resistance value is from giga (G) units to tera (T) units. It relates to a plate and a method of manufacturing the same.
일반적으로, 반도체 제품을 제조할 때에는 단결정 실리콘 잉곳을 얇게 슬라이스한 후, 그 표면을 연삭, 래핑, 폴리싱함으로써, 경면에 연마된 실리콘 웨이퍼를 얻을 수 있으며, 상기한 실리콘 웨이퍼는 사진공정, 박막증착공정, 이온주입공정, 식각공정 등 다수의 단위공정을 반복적으로 수행함으로써 반도체 장치인 칩(Chip)으로 제조된다.In general, in the manufacture of semiconductor products, thinly sliced single crystal silicon ingots are then ground, ground, and polished to obtain a silicon wafer polished on a mirror surface, and the silicon wafer is subjected to a photo process and a thin film deposition process. By repeatedly performing a plurality of unit processes, such as an ion implantation process and an etching process, a semiconductor device is manufactured as a chip.
이와 같이 제조된 반도체 웨이퍼는 직접회로가 집적된 후 여러 악조건하에서 반도체 수명 테스트를 거치게 되는데, 반도체 수명테스트는 보통 -50℃부터 +200℃ 사이의 온도로 제어되는 핫 앤 콜드 척 상에서 가역적으로 반복하여 수행된다.The semiconductor wafer thus manufactured is subjected to semiconductor life test under various adverse conditions after the integrated circuit is integrated. The semiconductor life test is usually reversibly repeated on a hot and cold chuck controlled at a temperature between -50 ° C and + 200 ° C. Is performed.
이와 같이 반도체 검사를 위한 웨이퍼 척은 베이스플레이트 상에 냉각유닛이 환형으로 위치되며, 그 중심에 가열유닛이 위치하게 되고, 그 상부에 탑플레이트가 캡형태로 베이스플레이트와 결합하게 된다.As described above, the wafer chuck for semiconductor inspection has an annular cooling unit positioned on the base plate, a heating unit positioned at the center thereof, and a top plate coupled to the base plate in the form of a cap.
이러한 종래 척은 냉각유닛과 가열유닛이 서로 다른 물질로 이루어지지만 동일면에 위치됨으로써 열팽창계수가 서로 달라 반도체 검사 과정에서 서로 다른 열팽창계수에 따라 탑 플레이트 표면에서 열변형이 발생하여 평탄하지 못한 표면을 갖게 되는 문제점이 있었다.In the conventional chuck, the cooling unit and the heating unit are made of different materials, but because they are positioned on the same surface, the thermal expansion coefficients are different so that thermal deformation occurs on the surface of the top plate according to different thermal expansion coefficients in the semiconductor inspection process to have an uneven surface. There was a problem.
이를 해소하기 위하여 베이스 플레이트 상에 가열유닛과 냉각유닛 및 탑 플레이트를 순차적으로 적층 시킨 척이 개발되어 사용되고 있으며, 상기한 탑 플레이트 표면에는 절연저항치를 높이기 위하여 수지를 함침 등의 방법으로 도포하여 사용하거나, 아노다이징이나 도금 등의 방법으로 니켈과 금을 순차적으로 도금하여 절연층을 형성하여 사용하고 있다.In order to solve this problem, a chuck in which a heating unit, a cooling unit, and a top plate are sequentially stacked on a base plate has been developed and used, and the resin is applied to the top plate surface by impregnation or the like to increase insulation resistance. Nickel and gold are sequentially plated by anodizing, plating, or the like to form an insulating layer.
그러나 상기한 바와 같은 함침, 아노다이징, 도금 등의 방법에 의할 경우 탑 플레이트의 외측으로 두께가 10㎛ 이내가 되는 절연층이 형성되므로, 절연층의 열팽창률이 높아 테스트 중 수지 혹은 니켈 및 금 도금으로 이루어진 절연층이 탑 플레이트 표면으로부터 박리되거나 금이 가는 문제점이 발생하였다.However, in the case of the above impregnation, anodizing, plating, etc., since an insulating layer having a thickness of less than 10 μm is formed on the outside of the top plate, the thermal expansion coefficient of the insulating layer is high, so that the resin or nickel and gold plating are under test. The insulating layer consisting of a peeling from the top plate surface or cracked problem occurred.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 탑 플레이트의 표면 혹은 이면에 금을 증착 방법을 사용하여 코팅하고, 측면에는 규소를 증착 방법으로 코팅함으로써, 두께가 얇아서 열변형이 발생하지 않도록 함과 아울러 절연저항치를 테라(T)급으로 향상시키는 반도체 웨이퍼용 척의 탑 플레이트 및 그 제조 방법을 제공하는 데 있다.The present invention is to solve the problems as described above, by coating gold on the surface or the back of the top plate using a deposition method, and by coating the silicon on the side by a deposition method, so that the thickness is thin so that no thermal deformation occurs In addition, the present invention provides a top plate of a chuck for a semiconductor wafer and a method of manufacturing the same, which improves the insulation resistance value to terra (T) grade.
상기한 목적을 달성하기 위한 본 발명의 특징은 탑 플레이트의 표면과 이면에 금을 증착 방법을 이용하여 코팅하고, 측면에는 규소를 증착 방법으로 코팅하며, 금의 접착력을 높이기 위하여 금의 증착 전에 크롬을 증착하는 반도체 웨이퍼용 척의 제조방법을 제공하여, 열 전도율과 절연저항 비율을 향상시킬 수 있도록 한 반도체 웨이퍼용 척의 탑 플레이트 및 그 제조 방법에 있다.A feature of the present invention for achieving the above object is the coating of gold on the surface and the back of the top plate by the deposition method, the side of the silicon coating by the deposition method, in order to increase the adhesion of gold chromium before the deposition of gold A semiconductor wafer chuck top plate and a method for manufacturing the same are provided by providing a method for manufacturing a semiconductor wafer chuck for depositing a film, and improving thermal conductivity and insulation resistance ratio.
상기한 특징을 갖는 본 발명의 실시 예를 하기에서 첨부된 도면을 참조하여 보다 상세하게 살펴본다.An embodiment of the present invention having the above features will be described in more detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 반도체 웨이퍼용 척의 탑 플레이트 구조를 나타내는 단면도이다.1 is a cross-sectional view showing a top plate structure of a chuck for a semiconductor wafer according to the present invention.
상기한 탑 플레이트(10)는 측면에 규소층(12)이 형성되고, 표면과 이면에는 크롬층(14)과 금층(16)이 순차적으로 형성된다.In the
이와 같은 규소층(12)과 크롬층(14) 및 금층(16)은 공지의 스퍼터링 장치를 사용하여 증착하며, 상기한 스퍼터링 장치를 통한 증착 방법은 반응성 가스가 투입된 진공 챔버 내로 전자빔을 발사하여, 발사된 전자빔이 타겟에 충돌하면서 타겟의 증발을 야기하고, 상기 타겟으로부터 증발되는 입자가 모터에 의하여 회전하는 증착 대상물에 증착되도록 하는 것으로, 상기 반응성 가스로는 산소, 질소가 주로 사용 사용된다.The
규소 증착Silicon deposition
탑 플레이트의 측면에 규소를 증착하는 경우를 살펴본다.Consider the case of depositing silicon on the side of the top plate.
이를 위하여 우선 탑 플레이트의 증착 면인 측면을 제외한 면은 종이 등을 사용하여 마스킹을 수행한다.For this purpose, masking is first performed using a paper or the like except for the side surface of the top plate.
이후, 측면에 규소를 증착하기 위해서 스퍼터링 장치의 진공챔버 내의 진공압력을 2~10×10-5Torr(바람직하게는 5.0×10-5Torr), 타겟물질로는 규소(Si)를 사용하며, 반응성 가스로는 아르곤(Ar) 400-500sccm(바람직하게는 470sccm)과 산소 20-100sccm(바람직하게는 50sccm)를 혼합사용하고, 탑 플레이트를 회전시키는 회전모터의 회전수는 20-50rpm(바람직하게는 30rpm)으로 하여 20-40분(바람직하게는 30분) 동안 증착한다.Then, in order to deposit silicon on the side, the vacuum pressure in the vacuum chamber of the sputtering apparatus is 2 to 10 x 10 -5 Torr (preferably 5.0 x 10 -5 Torr), and silicon (Si) is used as the target material. As the reactive gas, argon (Ar) 400-500 sccm (preferably 470 sccm) and oxygen 20-100 sccm (preferably 50 sccm) are mixed and the rotational speed of the rotating motor for rotating the top plate is 20-50 rpm (preferably 30 rpm) for 20-40 minutes (preferably 30 minutes).
크롬과 금 증착Chrome and gold deposition
탑 플레이트의 표면과 이면에 크롬과 금을 증착하는 경우를 살펴본다.Consider the deposition of chromium and gold on the top and back of the top plate.
이 과정에서도 상기한 실시예 1에서와 같이 증착면을 제외한 면은 종이 등으로 마스킹을 수행한다.In this process, as in Example 1, the surface except for the deposition surface is masked with paper or the like.
이와 같이 마스킹을 수행한 탑 플레이트를 진공챔버 내부에 위치시키고, 크롬을 증착하기 위해서 스퍼터링 장치의 진공챔버 내의 진공압력을 2~10×10-5Torr(바람직하게는 5.0×10-5Torr), 타겟물질로는 크롬(Cr)을 사용하며, 반응성 가스로는 아르곤(Ar) 200-400sccm(바람직하게는 300sccm)을 사용하고, 탑 플레이트를 회전시키는 회전모터의 회전수는 2-10rpm(바람직하게는 5rpm)으로 하여 25-45분(바람직하게는 35분) 동안 증착한다.The masked top plate is placed in the vacuum chamber, and the vacuum pressure in the vacuum chamber of the sputtering apparatus is set to 2 to 10 x 10 -5 Torr (preferably 5.0 x 10 -5 Torr) to deposit chromium. As the target material, chromium (Cr) is used, and as the reactive gas, argon (Ar) 200-400sccm (preferably 300sccm) is used, and the rotation speed of the rotating motor for rotating the top plate is 2-10rpm (preferably 5 rpm) for 25-45 minutes (preferably 35 minutes).
그리고 금을 증착하기 위해서는 동일한 방법으로 마스킹된 탑 플레이트를 진공챔버 내부에 위치시키고, 진공챔버 내의 진공압력을 2~10×10-5Torr(바람직하게는 5.0×10-5Torr), 타겟물질로는 금을 사용하며, 반응성 가스로는 아르곤 200-300sccm(바람직하게는 260sccm)을 사용하며, 탑 플레이트를 회전시키는 회전모터의 회전수는 2-10rpm(바람직하게는 5rpm)으로 하여 30-50분(바람직하게는 40분)동안 증착한다.In order to deposit the gold, the masked top plate was placed in the vacuum chamber in the same manner, and the vacuum pressure in the vacuum chamber was set to 2 to 10 × 10 -5 Torr (preferably 5.0 × 10 -5 Torr) as a target material. Silver is used, and 200-300 sccm (preferably 260 sccm) of argon is used as a reactive gas, and the rotation speed of the rotating motor for rotating the top plate is 2-10 rpm (preferably 5 rpm) for 30-50 minutes ( Preferably 40 minutes).
상기한 과정에서, 크롬은 금의 접착력을 향상시키기 위한 것으로 탑 플레이 트 표면에 크롬을 먼저 증착한 후 금을 증착한다.In the above process, chromium is to improve the adhesion of gold to deposit the chromium on the surface of the top plate first and then deposit the gold.
이상과 같이 형성된 본 발명에 따른 척의 누설전류, 노이즈전류, 평면도, 온도분포 및 절연저항과 온도와의 관계를 하기에서 살펴본다.The relationship between the leakage current, the noise current, the plan view, the temperature distribution, the insulation resistance and the temperature of the chuck according to the present invention formed as described above will be described below.
우선, 상기한 방법으로 제조된 탑 플레이트를 이용하여 척을 조립한 후, 전류 200pA에 ，DC 10０Ｖ의 전원을 인가하고, 습도 50% 이상의 실내에서 상온 22-25℃, 85℃, 150℃에서 각각 절연저항치를 측정한 결과 상온에서는 250TΩ, 85℃에서는 200TΩ, 150℃에서는 27TΩ의 절연저항치를 보였다.First, after assembling the chuck using the top plate manufactured by the method described above, apply a power of DC 100 Ｖ to a current of 200pA, and at room temperature 22-25 ℃, 85 ℃, 150 ℃ respectively at a humidity of 50% or more As a result of measuring insulation resistance, insulation resistance of 250TΩ at room temperature, 200TΩ at 85 ℃ and 27TΩ at 150 ℃ was shown.
그리고 온도 25℃, 습도 70%에서도 도 2에 나타내는 바와 같이 40TΩ이상의 높은 절연저항치를 보였다.And as shown in FIG. 2, even at the temperature of 25 degreeC, and 70% of humidity, the high insulation resistance value of 40T (ohm) or more was shown.
적분 시간：5PLC，전류１nA와 DC 10V의 전압을 인가하여，상온과 150℃에서 탑 플레이트가 갖는 시간당 누설전류를 측정하였으며, 그 결과는 표 1에 나타낸다.Integral time: 5PLC, current 1nA and a DC 10V voltage were applied, and the leakage current per hour of the top plate was measured at room temperature and 150 ° C. The results are shown in Table 1.
그리고 적분 시간：20PLC，전류 100pA에 ，DC ０Ｖ의 전압을 인가하여，탑 플레이트가 갖는 노이즈 전류를 상온과 150℃에서 측정한 결과, 상온에서 1.23*10-14Ω, 150℃에서 1.52*10-14Ω의 노이즈전류가 측정되었다.Integral time: 20PLC, applying a voltage of DC 0Ｖ to a current of 100pA, and measuring the noise current of the top plate at room temperature and 150 ℃, 1.23 * 10 -14 Ω at room temperature, 1.52 * 10 - at 150 ℃ A noise current of 14 Ω was measured.
그리고 상온과 150℃ 및 다시 상온으로 낮추었을 경우 평면도는 도 3에 나타내는 바와 같이 3.1-5.6㎛를 나타내며, 200℃에서 온도분포(R)는 도 4에 나타내는 바와 같이 2.6℃이다.When the temperature is lowered to room temperature and 150 ° C and again to room temperature, the plan view shows 3.1-5.6 μm as shown in FIG. 3, and the temperature distribution R at 200 ° C. is 2.6 ° C. as shown in FIG. 4.
상기한 바와 같은 본 발명은 규소가 절연저항치를 높이고 금이 저항치를 낮춤으로 인하여 절연저항치가 기가(G) 단위에서 테라(T) 단위로 높아지고, 증착된 절연층이 0.1-1㎛ 정도로 매우 얇아서 열팽창 시에 금이 가거나 탑 플레이트로부터 이탈되지 않아서 수명이 오래가는 효과가 있다.In the present invention as described above, since the silicon increases the insulation resistance and the gold decreases the insulation resistance, the insulation resistance increases from Giga (G) to tera (T), and the deposited insulation layer is very thin, such as 0.1-1 μm, so that the thermal expansion It does not crack or detach from the top plate, which has the effect of long life.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070008994A KR100883526B1 (en) | 2007-01-29 | 2007-01-29 | Top plate of wafer chuck and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020070008994A KR100883526B1 (en) | 2007-01-29 | 2007-01-29 | Top plate of wafer chuck and its manufacturing method |
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| KR100883526B1 true KR100883526B1 (en) | 2009-02-12 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5703493A (en) | 1995-10-25 | 1997-12-30 | Motorola, Inc. | Wafer holder for semiconductor applications |
| KR20030014724A (en) * | 2000-06-23 | 2003-02-19 | 허니웰 인터내셔날 인코포레이티드 | Vacuum chuck with integrated electrical testing points |
-
2007
- 2007-01-29 KR KR1020070008994A patent/KR100883526B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5703493A (en) | 1995-10-25 | 1997-12-30 | Motorola, Inc. | Wafer holder for semiconductor applications |
| KR20030014724A (en) * | 2000-06-23 | 2003-02-19 | 허니웰 인터내셔날 인코포레이티드 | Vacuum chuck with integrated electrical testing points |
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| KR20070063477A (en) | 2007-06-19 |
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