KR100873622B1 - Bulk voltage generator and semiconductor memory device having the same - Google Patents

Abstract

A bulk voltage generator and semiconductor memory device having the same is provided to control threshold voltage easily in writing operation and improve a tWR property by using a bulk reference voltage for writing operation. In a bulk voltage generator and semiconductor memory device, a bank includes a bulk voltage generation circuit supplies a bulk reference voltage according to the activation whether or not of the write command signal. A plurality of mat blocks includes a mat array(300) where a P-well(330) is divided completely by an N-well(320). The bulk reference voltage generation unit supplies a first and second reference voltage selectively in response to activation of the writing command signal. A level shifter receives the first and second reference voltage and boosts them to supplies the bulk reference voltage.

Description

Bulk voltage generator circuit and semiconductor memory device comprising same

1 is a block diagram of a bulk voltage generation circuit according to an embodiment of the present invention;

2A is a block diagram of a bulk reference voltage generator according to FIG. 1;

2B is a circuit diagram of a bulk reference voltage generator according to FIG. 2A;

3 is a circuit diagram of a pump signal generator according to FIG. 1, and

4 is a block diagram of a mat in which N wells are separated by a P well according to another embodiment of the present invention, and

FIG. 5 is a conceptual block diagram of a semiconductor memory device including FIG. 4.

<Explanation of symbols for the main parts of the drawings>

100: bulk reference voltage generation unit 150: bulk voltage providing unit

160: comparison unit 170: output unit

180: level shifter 200: pump signal generation unit

The present invention relates to a bulk voltage generation circuit, and more particularly, to a bulk voltage generation circuit for improving write operation characteristics and a semiconductor memory device including the same.

In general, semiconductor memory devices use internal voltages of various potential levels. For example, the bit line precharge voltage VBLP, the boost voltage VPP, the bulk voltage (hereinafter referred to as "VBB"), and the like.

In particular, the bulk voltage VBB is a voltage applied to the bulk of the semiconductor substrate and has a negative voltage level lower than the ground voltage VSS. As a result, a difference between the bulk voltage of the substrate (well voltage of the cell transistor) and the source voltage of the cell transistor occurs. Due to this difference, a body effect phenomenon, the threshold voltage of the cell transistor is increased. Therefore, the leakage current is reduced by increasing the threshold voltage of the cell transistor, the data retention time is increased, and the refresh characteristic can be improved.

On the other hand, tWR (Write Recovery Time) is a write recovery time, which means the time from the last data write to the cell transistor to precharge. However, when data is written to the memory cell, the write operation becomes difficult due to the raised threshold voltage, thereby degrading the tWR characteristic.

An object of the present invention is to provide a semiconductor memory device for improving the write operation characteristics.

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In order to achieve the above technical problem, a semiconductor memory device is disposed in a bank including a bulk voltage generation circuit that provides a bulk reference voltage having a different output level according to whether a write command signal is activated. And a plurality of mat blocks including a mat array in which P wells are completely separated by N wells, and a bulk voltage supply pump is provided to supply the bulk voltage to each mat block.
Bulk voltage supply pumps are arranged at all four edges of the bank. In addition, a high voltage obtained by boosting an external voltage is applied to the N well, and a bulk voltage is applied to the P well.

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Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

According to embodiments of the present invention, the tWR characteristic may be improved by varying the bulk voltage during the write operation. That is, by changing the bulk voltage according to whether the write command signal is activated, the threshold voltage may be controlled to be lowered during the write operation. By using the bulk reference voltage for the write operation, it is possible to improve the tWR characteristic by simply controlling the threshold voltage during the write operation.

Such a bulk voltage generation circuit will be described in more detail.

Referring to FIG. 1, the bulk voltage generation circuit includes a bulk reference voltage generator 100 and a pump signal generator 200.

The bulk reference voltage generator 100 according to an embodiment of the present invention receives the write command signal WT and the first reference voltage VREF1 or the second reference voltage VREF2 to provide the bulk reference voltage VBB_ref. do. The bulk reference voltage generator 100 uses the first reference voltage VREF1 or the second reference voltage VREF2 to vary the threshold voltage of the memory cell transistor during the write operation.

The pump signal generator 200 provides a bulk voltage pump signal VBB_ENB using the bulk reference voltage VBB_ref according to the sensed bulk voltage VBB. That is, the pump signal generator 200 detects the bulk voltage VBB to determine whether to pump the bulk voltage VBB.

Referring to FIG. 2A, the bulk reference voltage generator 100 includes a bulk voltage provider 150 and a level shifter 180.

First, the bulk voltage provider 150 selects the first reference voltage VREF1 or the second reference voltage VREF2 as the input signal A of the level shifter 180 according to whether the write command signal WT is activated. To provide. The write command signal WT is a signal provided at a high level activated during a write operation.

The level shifter 180 includes a comparator 160 and an output unit 170.

In more detail, the comparator 160 receives a voltage signal (not shown) distributed by the first reference voltage VREF1 or the second reference voltage VREF2 and the resistance ratio, which are selectively provided, and compares the comparison signal ( Provide B).

Thus, the output unit 170 receives the comparison signal B and provides the bulk reference voltage VBB_ref raised to a predetermined level. That is, the output unit 170 provides the bulk reference voltage VBB_ref shifted by a predetermined level than the respective reception level in response to the received first or second reference voltage VREF1 or VREF2.

This will be described in more detail with reference to FIG. 2B.

In detail, the bulk voltage providing unit 150 includes a transmitting unit 151. The transmitter 151 includes a first transmission gate T1 and a second transmission gate T2. The first transfer gate T1 and the second transfer gate T2 are selectively turned on depending on whether the write command signal WT is activated. When the first transfer gate T1 is turned on, the first reference voltage VREF1 is provided. When the second transfer gate T2 is turned on, the second reference voltage VREF2 is provided.

The comparator 160 includes a controller 161, a receiver 162, and a current mirror unit 163. Here, the comparison unit 160 illustrates a current mirror type differential amplifier, but is not limited thereto.

The controller 161 includes a first NMOS transistor N1 that receives an activation signal EN. When the activated high level activation signal EN is received, the first NMOS N1 is turned on. The receiver 162 includes a second NMOS transistor N2 and a third NMOS transistor N3. The second NMOS transistor N2 receives the signal A provided from the reference voltage providing unit 150, and the third NMOS transistor N3 receives the signal of the node f. The current mirror unit 163 mirrors the difference in the current driven by the receiver 162. The current mirror unit 163 includes first and second PMOS transistors P1 and P2 having respective gates connected to the node d. A source voltage VDD is connected to the sources of the first and second PMOSs P1 and P2, and a drain thereof is connected to the drains of the second and third NMOS transistors N2 and N3, respectively.

The output unit 170 includes a third PMOS transistor P3 and a voltage divider 171. The third PMOS transistor P3 includes a gate that receives the comparison signal B, a source connected to the power supply voltage VDD, and a drain connected to the node e. In particular, the voltage distributor 171 includes diode-connected fourth and fifth NMOS transistors N4 and N5. Here, the fourth and fifth NMOS transistors N4 and N5 are exemplified as being provided with transistors of the same size. Therefore, the voltage divided by the resistance ratios of the fourth and fifth NMOS transistors N4 and N5 is provided to the node f.

Subsequently, an operation of the bulk reference voltage provider 100 according to an exemplary embodiment of the present invention will be described with reference to FIG. 2B.

The case where the write operation is not performed will be described first.

When the low level write command signal WT is received, the node a is provided with the low level, and the node b is provided with the high level inverted by the inverter INV1. Accordingly, the first reference gate VREF1 is provided as the selected reference voltage A by turning on the first transfer gate T1. Here, the absolute value of the first reference voltage VREF1 is greater than the absolute value of the second reference voltage VREF2.

The second NMOS transistor N2 receives the first reference voltage VREF1. Here, the first reference voltage VREF1 may be 0.8V, for example. Thus, the gate-to-gate voltage V _{GS of} the second NMOS transistor N2 becomes equal to or greater than the threshold voltage Vt and the second NMOS transistor N2 is turned on. Thus, the level of node c becomes lightly low level. Thus, the third PMOS transistor P3 is finely turned on so that the output unit 170 may provide a current path to the ground voltage VSS. In this case, the voltage of the node e may be determined by the voltage divider 171.

In more detail, since the fourth and fifth NMOS transistors N4 and N5 of the voltage divider 171 are diode-connected, they may serve as active resistors. The voltages distributed by the fourth and fifth NMOS transistors N4 and N5 are provided to the third NMOS transistor N3. According to the differential amplifier operation of the comparator 160, the level received at the gate of the node f, that is, the third NMOS transistor N3, will correspond to the level received at the gate of the second NMOS transistor N2. In other words, the voltage of the node f corresponds to the first reference voltage VREF1, which is a voltage divided by the fourth and fifth NMOS transistors N4 and N5. As described above, the fourth and fifth NMOS transistors N4 and N5 are equally sized transistors and are diode connected. Therefore, the sum of the voltages across the fourth and fifth NMOS transistors N4 and N5 is provided to the node e. Thus, the node e will be provided with a signal having a double first reference voltage VREF1. That is, when not in the write operation, the bulk reference voltage VBB_ref may provide a voltage signal that is twice the voltage of the boosted level, that is, the first reference voltage VREF1, based on the first reference voltage VREF1. However, in order to detect a desired bulk reference voltage VBB_ref according to the circuit configuration, the configuration or number of transistors of the voltage divider 171 may vary.

Next, a case of a write operation will be described.

When the write command signal WT having the high level activated during the write operation is received, the node a is provided with the high level, and the node b is provided with the low level inverted by the inverter INV1. Accordingly, by turning on the second transfer gate T2, the second reference voltage VREF2 is provided to the comparator 160 as the selected reference voltage A. FIG. Here, the absolute value of the second reference voltage VREF2 is smaller than the absolute value of the first reference voltage VREF1. For example, it may be 0.6V. That is, during the write operation, the second reference voltage VREF2 smaller is used.

The lower signal, that is, the second reference voltage VREF2, is received by the second NMOS transistor N2. On the other hand, the opposite third NMOS transistor N3 will be provided with the first reference voltage VREF1 which is the previous signal. Accordingly, the third NMOS N3 is turned on in accordance with the operation of the comparator 160, so that the node d is at a low level. Thus, by turning on the first PMOS transistor P1, the node c is provided with a high level. As a result, the third PMOS transistor P3 is turned off. Since the supply power is cut off, node f will eventually go down until the level corresponding to the second NMOS transistor N2 is reached. Thus, as described above, the level of the node f received at the gate of the third NMOS transistor N3 according to the differential amplifier operation of the comparator 160 may be a level corresponding to the second reference voltage VREF2.

Subsequently, the comparator 160 continuously compares the levels received by the second and third NMOS transistors N2 and N3. Accordingly, node e is provided with a second second reference voltage VREF2. As a result, a signal having a lower level than that of the normal case is provided by using the second reference voltage VREF2 in which the bulk reference voltage VBB_ref is smaller during the write operation.

In the conventional case, there is always a constant bulk reference voltage. However, according to an embodiment of the present invention, the threshold voltage of the cell transistor may be lowered by providing a lower reference voltage as the bulk reference voltage VBB_ref during the write operation. That is, by providing a bulk reference voltage that varies depending on whether the write command signal is activated, the data write operation can be made easier for the cell transistor during the write operation. As a result, the tWR characteristic can be improved.

Referring to FIG. 3, the pump signal generator 200 using the bulk reference voltage VBB_ref is illustrated.

The pump signal generator 200 uses the bulk reference voltage VBB_ref according to the sensed bulk voltage VBB. The pump signal generator 200 includes a detector 210 and a pump signal determiner 220.

First, the detector 210 includes a first PMOS transistor PM1 and a second PMOS transistor PM2. The first PMOS transistor PM1 includes a gate that receives the ground voltage VSS, a source connected to the bulk reference voltage VBB_ref, and a drain connected to the node g. The second PMOS transistor PM2 includes a gate receiving the bulk voltage VBB, a source connected to the ground voltage VSS, and a drain connected to the node g. Thus, the detector 210 detects whether the detected bulk voltage VBB is higher or lower than the first or second reference voltages VREF1 and VREF2 that are target voltages. Here, the node g of the detector 210 may be provided with the first or second reference voltages VREF1 and VREF2 initially, and the first and second PMOS transistors PM1 and PM2 designed to satisfy the example may be illustrated. do.

The pump signal determiner 220 provides the bulk voltage pump signal VBB_ENB according to the signal level of the detection signal det. The pump signal determiner 220 includes a third PMOS transistor PM3 and a first NMOS transistor NM1. The third PMOS transistor PM3 and the first NMOS transistor NM1 may be selectively turned on according to the level of the received detection signal det.

Subsequently, the operation of the pump signal generator 200 will be described.

The detector 210 may provide a current path through the second PMOS transistor PM2 by turning on the first PMOS transistor PM1 that receives the ground voltage VSS. Thus, the analog g is provided to the node g by the effective resistance of the second PMOS transistor PM2 receiving the bulk voltage VBB. Here, the bulk voltage VBB may be the bulk voltage VBB sensed at the bulk voltage node.

In detail, the detector 210 provides the level of the detection signal det by the difference between the effective resistance values of the first and second PMOS transistors PM1 and PM2. Since the first PMOS transistor PM1 receives the ground voltage VSS, the effective resistance is almost constant. Accordingly, the detection signal det is determined by the effective resistance of the second PMOS transistor PM2 that receives the sensed bulk voltage VBB. For example, if the level of the sensed bulk voltage VBB is lower than the target voltage (first or second reference voltage), that is, the absolute value of the sensed bulk voltage VBB is small, the second PMOS transistor. The effective resistance of PM2 is increased. As a result, the level of the detection signal det detected analogically is increased slightly than the level initially set. As a result, the first NMOS transistor NM1 of the pump signal determiner 220 is turned on. Thus, the bulk voltage pump signal VBB_ENB is provided at an activated low level. That is, since the detected bulk voltage VBB is lower than the reference voltage (first or second reference voltage) of the target level, the pumping operation is determined. Thus, providing an activated bulk voltage pump signal VBB_ENB.

On the other hand, when the sensed bulk voltage VBB is higher than the reference voltage (first or second reference voltage) of the target level, the effective resistance of the second PMOS transistor PM2 is lowered. Thus, node g is at an analog low level. Accordingly, the third PMOS transistor PM3 is turned on by the low level detection signal det to provide the high level inactive bulk voltage pump signal VBB_ENB. That is, when the sensed bulk voltage VBB is higher than the first or second reference voltages VREF1 and VREF2, the bulk voltage pump signal VBB_ENB is deactivated to stop the pumping.

Another embodiment of the present invention will be described with reference to FIGS. 4 to 5. 4 is a block diagram illustrating a well structure in the mat 300. 5 is a block diagram illustrating a semiconductor memory device 500 including the mat 300.

The plurality of cell mat arrays 300 arranged in a matrix form includes a deep N well 310, an N well 320, and a P well 330.

According to an embodiment of the present invention, the P well 330 is completely separated by the N well 320. That is, the P wells 330 to which the bulk voltage VBB is applied in the mat 300 are divided into predetermined units so as not to be connected to one. Thus, in the mat 300 provided with the bulk voltage generation circuit according to an embodiment of the present invention, the effect of the change of the bulk reference voltage VBB_ref is increased.

In other words, when the P well 330 is partitioned into blocks by the N well 320, the well capacitor of the P well 330 itself may be reduced. That is, by partitioning the size of the P well 330, the effect of the bulk reference voltage VBB_ref that is changed in circuit can be increased. The boosted high voltage VPP is applied to the N well 320. In addition, a bulk voltage VBB is applied to the P well 330.

The semiconductor memory device 500 may include a plurality of banks 400 (BANKs), and the banks 110 may include mats 300. In this case, the plurality of mats may be arranged at predetermined intervals, and a row decoder XDEC and a column decoder YDEC are positioned between the mats.

According to one embodiment of the present invention, a bulk voltage supply pump 410 is disposed at all four edges of each bank 400. That is, a bulk voltage supply pump 410 is provided for supplying the bulk voltage VBB to each mat block. As a result, one bulk voltage supply pump 410 may supply the bulk voltage VBB to the partitioned unit mat Mat. That is, in the embodiment of the present invention, the P well 330 is partitioned into Mat units to supply the bulk voltage VBB which is a bias of the P well 330 per mat. By partitioning and separating the P wells 330 as described above, the well capacitors of the P wells 330 may be reduced to increase the influence of the changed bulk reference voltage VBB_ref.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. Do.

As described in detail above, according to embodiments of the present invention, the tWR characteristic may be improved by varying the bulk voltage during the write operation. That is, by changing the bulk voltage according to whether the write command signal is activated, the threshold voltage may be controlled to be lowered during the write operation. By using the bulk reference voltage for the write operation, it is possible to improve the tWR characteristic by simply controlling the threshold voltage during the write operation.

Claims (18)

delete delete delete delete delete delete delete delete delete A bank including a bulk voltage generation circuit configured to provide a bulk reference voltage having a different output level according to whether the write command signal is activated; And A plurality of mat blocks disposed in the bank and comprising a mat array in which the P wells are completely separated by N wells,  And a bulk voltage supply pump for supplying the bulk voltage to each mat block. delete The method of claim 10, And the bulk voltage supply pump is disposed at all four edges of the bank. The method of claim 10, And applying a high voltage boosted to an external voltage to the N well. The method of claim 10, And applying the bulk voltage to the P well. The method of claim 10, The bulk voltage generation circuit, A bulk reference voltage generator configured to receive the write command signal and a first reference voltage or a second reference voltage to provide the bulk reference voltage; And And a pump signal generator configured to provide a bulk voltage pump signal using the bulk reference voltage according to the sensed bulk voltage. The method of claim 15, The bulk reference voltage generator, A reference voltage providing unit selectively providing the first reference voltage or the second reference voltage according to whether the write command signal is activated; And And a level shifter receiving the first reference voltage or the second reference voltage and boosting the received first or second reference voltage to provide the bulk reference voltage. The method of claim 16, The reference voltage providing unit provides the first reference voltage when the write command signal is inactivated. The method of claim 16, The reference voltage providing unit provides the second reference voltage when the write command signal is activated.

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