KR100872130B1 - Method for forming through interconnection and manufacturing printed circuit board - Google Patents

Abstract

A method for forming a penetration electrode and a method for manufacturing a printed circuit board are provided to improve electrical characteristic by forming the penetration electrode with densely filled conductive material without a void or a seam. A penetration hole(13) consisting of a small hole(14) to face from one side to other side and a large hole(16) of which cross section is enlarged in one end of the small hole, is formed in a substrate(12). The conductive material is filled in the small hole. The large hole is removed. The other surface of the substrate is ground and planed to expose the conductive material. The substrate is ceramic or silicon wafer.

Description

Method for forming through interconnection and manufacturing printed circuit board

The present invention relates to a method of forming a through electrode and a method of manufacturing a printed circuit board.

With the development of the electronics industry, portable electronic products such as mobile phones and DMB (Digital Multimedia Broadcasting) are becoming smaller and more functional. Accordingly, electronic components are also required to be miniaturized, highly integrated, multifunctional, and high performance. One of the key technologies that enables this product development goal is package assembly technology.

Chip-scale package as a package assembly technology is a new type of package that has been recently developed and proposed, and has the advantage of greatly reducing the size of a package compared to a typical plastic package.

Chip-scale packages are mainly used in products requiring miniaturization and mobility, such as digital camcorders, mobile phones, notebook computers, memory cards, and so on, and include digital signal processors (DSPs), application specific integrated circuits (ASICs), and microcontrollers (microcontrollers). Semiconductor devices such as controllers are mounted in chip-scale packages. In addition, the use of chip-scale packages in which memory devices such as dynamic random access memory (DRAM), flash memory, and the like are mounted is increasingly being used.

However, while the chip scale package has an absolute advantage in terms of size, it is difficult to secure reliability and additional manufacturing equipment is required for the manufacture of the chip scale package. There is a downside to falling.

In order to solve this problem, chip-scale packages are emerging at the wafer level. In a typical wafer fabrication process, when a semiconductor wafer is manufactured, individual chips are separated from the wafer and subjected to a package assembly process. This package assembly process is completely separate from the wafer fabrication process and requires different equipment and raw materials. However, it is possible to produce a package as a complete product at the wafer level, i.e. without separating individual chips from the wafer. Therefore, the existing wafer manufacturing equipment and processes can be used as it is in the manufacturing equipment or manufacturing process used to manufacture the package. This also means that it is possible to minimize the additional raw materials required to manufacture the package. In addition, a stack package in which a chip scale package manufactured at the wafer level is stacked in three dimensions is also emerging.

On the other hand, as the semiconductor chip becomes more sophisticated and highly integrated, the number of I / Os of the semiconductor chip increases, so that the number of pads of the package substrate on which the semiconductor chip is mounted increases, thereby requiring fine pitch of the package substrate. Since the fine pitch of the package substrate increases the manufacturing cost of the substrate, the fine pitch of the package substrate is overcome by interposing an interposer substrate between the semiconductor chip and the package substrate.

However, the interposer substrate on which the semiconductor chip is mounted is still required to have fine pitch, and accordingly, the through electrode for electrical conduction between the upper and lower sides of the interposer substrate is also required to be refined.

1 is a flowchart illustrating a method of forming a through electrode according to the prior art. In order to form a fine through electrode 106 on the substrate 102 according to the prior art, first, a small aperture through hole is drilled through the substrate 102 and a conductive material is filled into the through hole by plating. In this case, as shown in FIG. 1, the through-electrode 106 is formed by performing a planarization process of polishing the surface of the overfilled substrate by performing plating to overfill the through-hole.

However, the method of forming the through electrode according to the related art has a problem in that the through hole has a small diameter and the thickness of the plate is large, so that the plating solution does not penetrate the through hole so that the filling rate of the through hole is low and the electrical characteristics are not good.

In addition, in order to stack the chip scale packages manufactured at the wafer level in three dimensions, a through electrode is required between the chip scale packages disposed up and down. The through holes required to stack the chip scale packages in three dimensions at the wafer level are semiconductor chips. As the aspect ratio is very large compared to the printed circuit board (PCB) due to the high density and high density of the PCB, it is very difficult to fill the through electrode without voids or cracks in the through hole.

On the other hand, the interposer substrate is interposed between the semiconductor chip and the package substrate to electrically connect the semiconductor chip and the package substrate, there is a problem that the height of the entire package is increased.

The present invention provides a through electrode forming method and a printed circuit board manufacturing method capable of forming a through electrode filled with a conductive material more tightly without voids or cracks, and reducing the overall height of the package substrate. To provide.

According to one aspect of the invention, providing a substrate formed with a through hole consisting of a small hole formed from one side toward the other surface, and a large hole in which the cross section is enlarged at one end of the small hole, filling the small hole with a conductive material And polishing and planarizing the other surface of the substrate to expose the conductive material.

The substrate may be either ceramic or silicon wafer.

The filling may include depositing a seed layer on one surface of the substrate and electroplating the seed layer with an electrode. In addition, the filling may include filling to overfill one end of the small hole.

According to another aspect of the present invention, there is provided a substrate having a through-hole formed of a small hole formed from one side toward the other surface and a large hole having an enlarged cross section at one end of the small hole, wherein the small hole is filled with a conductive material. A method of manufacturing a printed circuit board is provided, the method including forming a first circuit pattern on one surface of a substrate and polishing and planarizing the other surface of the substrate to expose a conductive material.

After the forming of the first circuit pattern, the buildup layer may further include stacking a buildup layer on one surface of the substrate, and forming a via and a second circuit pattern electrically connected to the first circuit pattern on the buildup layer. have. In this case, a plurality of buildup layers may be stacked, and vias and second circuit patterns may be formed in the plurality of buildup layers, respectively.

After the build-up step, the method may further include forming a conductive bump formed on the surface of the build-up layer and electrically connected to the second circuit pattern.

The step of planarization may be performed after the step of forming the conductive bumps.

After the planarizing, the method may further include forming a conductive bump formed on the other surface of the substrate and electrically connected to the conductive material.

The filling may include depositing a seed layer on one surface of the substrate and electroplating the seed layer with an electrode. Also, the filling may include filling the small hole to over filling.

The substrate may be either ceramic or silicon wafer.

The through-electrode forming method and the printed circuit board manufacturing method according to the present invention can improve the electrical properties by forming a through-electrode filled with a conductive material more tightly without voids or cracks. Small depth can shorten the process time for filling. In addition, the overall height of the package can be lowered by reducing the height of the substrate through the planarization process.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, an embodiment of a method of forming a through electrode and a method of manufacturing a printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings. In the following description with reference to the accompanying drawings, the same or corresponding components are the same reference numerals. And duplicate description thereof will be omitted.

2 is a flowchart illustrating a through electrode forming method according to an embodiment of the present invention. Referring to FIG. 2, a substrate 12, a small hole 14, a large hole 16, a through hole 13, a seed layer 18, a conductive material 20, and a through electrode 21 are illustrated. .

According to the present embodiment, the substrate 12 having the through-hole 13 formed of a small hole 14 formed from one surface thereof toward the other surface and a large hole 16 having an enlarged cross section at one end of the small hole 14 is formed. Providing a small hole 14 with the conductive material 20 and polishing and planarizing the other surface of the substrate 12 to expose the conductive material 20. By forming the more tightly charged through electrode 21, the electrical characteristics can be improved, and the filling depth can be shortened, thereby shortening the processing time for charging. It is also possible to reduce the overall height of the package substrate.

In the through-electrode formation method according to the present embodiment, first, as shown in (a) of FIG. 2, a small hole 14 is formed from one surface to the other surface and an end surface of the small hole 14 is enlarged. It provides a substrate 12 in which a through hole 13 consisting of a large hole 16 is formed.

In the drilling of the through-holes for forming the through-electrode 21, the small hole 14 formed from one surface of the substrate 12 toward the other surface, and the large hole whose cross section is enlarged at one end of the small hole 14 ( A through hole 13 having a two-stage structure composed of 16 is formed. That is, by providing the through holes 13 having a two-stage structure, only the small holes 14 are filled with the conductive material 20, so that the filling depth can be lowered, making the filling more compact, and the filling process time can be shortened. .

In particular, since the aspect ratio of the through-holes for forming the through-electrode 21 is very large in the manufacture of a wafer-level chip package substrate, the filling rate of the through-holes decreases, and voids or cracks are formed even when the through-holes 21 are filled. A seam may occur. Therefore, the through hole 13 having a two-stage structure is formed so that only the small hole 14 is filled, thereby making the filling more compact. That is, since the aspect ratio of the small hole 14 is small, a filling rate can be raised. Here, an aspect ratio means a value obtained by dividing the depth of the through hole by the diameter of the through hole.

In addition, in the case of the interposer substrate for the electrical connection between the semiconductor chip and the package substrate, the fine pitch of the circuit pattern is required to increase the aspect ratio of the through electrode 21. If the through electrode 21 is formed by using the 13), the through electrode 21 may be more closely charged. In addition, since the overall height of the package may be increased by the interposer substrate, the overall height of the package may be lowered by lowering the thickness of the interposer substrate by the planarization process described later.

The substrate 12 of the present embodiment may be either ceramic or silicon wafer. In addition, high-resistance silicon wafers, polycrystalline silicon, glass, PCB substrates, and the like may be used.

Next, the small holes 14 are filled with the conductive material 20. As a method of filling the small holes 14, a method of filling by electroless / electroplating, a method of filling a conductive paste, a method of filling a conductive ink by inkjet printing, a method of polymerizing and filling a conductive polymer, or the like can be used. have.

In this embodiment, a method of filling the small hole 14 with the conductive material 20 by electroplating is disclosed. That is, as shown in FIG. 2B, the seed layer 18 is deposited on one surface of the substrate 12. When the seed layer 18 is deposited, as shown in (c) of FIG. 2, the small hole 14 is filled by electroplating the seed layer 18 with an electrode. In this case, plating may be overfilled at one end of the small hole 14 when the electroplating is performed.

Next, as shown in FIG. 2D, the other surface of the substrate 12 is polished and planarized so that the conductive material 20 is exposed. That is, the other surface of the substrate 12 is polished and the other surface of the substrate 12 is planarized so that the conductive material 20 filled in the small holes 14 is exposed to the other surface of the substrate 12. do. By the planarization process, the overall height of the substrate 12 may be lowered, and the through electrode 21 filled with the conductive material 20 may be tightly formed.

3 is a flowchart of a method of manufacturing a printed circuit board according to an embodiment of the present invention, and FIG. 4 is a flowchart of a method of manufacturing a printed circuit board according to an embodiment of the present invention. Referring to FIG. 4, the substrate 12, the through hole 13, the small hole 14, the large hole 16, the seed layer 18, the conductive material 20, the through electrode 21, and the first circuit The pattern 22, buildup layer 24, second circuit pattern 26, via 28, and bump 30 are shown.

The printed circuit board manufacturing method according to the present invention can be used not only for manufacturing a wafer level chip package substrate, but also for manufacturing an interposer substrate for electrical connection between a semiconductor chip and a package substrate. In addition, it can of course be used in the manufacture of a general PCB substrate.

Hereinafter, a method of manufacturing an interposer substrate for electrical connection between a semiconductor chip and a package substrate will be described.

As the semiconductor chip becomes smaller and more integrated, the number of I / Os of the semiconductor chip increases, so that the number of pads of the package substrate on which the semiconductor chip is mounted increases, thereby requiring fine pitch of the package substrate. Since the fine pitch of the package substrate increases the manufacturing cost of the package substrate, the fine pitch of the package substrate is overcome by interposing an interposer substrate between the semiconductor chip and the package substrate. However, the interposer substrate on which the semiconductor chip is mounted still requires fine pitching, and accordingly, the through electrode 21 for electrical conduction between the upper and lower sides of the interposer substrate is also required to be miniaturized.

In this embodiment, the substrate 12 is formed with a through hole 13 including a small hole 14 formed from one surface thereof toward the other surface and a large hole 16 having an enlarged cross section at one end of the small hole 14. The method may further include: providing a small hole 14 with the conductive material 20, forming a first circuit pattern 22 on one surface of the substrate 12, and exposing the conductive material 20. Including the step of polishing and flattening the other surface of the 12), the conductive material 20 can form a more tightly charged through electrode 21 to improve the electrical characteristics, the process time for charging is small Can shorten. It is also possible to reduce the overall height of the package substrate.

In the method of manufacturing a printed circuit board according to the present embodiment, first, as shown in (a) of FIG. 4, a small hole 14 is formed from one surface to the other surface and a cross section at one end of the small hole 14. The substrate 12 is provided with a through hole 13 formed of the enlarged large hole 16 (S100).

In drilling the through hole 13 for forming the through electrode 21, a small hole 14 is formed from one surface of the substrate 12 toward the other surface, and a cross section is enlarged at one end of the small hole 14. A through hole 13 having a two-stage structure consisting of a large hole 16 is formed. That is, by providing the through holes 13 having a two-stage structure, only the small holes 14 are filled with the conductive material 20, so that the filling depth can be lowered, making the filling more compact, and the filling process time can be shortened. .

In the case of the interposer substrate for the electrical connection between the semiconductor chip and the package substrate, a fine pitch of the circuit pattern is required to increase the aspect ratio of the through electrode 21, so that the through hole 13 having a two-stage structure When the through electrode 21 is formed using the through electrode 21, the through electrode 21 may be more closely charged. In addition, since the overall height of the package may be increased by the interposer substrate, the overall height of the package may be lowered by lowering the thickness of the interposer substrate by the planarization process described later. Further, even when the conductive material 20 is filled to overfill one end of the small hole 14, the overfilling part is present in the large hole 16, so that the planarization process is not performed because it does not protrude on the surface of the substrate 12. Other processes can be carried out even if not performed.

The substrate 12 of the present embodiment may be either ceramic or silicon wafer. Since the interposer substrate plays a buffer role to alleviate stress due to mismatching of thermal expansion coefficients that may occur between the semiconductor chip and the package substrate, the silicon wafer may be used as the interposer substrate. In addition, high-resistance silicon wafers, polycrystalline silicon, ceramics, glass, PCB substrates, and the like may be used.

Next, as shown in FIGS. 4B and 4C, the small holes 14 are filled with the conductive material 20 (S200). As a method of filling the small holes 14, a method of filling by electroless / electroplating, a method of filling a conductive paste, a method of filling a conductive ink by inkjet printing, a method of polymerizing and filling a conductive polymer, or the like can be used. have.

In this embodiment, a method of filling the small hole 14 with the conductive material 20 by electroplating is disclosed. That is, as shown in FIG. 4B, the seed layer 18 is deposited on one surface of the substrate 12 (S201). When the seed layer 18 is deposited, as shown in (c) of FIG. 4, the small hole 14 is filled by electroplating the seed layer 18 with an electrode (S202). In this case, plating may be overfilled at one end of the small hole 14 when the electroplating is performed.

Next, as shown in FIG. 4D, the first circuit pattern 22 is formed on one surface of the substrate 12 (S300).

It is also possible to planarize the other surface of the substrate 12 by polishing the other surface of the substrate 12 before this step, but since the plating overfilled in the small holes 14 exists in the large hole 16, the surface of the substrate 12 is Since it is not protruded in the planarization process, another process may be performed without first performing the planarization process. In addition, since the damage to the substrate 12 may occur due to the rigidity reduction of the substrate 12 according to the planarization process, another process of maintaining the rigidity of the substrate 12 may be performed first by performing the planarization process later. Can be.

The first circuit pattern 22 may form a plating layer by performing electroplating on one surface of the substrate 12 using the seed layer 18 as an electrode and then forming a circuit pattern by a photolithography process. That is, after forming an etching resist corresponding to the first circuit pattern 22 on the plating layer, an etching solution is applied to one surface of the substrate 12 to selectively etch the plating layer to form the first circuit pattern 22. Of course, it is also possible to form the first circuit pattern 22 by applying the screen printing method in addition to the photolithography method or by ejecting the conductive ink by the inkjet method. The formation of the first circuit pattern 22 is not limited to the above-described method, and the first circuit pattern 22 may be formed by various methods.

Next, as shown in FIG. 4E, a via is stacked on one surface of the substrate 12, and the via is electrically connected to the first circuit pattern 22 on the buildup layer 24. 28 and the second circuit pattern 26 are formed (S400).

The buildup layer 24 is made of an insulating material, and a multilayered printed circuit board may be manufactured by stacking a plurality of buildup layers 24 on the substrate 12 by a buildup method. That is, the build-up layer 24 made of an insulating material is stacked on the substrate 12, and the via 28 and the second circuit pattern 26 electrically connected to the first circuit pattern 22 are formed to form one build-up. The up layer 24 may be formed, and the above steps may be repeated to build up the multilayer build up layer 24. The build-up layer 24 may be stacked in plural, and the vias 28 and the second circuit patterns 26 may be formed in the plurality of build-up layers 24, respectively, to manufacture a multilayer printed circuit board.

As shown in FIG. 4, the build-up layer 24 in which the vias 28 and the second circuit patterns 26 are formed on the substrate 12 is stacked in two stages.

Next, as shown in FIG. 4F, a conductive bump 30 is formed on the surface of the build-up layer 24 and electrically connected to the second circuit pattern 26. S500). The semiconductor chip is subsequently seated on the conductive bumps 30 electrically connected to the second circuit pattern 26 to electrically connect the substrate 12 and the semiconductor chip.

Next, as illustrated in FIG. 4G, the other surface of the substrate 12 is polished and planarized to expose the conductive material 20 (S600). That is, the other surface of the substrate 12 is polished and the other surface of the substrate 12 is planarized so that the conductive material 20 filled in the small holes 14 is exposed to the other surface of the substrate 12. do. By the planarization process, the overall height of the substrate 12 may be lowered, and the through electrode 21 filled with the conductive material 20 may be tightly formed.

As described above, the planarization process is performed after the conductive bumps 30 electrically connected to the second circuit patterns 26 are formed to perform other processes in which the rigidity of the substrate 12 is maintained. Damage to (12) can be prevented.

Next, as shown in FIG. 4H, a conductive bump 30 is formed on the other surface of the substrate 12 and electrically connected to the conductive material 20 (S700). The conductive bumps 30 formed on the other surface of the substrate 12 are for electrically connecting the substrate 12 of this embodiment to the package substrate.

5 is a state diagram used when a printed circuit board according to an embodiment of the present invention is used as an interposer substrate. Referring to FIG. 5, a semiconductor chip 32, an underfill 36, an interposer substrate 38, and a package substrate 34 are shown.

As the semiconductor chip 32 becomes smaller and more highly integrated, the number of I / Os of the semiconductor chip 32 increases, thereby increasing the number of pads of the package substrate 34 on which the semiconductor chip 32 is mounted. Fine pitching is required. Since the fine pitch of the package substrate 34 increases the manufacturing cost of the package substrate 34, the package is interposed between the semiconductor chip 32 and the package substrate 34 with an interposer substrate 38 interposed therebetween. The problem of fine pitch of the substrate 34 is overcome. However, the interposer substrate 38 on which the semiconductor chip 32 is mounted still requires fine pitching, and accordingly, the through electrode 21 for electrical conduction between the upper and lower sides of the interposer substrate 38 is also required to be miniaturized.

Referring to FIG. 5, a highly integrated semiconductor chip 32 is mounted on an interposer substrate 38 manufactured according to the above-described method of manufacturing a printed circuit board. The interposer substrate 38 on which the semiconductor chip 32 is mounted is mounted on the package substrate 34, and between the semiconductor chip 32 and the interposer substrate 38 and between the interposer substrate 38 and the package substrate ( Inject and cure the liquid underfill 36 (34) between the 34 to ensure the reliability of the bonding.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

1 is a flow chart showing a through electrode forming method according to the prior art.

2 is a flow chart showing a through electrode forming method according to an embodiment of the present invention.

Figure 3 is a flow chart of a printed circuit board manufacturing method according to an embodiment of the present invention.

Figure 4 is a flow chart of a printed circuit board manufacturing method according to an embodiment of the present invention.

5 is a state diagram used when the printed circuit board according to an embodiment of the present invention is used as an interposer substrate.

<Explanation of symbols for the main parts of the drawings>

12 substrate 13 through hole

14: small hall 16: large hall

18: seed layer 20: conductive material

21: through electrode 22: first circuit pattern

24: build-up layer 26: the second circuit pattern

28: Via 30: Bump

32: semiconductor chip 34: package substrate

36: underfill 38: interposer substrate

Claims (13)

Providing a substrate having a through hole formed from one surface of the small hole toward the other surface and a large hole having an enlarged cross section at one end of the small hole; Filling the small holes with a conductive material; And And grinding and planarizing the other surface of the substrate so that the large hole is removed and the conductive material is exposed. The method of claim 1, The substrate is a through electrode forming method, characterized in that any one of a ceramic (ceramic) or a silicon wafer (silicon wafer). The method of claim 1, The charging step, Depositing a seed layer on one surface of the substrate; And A through electrode forming method comprising electroplating the seed layer with an electrode. The method of claim 1, The charging step, And overfilling the small holes to one end of the small holes. Providing a substrate having a through hole formed from one surface of the small hole toward the other surface and a large hole having an enlarged cross section at one end of the small hole; Filling the small holes with a conductive material; Forming a first circuit pattern on one surface of the substrate; And And grinding and planarizing the other surface of the substrate to expose the conductive material. The method of claim 5, After the forming of the first circuit pattern, And a build-up step of stacking a build-up layer on one surface of the substrate and forming a via and a second circuit pattern electrically connected to the first circuit pattern on the build-up layer. The method of claim 6, The build-up layer is stacked in plurality, the via and the second circuit pattern is a printed circuit board manufacturing method, characterized in that formed in the plurality of the build-up layer, respectively. The method of claim 6, After the buildup phase above, And forming a conductive bump formed on the surface of the build-up layer and electrically connected to the second circuit pattern. The method of claim 8, And said planarization step is performed after said step of forming said conductive bumps. The method of claim 5, After the planarizing step, And forming a conductive bump formed on the other surface of the substrate and electrically connected to the conductive material. The method of claim 5, The charging step, Depositing a seed layer on one surface of the substrate; And A method of manufacturing a printed circuit board comprising electroplating the seed layer with an electrode. The method of claim 5, The charging step, And filling the end of the small hole to be overfilled. The method of claim 5, The substrate is a printed circuit board manufacturing method, characterized in that any one of a ceramic (ceramic) or a silicon wafer.

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