KR100872583B1 - Method for manufacturing printed circuit board and interposer board - Google Patents

Abstract

A method for manufacturing a printed circuit board and an interposer board are provided to reduce an overall height of a package by reducing the height of the substrate through a planarization process. A small hole(14) is formed at one side to face other side. A penetrating hole(13) composed of a large hole(16) to enlarge a section at one side of the small hole is formed in a substrate(12). When punching the penetrating hole for forming a penetrating electrode(21), the filling is dense by reducing a filling depth by filling the conductive material in the small hole only through the penetrating hole with two stage structure. The filling process time is reduced.

Description

Method for manufacturing printed circuit board and interposer board

The present invention relates to a printed circuit board manufacturing method and an interposer substrate.

 With the development of the electronics industry, portable electronic products such as mobile phones and DMB (Digital Multimedia Broadcasting) are becoming smaller and more functional. Accordingly, electronic components are also required to be miniaturized, highly integrated, multifunctional, and high performance. One of the key technologies that enables this product development goal is package assembly technology.

Chip-scale package as a package assembly technology is a new type of package that has been recently developed and proposed, and has the advantage of greatly reducing the size of a package compared to a typical plastic package.

Chip-scale packages are mainly used in products requiring miniaturization and mobility, such as digital camcorders, mobile phones, notebook computers, memory cards, and so on, and include digital signal processors (DSPs), application specific integrated circuits (ASICs), and microcontrollers (microcontrollers). Semiconductor devices such as controllers are mounted in chip-scale packages. In addition, the use of chip-scale packages in which memory devices such as dynamic random access memory (DRAM), flash memory, and the like are mounted is increasingly being used.

However, while the chip scale package has an absolute advantage in terms of size, it is difficult to secure reliability and additional manufacturing equipment is required for the manufacture of the chip scale package. There is a downside to falling.

In order to solve this problem, chip-scale packages are emerging at the wafer level. In a typical wafer fabrication process, when a semiconductor wafer is manufactured, individual chips are separated from the wafer and subjected to a package assembly process. This package assembly process is completely separate from the wafer fabrication process and requires different equipment and raw materials. However, it is possible to produce a package as a complete product at the wafer level, i.e. without separating individual chips from the wafer. Therefore, the existing wafer manufacturing equipment and processes can be used as it is in the manufacturing equipment or manufacturing process used to manufacture the package. This also means that it is possible to minimize the additional raw materials required to manufacture the package. In addition, a stack package in which a chip scale package manufactured at the wafer level is stacked in three dimensions is also emerging.

On the other hand, as the semiconductor chip becomes more sophisticated and highly integrated, the number of I / Os of the semiconductor chip increases, so that the number of pads of the package substrate on which the semiconductor chip is mounted increases, thereby requiring fine pitch of the package substrate. Since the fine pitch of the package substrate increases the manufacturing cost of the package substrate, the fine pitch of the package substrate is overcome by interposing an interposer board between the semiconductor chip and the package substrate. Further, when the semiconductor chip is mounted on the package substrate, the reliability of the electrical connection of the thermal expansion coefficient of the package substrate and the semiconductor chip may be deteriorated. Thus, mismatching of the thermal expansion coefficient may be caused by interposing the interposer substrate between the semiconductor chip and the package substrate. It acts as a buffer to alleviate stress caused by miss matching.

However, the interposer substrate on which the semiconductor chip is mounted is still required to have fine pitch, and accordingly, the through electrode for electrical conduction between the upper and lower sides of the interposer substrate is also required to be refined.

1 is a flowchart illustrating a method of forming a through electrode according to the prior art. In order to form a fine through electrode 106 on the substrate 102 according to the prior art, first, a small aperture through hole is drilled through the substrate 102 and a conductive material is filled into the through hole by plating. In this case, as shown in FIG. 1, the through-electrode 106 is formed by performing a planarization process of polishing the surface of the overfilled substrate by performing plating to overfill the through-hole.

However, the method of forming the through electrode according to the related art has a problem in that the through hole has a small diameter and the thickness of the plate is large, so that the plating solution does not penetrate the through hole so that the filling rate of the through hole is low and the electrical characteristics are not good.

In addition, in order to stack the chip scale package manufactured at the wafer level in three dimensions, a through electrode is required between the chip scale packages disposed up and down. Due to the high integration and high density of chips, it is very difficult to charge through electrodes without voids or gaps in the through holes because the aspect ratio is much larger than that of a printed circuit board (PCB). .

On the other hand, the interposer substrate is interposed between the semiconductor chip and the package substrate to electrically connect the semiconductor chip and the package substrate, there is a problem that the height of the entire package is increased.

The present invention provides a through electrode forming method and a printed circuit board manufacturing method capable of forming a through electrode filled with a conductive material more tightly without voids or cracks, and reducing the overall height of the package. To provide.

According to one aspect of the invention, providing a substrate formed with a through hole consisting of a small hole formed from one side toward the other surface, and a large hole in which the cross section is enlarged at one end of the small hole, filling the small hole with a conductive material And forming a through electrode by polishing the other surface of the substrate to expose the conductive material, and forming a first circuit pattern electrically connected to the through electrode on one surface of the substrate.

The method may further include stacking a first build-up layer on one surface of the substrate and forming first vias and second circuit patterns electrically connected to the first circuit patterns on the first build-up layer. .

The first buildup layer may be stacked in plural, and the first via and the second circuit pattern may be formed in the plurality of first buildup layers, respectively.

After the forming of the second circuit pattern, the method may further include forming a conductive bump formed on the surface of the first build-up layer and electrically connected to the second circuit pattern.

Forming a third circuit pattern electrically connected to the through electrode on the other surface of the substrate; stacking a second buildup layer on the other surface of the substrate; and a second via electrically connected to the third circuit pattern on the second buildup layer; The method may further include forming a fourth circuit pattern.

A plurality of second buildup layers may be stacked, and the second via and fourth circuit patterns may be formed in the plurality of second buildup layers, respectively.

After the forming of the fourth circuit pattern, the method may further include forming a conductive bump formed on the surface of the second build-up layer and electrically connected to the fourth circuit pattern.

The method may further include forming a conductive bump formed on the other surface of the substrate and electrically connected to the through electrode.

The filling may include depositing a seed layer on one surface of the substrate and electroplating the seed layer with an electrode.

The filling may also include filling to overfill with one end of the small hole.

The substrate may be made of either ceramic or silicon.

According to another aspect of the present invention, a silicon substrate, a through electrode formed through the silicon substrate, a buildup layer stacked on one side and the other surface of the silicon substrate, and a buildup layer electrically connected to the through electrode The interposer board is electrically connected to vias and vias, and includes circuit patterns formed on the build-up layer, respectively.

The buildup layer may be stacked in plural, and the via and circuit patterns may be formed in plural to be processed in the plurality of buildup layers and electrically connected to each other.

It may further include a conductive bump formed on the surface of the buildup and electrically connected to the via.

The through electrode is filled with a conductive material in a small hole of a silicon substrate formed with a small hole formed from one surface thereof toward the other surface and a large hole formed with a large hole having an enlarged cross section at one end of the small hole, and then polishing the other surface of the silicon substrate. Can be formed.

The printed circuit board manufacturing method and the interposer substrate according to the present invention can improve the electrical properties by forming a through electrode filled with a conductive material more tightly without voids or cracks, and the filling depth Small size can shorten the process time for charging.

In addition, the overall height of the package can be lowered by reducing the height of the substrate through the planarization process.

In addition, by forming a multi-layered circuit pattern on both sides of the silicon substrate it is possible to enlarge the wiring area, it is possible to exhibit an excellent electrical characteristics by reducing the electrical path.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, an embodiment of a method for manufacturing a printed circuit board and an interposer substrate according to the present invention will be described in detail with reference to the accompanying drawings. In describing the accompanying drawings, the same or corresponding components may have the same reference numerals. And duplicate description thereof will be omitted.

2 is a flowchart illustrating a method of forming a through electrode according to a first embodiment of the present invention. Referring to FIG. 2, a substrate 12, a small hole 14, a large hole 16, a through hole 13, a seed layer 18, a conductive material 20, and a through electrode 21 are illustrated. .

According to the present embodiment, the substrate 12 having the through-hole 13 formed of a small hole 14 formed from one surface thereof toward the other surface and a large hole 16 having an enlarged cross section at one end of the small hole 14 is formed. Providing a small hole 14 with the conductive material 20 and polishing and planarizing the other surface of the substrate 12 to expose the conductive material 20. By forming the more tightly charged through electrode 21, the electrical characteristics can be improved, and the filling depth can be shortened, thereby shortening the processing time for charging. It is also possible to reduce the overall height of the package substrate.

In the through-electrode forming method according to the present embodiment, first, as shown in (a) of FIG. 2, a small hole 14 is formed from one surface to the other surface, and a cross section is enlarged at one end of the small hole 14. Provided is a substrate 12 in which a through hole 13 consisting of a large hole 16 is formed.

In the drilling of the through-holes for forming the through-electrode 21, the small hole 14 formed from one surface of the substrate 12 toward the other surface, and the large hole whose cross section is enlarged at one end of the small hole 14 ( A through hole 13 having a two-stage structure composed of 16 is formed. That is, by providing the through holes 13 having a two-stage structure, only the small holes 14 are filled with the conductive material 20, so that the filling depth can be lowered, making the filling more compact, and the filling process time can be shortened. .

In particular, since the aspect ratio of the through-holes for forming the through-electrode 21 is very large in the manufacture of a wafer-level chip package substrate, the filling rate of the through-holes decreases, and voids or cracks are formed even when the through-holes 21 are filled. A seam may occur. Therefore, the through hole 13 having a two-stage structure is formed so that only the small hole 14 is filled, thereby making the filling more compact. That is, since the aspect ratio of the small hole 14 is small, a filling rate can be raised. Here, an aspect ratio means a value obtained by dividing the depth of the through hole by the diameter of the through hole.

In addition, in the case of the interposer substrate for the electrical connection between the semiconductor chip and the package substrate, the fine pitch of the circuit pattern is required to increase the aspect ratio of the through electrode 21. If the through electrode 21 is formed by using the 13), the through electrode 21 may be more closely charged. In addition, since the overall height of the package may be increased by the interposer substrate, the overall height of the package may be lowered by lowering the thickness of the interposer substrate by the planarization process described later.

The substrate 12 of the present embodiment may be either ceramic or silicon wafer. In addition, high-resistance silicon wafers, polycrystalline silicon, glass, PCB substrates, and the like may be used.

Next, the small holes 14 are filled with the conductive material 20. As a method of filling the small holes 14, a method of filling by electroless / electroplating, a method of filling a conductive paste, a method of filling a conductive ink by inkjet printing, a method of polymerizing and filling a conductive polymer, or the like can be used. have.

In this embodiment, a method of filling the small hole 14 with the conductive material 20 by electroplating is disclosed. That is, as shown in FIG. 2B, the seed layer 18 is deposited on one surface of the substrate 12. When the seed layer 18 is deposited, as shown in (c) of FIG. 2, the small hole 14 is filled by electroplating the seed layer 18 with an electrode. In this case, plating may be overfilled at one end of the small hole 14 when the electroplating is performed.

Next, as shown in FIG. 2D, the other surface of the substrate 12 is polished and planarized so that the conductive material 20 is exposed. That is, the other surface of the substrate 12 is polished and the other surface of the substrate 12 is planarized so that the conductive material 20 filled in the small holes 14 is exposed to the other surface of the substrate 12. do. By the planarization process, the overall height of the substrate 12 may be lowered, and the through electrode 21 filled with the conductive material 20 may be tightly formed.

3 is a flowchart of a method of manufacturing a printed circuit board according to a second embodiment of the present invention, and FIG. 4 is a flowchart of a method of manufacturing a printed circuit board according to a second embodiment of the present invention. Referring to FIG. 4, the substrate 12, the through hole 13, the small hole 14, the large hole 16, the seed layer 18, the conductive material 20, the through electrode 21, and the first circuit The pattern 22, the first buildup layer 24, the second buildup layer 25, the second circuit pattern 26, the third circuit pattern 27, the first via 28, and the fourth circuit pattern 29 ), Bumps 30, and second vias 31 are shown.

The printed circuit board manufacturing method according to the present invention can be used not only for manufacturing a wafer level chip package substrate, but also for manufacturing an interposer substrate for electrical connection between a semiconductor chip and a package substrate. In addition, it can of course be used in the manufacture of a general PCB substrate.

Hereinafter, a method of manufacturing an interposer substrate for electrical connection between a semiconductor chip and a package substrate will be described.

As the semiconductor chip becomes smaller and more integrated, the number of I / Os of the semiconductor chip increases, so that the number of pads of the package substrate on which the semiconductor chip is mounted increases, thereby requiring fine pitch of the package substrate. Since the fine pitch of the package substrate increases the manufacturing cost of the package substrate, the fine pitch of the package substrate is overcome by interposing an interposer substrate between the semiconductor chip and the package substrate. However, the interposer substrate on which the semiconductor chip is mounted still requires fine pitching, and accordingly, the through electrode 21 for electrical conduction between the upper and lower sides of the interposer substrate is also required to be miniaturized.

Meanwhile, the interposer substrate may be interposed between the semiconductor chip and the semiconductor chip (see FIG. 6) and used for manufacturing a package having a stacked structure in which electrical connections between the semiconductor chips and a plurality of semiconductor chips are stacked.

According to the present embodiment, the substrate 12 having the through-hole 13 formed of a small hole 14 formed from one surface thereof toward the other surface and a large hole 16 having an enlarged cross section at one end of the small hole 14 is formed. Providing, filling the small holes 14 with the conductive material 20, polishing the other surface of the substrate 12 to expose the conductive material 20 to form the through electrode 21 and the substrate 12. And forming a first circuit pattern 22 electrically connected to the through electrode 21 on one surface thereof, thereby forming a through electrode 21 filled with the conductive material 20 more tightly. It can be improved, and the filling depth can be shortened and the process time for filling can be shortened. It is also possible to reduce the overall height of the package substrate. In addition, by forming a multi-layered circuit pattern on both sides of the substrate 12, it is possible to enlarge the wiring area, it is possible to exhibit an excellent electrical characteristics by reducing the electrical path.

In the method of manufacturing a printed circuit board according to the present embodiment, first, as shown in (a) of FIG. 4, a small hole 14 is formed from one surface to the other surface and a cross section at one end of the small hole 14. The substrate 12 is provided with a through hole 13 formed of the enlarged large hole 16 (S100).

In drilling the through hole 13 for forming the through electrode 21, a small hole 14 is formed from one surface of the substrate 12 toward the other surface, and a cross section is enlarged at one end of the small hole 14. A through hole 13 having a two-stage structure consisting of a large hole 16 is formed. That is, by providing the through holes 13 having a two-stage structure, only the small holes 14 are filled with the conductive material 20, so that the filling depth can be reduced, thereby making the filling more compact, and the filling process time can be shortened. .

In the case of the interposer substrate for the electrical connection between the semiconductor chip and the package substrate, a fine pitch of the circuit pattern is required to increase the aspect ratio of the through electrode 21, so that the through hole 13 having a two-stage structure When the through electrode 21 is formed using the through electrode 21, the through electrode 21 may be more closely charged. In addition, since the overall height of the package may be increased by the interposer substrate, the overall height of the package may be lowered by lowering the thickness of the interposer substrate by the planarization process described later. Further, even when the conductive material 20 is filled to overfill one end of the small hole 14, the overfilling part is present in the large hole 16, so that the planarization process is not performed because it does not protrude on the surface of the substrate 12. Other processes can be carried out even if not performed.

The substrate 12 of the present embodiment may include any one of ceramic or silicon. The interposer substrate may be used as an interposer substrate because the interposer substrate acts as a buffer for mitigating stress caused by mismatching of the coefficient of thermal expansion that may occur between the semiconductor chip and the package substrate or between the semiconductor chip and the semiconductor chip. . In addition, high-resistance silicon wafers, polycrystalline silicon, ceramics, glass, PCB substrates, and the like may be used.

Next, as shown in FIGS. 4B and 4C, the small holes 14 are filled with the conductive material 20 (S200). As a method of filling the small holes 14, a method of filling by electroless / electroplating, a method of filling a conductive paste, a method of filling a conductive ink by inkjet printing, a method of polymerizing and filling a conductive polymer, or the like can be used. have.

In this embodiment, a method of filling the small hole 14 with the conductive material 20 by electroplating is disclosed. That is, as shown in FIG. 4B, the seed layer 18 is deposited on one surface of the substrate 12 (S201). When the seed layer 18 is deposited, as shown in (c) of FIG. 4, the small hole 14 is filled by electroplating the seed layer 18 with an electrode (S202). In this case, plating may be overfilled at one end of the small hole 14 when the electroplating is performed.

Next, as shown in FIG. 4D, the other surface of the substrate 12 is polished so that the conductive material 20 is exposed to form the through electrode 21 (S300). That is, the other surface of the substrate 12 is polished so that the other surface of the substrate 12 on which the large hole 16 is opened is polished so that the conductive material 20 filled in the small hole 14 is exposed to the other surface of the substrate 12. To flatten. Through the planarization process, the through electrode 21 penetrating from one surface of the substrate 12 to the other surface can be formed, the overall height of the substrate 12 can be lowered, and the penetration of the conductive material 20 tightly filled. The electrode 21 can be formed.

Next, as shown in FIG. 4E, the first circuit pattern 22 is formed on one surface of the substrate 12 (S400).

It is also possible to planarize the other surface of the substrate 12 by polishing the other surface of the substrate 12 before this step, but the conductive material 20 overfilled in the small holes 14 is present in the large hole 16 so that the substrate Even if the surface of the substrate 12 is not protruded and the planarization process is not performed first, the first circuit pattern 22 forming process and the first buildup layer 24 forming process may be performed on one surface of the substrate 12.

The first circuit pattern 22 may be formed by a photolithography process after forming a plating layer by performing electroplating on one surface of the substrate 12 using the seed layer 18 as an electrode. That is, after forming an etching resist corresponding to the first circuit pattern 22 on the plating layer, an etching solution may be applied to one surface of the substrate 12 to selectively etch the plating layer to form the first circuit pattern 22. Of course, one surface of the substrate 12 is polished and the seed layer 18 is removed, followed by screen printing in addition to the photolithography method to form the first circuit pattern 22 or by discharging conductive ink by an inkjet method to thereby form the first circuit. It is also possible to form the pattern 22. In forming the first circuit pattern 22, the method is not limited to the above-described method, and the first circuit pattern 22 may be formed by various methods.

Next, as shown in FIG. 4F, the first buildup layer 24 is stacked on one surface of the substrate 12, and the first circuit pattern 22 and the first circuit pattern 22 are electrically stacked on the first buildup layer 24. A first via 28 and a second circuit pattern 26 connected to each other are formed (S400).

The buildup layer 24 is made of an insulating material, and a multilayered printed circuit board may be manufactured by stacking a plurality of buildup layers 24 on the substrate 12 by a buildup method. That is, the build-up layer 24 made of an insulating material is stacked on the substrate 12, and the first via 28 and the second circuit pattern 26 electrically connected to the first circuit pattern 22 are formed to form one. Build-up of the multi-layer build-up layer 24 may be performed by repeating the above steps. The build-up layer 24 may be stacked in plural, and the first via 28 and the second circuit pattern 26 may be formed in the plurality of build-up layers 24, respectively, to manufacture a multilayer printed circuit board.

As shown in FIG. 4, the buildup layer 24 having the plurality of first vias 28 and the second circuit patterns 26 formed on one surface of the substrate 12 is stacked in three stages. Suggesting.

Next, as shown in FIGS. 4G and 4H, after forming the third circuit pattern 27 electrically connected to the through-electrode 21 on the other surface of the substrate 12. In operation S600, the second buildup layer 25 is stacked on the other surface of the substrate 12 on which the third circuit pattern 27 is formed, and the second buildup layer 25 is electrically connected to the third circuit pattern 27. The second via 31 and the fourth circuit pattern 29 are formed (S700). In this case, a plurality of second buildup layers 25 may be stacked, and the second vias 31 and the fourth circuit patterns 29 may be formed in the plurality of second buildup layers 25, respectively.

If a high density wiring area is required on the interposer substrate interposed between the semiconductor chip and the package substrate or between the semiconductor chip and the semiconductor chip, a large wiring area is secured by stacking a plurality of buildup layers on both sides of the substrate 12. It can be lowered, thereby improving the reliability of the electrical connection, and lower the manufacturing failure rate. That is, a multi-layer buildup layer may be stacked on the other surface of the substrate 12 to secure the wiring area.

The method of forming the third circuit pattern 27 on the other surface of the substrate 12, the second build-up layer 25 is laminated on the other surface of the substrate 12 on which the third circuit pattern 27 is formed, and the second build up is performed. Since the method of forming the second via 31 and the fourth circuit pattern 29 electrically connected to the third circuit pattern 27 on the up layer 25 is the same as the method described above, the description thereof will be omitted.

As shown in FIG. 4, the second build-up layer 25 having the plurality of second vias 31 and the fourth circuit patterns 29 formed on the other surface of the substrate 12 is stacked in two stages. The form is presented.

Next, as shown in FIG. 4I, a conductive bump 30 is formed on the surface of the first build-up layer 24 and electrically connected to the second circuit pattern 26. In operation S800, a conductive bump 30 is formed on the surface of the second build-up layer 25 and electrically connected to the fourth circuit pattern 29 (S900).

The conductive bumps 30 allow the semiconductor chip to be electrically connected to the interposer substrate by a flip chip method, or the interposer substrate to be electrically connected to the package substrate by a flip chip method.

In addition to the above-described embodiment, after the multilayer build-up layer is stacked only on one surface of the substrate 12 and vias and circuit patterns are formed, the conductive bumps 30 electrically connected to the through electrodes 21 are formed on the other surface of the substrate 12. It is also possible to form an interposer substrate by forming it.

5 is a cross-sectional view of an interposer substrate according to a third embodiment of the present invention. Referring to FIG. 5, an interposer substrate 40, a silicon substrate 42, a through electrode 44, a buildup layer 46, a via 48, a circuit pattern 50, and a bump 52 are illustrated. .

As the semiconductor chip becomes smaller and more integrated, the number of I / Os of the semiconductor chip increases, so that the number of pads of the package substrate on which the semiconductor chip is mounted increases, thereby requiring fine pitch of the package substrate. Since the fine pitch of the package substrate increases the manufacturing cost of the package substrate, the problem of fine pitch of the package substrate is overcome by interposing an interposer board 40 between the semiconductor chip and the package substrate. . However, the interposer substrate 40 on which the semiconductor chip is mounted is still required to have fine pitch, and accordingly, the through electrode 44 for electrical conduction between the top and bottom of the interposer substrate 40 is also required to be miniaturized.

On the other hand, the interposer substrate 40 may be used not only between the semiconductor chip and the package substrate, but also interposed between the semiconductor chip and the semiconductor chip, for electrical connection between the semiconductor chips, and for manufacturing a package having a stacked structure in which a plurality of semiconductor chips are stacked. .

The interposer substrate 40 according to the present embodiment includes a silicon substrate 42, a through electrode 44 formed through the silicon substrate 42, and a buildup layer stacked on one surface and the other surface of the silicon substrate 42, respectively. 46 and a circuit pattern 50 formed through the build-up layer 46 and electrically connected to the via 48 and the via 48 that are electrically connected to the through electrode 44 through the build-up layer 46. ) As a component, the build-up layer 46 is formed on both sides of the silicon substrate 42, and the multi-layer circuit pattern 50 is formed on both sides of the silicon substrate 42 to enlarge the wiring area. By reducing the path, it can exhibit excellent electrical properties.

The interposer substrate 40 may be manufactured at the wafer level by using the silicon substrate 42 in the form of a silicon wafer. The interposer substrate 40 acts as a buffer to alleviate the stress caused by mismatching of the coefficient of thermal expansion that may occur between the semiconductor chip and the package substrate or between the semiconductor chip and the semiconductor chip. Silicone can be used. In addition, high resistance silicon, polycrystalline silicon, ceramics, and the like may be used.

The through electrode 44 is filled with a conductive material in a small hole of the silicon substrate 42 formed with a small hole formed from one surface toward the other surface, and a large hole formed with a large hole having an enlarged cross section at one end of the small hole. It can be formed by polishing the other surface of 42. As such, the through electrode 44 may be formed to form the through electrode 44 filled with the conductive material more tightly, thereby improving electrical characteristics, and the process time for charging may be shortened due to the small filling depth. In addition, when the height of the interposer substrate 40 is reduced, when the semiconductor chip is mounted and the interposer substrate 40 is mounted on the package substrate, the overall height of the package may be reduced.

In particular, in the manufacture of a chip package substrate at the wafer level, the aspect ratio of the through-holes for forming the through-electrode 44 is very large, so that the filling rate of the through-holes is reduced, and voids or cracks are formed even when the wafers are filled. A seam may occur. Therefore, the through-hole of the two-stage structure is formed to fill only small holes, thereby making the filling more compact. In other words, the filling ratio is small because the aspect ratio of the small hole is small. Here, an aspect ratio means a value obtained by dividing the depth of the through hole by the diameter of the through hole.

In addition, in the case of the interposer substrate 40 for electrical connection between the semiconductor chip and the package substrate, a fine pitch of the circuit pattern is required to increase the aspect ratio of the through electrode 44. When the through electrode 44 is formed using the through hole, the through electrode 44 may be more tightly charged. Since the overall height of the package may be increased by the interposer substrate 40, the overall height of the package may be lowered by lowering the thickness of the interposer substrate 40 by a planarization process of polishing the other surface of the silicon substrate 42. Can be.

The buildup layer 46 may be stacked on one surface and the other surface of the silicon substrate 42 to enlarge the wiring area of the interposer substrate 40.

The interposer substrate 40 is to solve the problem caused by the fine pitch of the package substrate. However, since the interposer substrate 40 still requires fine pitch, when the fine pitch of the interposer substrate 40 is required according to many wiring areas, the build-up layer 46 is laminated and built on both sides of the silicon substrate 42. By forming a via 48 and a circuit pattern 50 electrically connected to the through electrode 44 in the up layer, the wiring area may be enlarged to solve the problem of fine pitch of the interposer substrate 40.

The build-up layer 46 is made of an insulating material, and the multi-layer interposer substrate 40 may be manufactured by stacking the multi-layer build-up layer 46 on both sides of the silicon substrate 42 by the build-up method. That is, a buildup layer 46 made of an insulating material is stacked on both surfaces of the silicon substrate 42, and a via 48 and a circuit pattern 50 electrically connected to the through electrode 44 are formed to form one buildup. Next, the process may be repeated to build up the multilayer buildup layer 46. The build-up layer 46 may be stacked in plurality, and the vias 48 and the circuit patterns 50 may be formed in the plurality of build-up layers 46, respectively, to manufacture a multi-layer interposer substrate 40.

In this embodiment, as shown in FIG. 5, the build-up layer 46 having the plurality of vias 48 and the circuit patterns 50 formed on one surface of the silicon substrate 42 is stacked in three stages, and the silicon substrate 42 is stacked. The build-up layer 46 having a plurality of vias 48 and a circuit pattern 50 formed on the other surface of the top surface is provided in two layers.

A conductive bump 52 may be formed on the surface of the build-up layer 46 to be electrically connected to the via 48. The conductive bumps 52 electrically connect the semiconductor chips on the interposer substrate 40 by a flip chip method, or electrically connect the interposer substrate 40 on the package substrate by a flip chip method. To be connected.

FIG. 6 is a state diagram when an interposer substrate according to a third embodiment of the present invention is used for a package, and FIG. 7 is a case where semiconductor chips are mounted on both surfaces of an interposer substrate according to a third embodiment of the present invention. State of use. Referring to FIG. 5, a semiconductor chip 32, an underfill 36, an interposer substrate 40, and a package substrate 34 are shown.

6 illustrates a structure in which the semiconductor chip 32 is mounted on one surface of the interposer substrate 40 according to the present embodiment, and the interposer substrate 40 on which the semiconductor chip 32 is mounted is mounted on the package substrate 34. 7 shows a structure in which the semiconductor chips 32 are mounted on both surfaces of the interposer substrate 40 according to the present embodiment.

That is, as shown in FIG. 5, the semiconductor chip 32 having a high degree of integration is mounted on a conductive bump formed on one surface of the interposer substrate 40 by a flip chip method, and the interposer on which the semiconductor chip 32 is mounted. The substrate 40 is mounted on the package substrate 34 by a flip chip method via conductive bumps formed on the other surface of the interposer substrate 40. At this time, a liquid underfill solution is injected and cured between the semiconductor chip 32 and the interposer substrate 40 and between the interposer substrate 40 and the package substrate 34 to improve the reliability of the bonding. It can be secured.

In addition, as shown in FIG. 6, the highly integrated semiconductor chip 32 may be mounted on both surfaces of the interposer substrate 40 by a flip chip method, and then remounted on the package substrate. The interposer substrate 40 may have a plurality of build-up layers formed on both sides of the silicon substrate to secure a larger wiring area, thereby increasing design freedom, and reducing electrical paths, thereby exhibiting excellent electrical characteristics.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

1 is a flow chart showing a through electrode forming method according to the prior art.

2 is a flowchart illustrating a through electrode forming method according to a first embodiment of the present invention;

Figure 3 is a flow chart of a printed circuit board manufacturing method according to a second embodiment of the present invention.

4 is a flowchart of a method of manufacturing a printed circuit board according to a second embodiment of the present invention.

5 is a cross-sectional view of an interposer substrate according to a third embodiment of the present invention.

6 is a use state diagram when an interposer substrate according to a third embodiment of the present invention is used for a package;

7 is a use state diagram when semiconductor chips are mounted on both surfaces of an interposer substrate according to a third embodiment of the present invention;

<Explanation of symbols for the main parts of the drawings>

12 substrate 13 through hole

14: small hall 16: large hall

18: seed layer 20: conductive material

21: through electrode 22: first circuit pattern

24, 25: build-up layer 26: the second circuit pattern

28: Via 30, 52: Bump

32: semiconductor chip 34: package substrate

36: underfill 40: interposer substrate

Claims (15)

Providing a substrate having a through hole formed from one surface of the small hole toward the other surface and a large hole having an enlarged cross section at one end of the small hole; Filling the small holes with a conductive material; Polishing the other surface of the substrate to expose the conductive material to form a through electrode; And And forming a first circuit pattern electrically connected to the through electrode on one surface of the substrate. The method of claim 1, Stacking a first build-up layer on one surface of the substrate and forming first vias and second circuit patterns electrically connected to the first circuit patterns on the first build-up layer; Printed circuit board manufacturing method. The method of claim 2, The first build-up layer is stacked in plurality, the first via and the second circuit pattern is a printed circuit board manufacturing method, characterized in that formed on the plurality of first build-up layer, respectively. The method of claim 2, After the forming of the second circuit pattern, And forming a conductive bump formed on a surface of the first build-up layer and electrically connected to the second circuit pattern. The method of claim 2, Forming a third circuit pattern electrically connected to the through electrode on the other surface of the substrate; And Laminating a second build-up layer on the other surface of the substrate, and forming a second via and a fourth circuit pattern electrically connected to the third circuit pattern on the second build-up layer . The method of claim 5, The second build-up layer is stacked in plurality, the second via and the fourth circuit pattern is a printed circuit board manufacturing method, characterized in that formed in the plurality of second build-up layer, respectively. The method of claim 5, After the forming of the fourth circuit pattern, And forming a conductive bump formed on a surface of the second build-up layer and electrically connected to the fourth circuit pattern. The method of claim 1, And forming a conductive bump formed on the other surface of the substrate and electrically connected to the through electrode. The method of claim 1, The charging step, Depositing a seed layer on one surface of the substrate; And A method of manufacturing a printed circuit board comprising electroplating the seed layer with an electrode. The method of claim 1, The charging step, And filling the end of the small hole to be overfilled. The method of claim 1, The substrate is a printed circuit board manufacturing method comprising any one of ceramic (ceramic) or silicon. A silicon substrate; A through electrode formed through the silicon substrate; A buildup layer stacked on the silicon substrate; A via penetrating the build-up layer to electrically connect with the through electrode; And The circuit pattern is electrically connected to the vias and includes circuit patterns respectively formed in the buildup layer. The through-electrode is filled with a conductive material in the small hole of the silicon substrate, the through-hole formed of a small hole formed from one surface toward the other surface, and a large hole extending in cross section at one end of the small hole, the silicon substrate Interposer substrate, characterized in that formed by polishing the other surface. The method of claim 12, The build-up layer is stacked in a plurality, the via and the circuit pattern is a plurality of build-up layer, the interposer substrate, characterized in that formed in plurality to be electrically connected to each other. The method of claim 12, And a conductive bump formed on a surface of the build up and electrically connected to the via. The method of claim 12, The buildup layer, And an interposer substrate stacked on both sides of the silicon substrate.

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