KR100869360B1 - Over Driving Pulse Generator and Memory Device that includes the Over Driving Pulse Generator - Google Patents

Abstract

The present invention provides an over-driving pulse generator for outputting pulses having different widths according to temperature, and a memory device including the same. The memory device of the present invention provides a bit for amplifying a voltage difference between a pair of bit lines. Line sense amplifiers; A sense amplifier driver supplying driving power to the bit line sense amplifier for enabling the bit line sense amplifier, supplying the driving power as a high voltage for overdriving at an initial stage and a core voltage thereafter; And an over-driving pulse generator which generates a plurality of pulses having different widths, selects one of the plurality of pulses according to temperature information indicating the temperature of the memory device, and outputs the over-driving pulse for determining the size of the overdriving section. Include.

Overdriving, Bitline Sense Amplifier, Temperature Information Output Device

Description

Over Driving Pulse Generator and Memory Device that includes the Over Driving Pulse Generator}

1 is a conventional bit line sensing timing diagram for explaining an overdriving scheme.

2A is a circuit diagram of an overdriving pulse generator according to the prior art, and FIG. 2B is a signal timing diagram thereof.

3 is a circuit diagram showing a core structure of a memory device.

4 is a block diagram of an overdriving pulse generator according to an embodiment of the present invention.

5 is a configuration diagram of an embodiment of the pulse generator 410 of FIG. 4.

6 is a configuration diagram of an embodiment of the temperature information output device 420 of FIG.

7 shows when the flag signals TEMPA, TEMPB, and TEMPC are enabled.

8 is a diagram illustrating an embodiment of the pulse output unit 430 of FIG. 4.

* Explanation of symbols for the main parts of the drawings

410: pulse generator 420: temperature information output device

430: pulse output unit

The present invention relates to a pulse generator and a memory device including the same, and more particularly, to a pulse generator for over-driving when driving a bit line sense amplifier and a memory device including the same.

As is well known, when a DRAM reads data stored in a memory cell, a signal is amplified by a bit line sense amplifier, and an over driving scheme is applied in an initial period of enable of the bit line sense amplifier.

FIG. 1 illustrates a conventional bit line sensing timing diagram for explaining an overdriving scheme, and looks at the amplification process and the overdriving operation of a bit line sense amplifier.

When the word line WL of the selected memory cell is activated, charge sharing occurs between the data stored in the cell and the bit line that has been precharged, and thus, between the right bit line BL and the sub bit line BLB. A minute voltage difference dV is generated at. The section is indicated by reference numeral 102.

Thereafter, the bit line sense amplifier is enabled so that the positive bit line BL and the sub bit line BLB are spread with the core voltage VCORE and the ground voltage VSS. The bit line sense amplifier is enabled by applying power to driving power lines rto and sb of the sense amplifier. That is, by applying the core voltage VCORE to the rto line and applying the ground voltage VSS to the sb line, the sense amplifier is driven to amplify the signal of the bit line TKd.

On the other hand, as described above, the driving is overdriving by applying a high voltage of more than the core voltage to the rto line in the initial enable period of the sense amplifier, and the overdriving section is indicated as "103" in the figure. The size of the overdriving section is determined by the pulse width of the overdriving pulse.

2A is a circuit diagram of an overdriving pulse generator according to the prior art, and FIG. 2B is a signal timing diagram thereof.

As shown in FIG. 2A, the conventional overdriving pulse generator includes a delay circuit unit 201 in which an inverter is connected in series to delay an input signal, a NAND gate 202 for receiving an input signal and a delayed signal, and a NAND gate. And an inverter 203 which receives the output signal of 202 and outputs an overdriving pulse signal. The delay circuit section 201 includes an odd number of inverters.

Referring to FIG. 2B, when an input signal 211 is input to the node A (the input signal is a signal activated by an active command and inactivated by a precharge command, a bit line sense after an active command). The delay signal is delayed by the time until the operation of the amplifier.) The input circuit is inverted and delayed by the delay circuit unit 201.

The input signal 211 and the inverted and delayed signal 212 are logically combined through the NAND gate 202 and the inverter to generate a final overdriving pulse 213.

As described above, the conventional overdriving pulse generator is only capable of generating an overdriving pulse signal having a set pulse width, and it is impossible to change the width of the pulse with temperature. That is, it is inevitable to generate a signal whose pulse width is determined by a preset inverter delay value.

However, at low temperatures, the threshold voltage (Vt) of the transistors in the memory device rises, which causes various characteristics of the memory device to change with temperature, such as a decrease in the write recovery time (tWR) characteristic of the memory device. Therefore, there is a need to adjust the width of the overdriving pulse proportionally or inversely with temperature.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide an overdriving pulse generator in which the width of a pulse is adjusted according to temperature.

Another object of the present invention is to provide a memory device in which the size of an overdriving section during bit line sensing is adjusted according to temperature.

The present invention for achieving the above object, the pulse generator for generating a plurality of pulse signals of different widths; A temperature information output device for outputting temperature information; And a pulse output unit configured to select and output one of the plurality of pulse signals using the temperature information.

In addition, a bit line sense amplifier for amplifying the voltage difference between the bit line pair; A sense amplifier driver supplying driving power to the bit line sense amplifier for enabling the bit line sense amplifier, supplying the driving power as a high voltage for overdriving at an initial stage and a core voltage thereafter; And an over-driving pulse generator which generates a plurality of pulses having different widths, selects one of the plurality of pulses according to temperature information indicating the temperature of the memory device, and outputs the over-driving pulse for determining the size of the overdriving section. A memory device is provided.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

3 is a circuit diagram illustrating a core structure of a memory device.

As shown in FIG. 3, the core of the memory device includes a bit line sense amplifier 310, a sense amplifier driver 320, and an overdriving controller 330.

The bit line sense amplifier unit 310 includes a latch-type sense amplifier 312 that serves to amplify a voltage difference between the positive bit line BL and the sub bit line BLB, and the positive bit line BL and the sub bit. And a precharge unit 314 for equalizing and precharging the line BLB. The sense amplifier 312 receives power through the driving power lines rto and sb.

When the control signals sap and san are activated, the sense amplifier driver 320 supplies the core voltage VCORE to the driving power line rto, and supplies the ground voltage VSS to the driving power line sb when the control signals sap and san are activated. In the initial stage of enabling the sense amplifier, a high voltage is supplied to the driving power supply line rto by connecting the power supply voltage VDD supply terminal and the core voltage VCORE supply terminal by the transistor T3 controlled by the overdriving pulse. The period in which the high voltage is supplied to the driving power line rto (overdriving period) is determined by the width of the overdriving pulse.

The overdriving pulse generator 330 generates an overdriving pulse. The overdriving pulse generator 330 generates a plurality of pulses having different widths, and selects one of the plurality of pulses according to temperature information indicating the temperature of the memory device. Different pulse widths mean that the turn-on intervals of the transistor T3 are different, which means that the lengths of the overdriving intervals are different.

4 is a configuration diagram of an overdriving pulse generator according to an embodiment of the present invention.

As shown in the figure, the overdriving pulse generator of the present invention includes a pulse generator 410 for generating a plurality of pulse signals (pulse1, pulse2, pulse3) of different widths; A temperature information output device 420 for outputting temperature information TEMPA, TEMPB, and TEMPC; And a pulse output unit 430 for selecting and outputting one of the plurality of pulse signals pulse1, pulse2, and pulse3 using the temperature information TEMPA, TEMPB, and TEMPC.

That is, a plurality of pulses (pulse1, 2, 3) having different widths are generated, and one of them is selected and output according to the temperature.

5 is a configuration diagram of an embodiment of the pulse generator 410 of FIG. 4.

The pulse generator 410 generates a plurality of pulse signals by logically combining the input signal with the delayed input signal as in the prior art. However, a plurality of pulses are generated, and the widths of the pulses are different from the conventional ones.

 The pulse generator according to the present invention is an input signal (A node), which is a signal activated by an active command and deactivated by a precharge command. The time when the bit line sense amplifier operation is performed after the active command is performed. Delayed circuit units 510, 511, and 512 connected in series with the inverter, NAND gates 520, 521, and 522 that receive input signals and delayed signals, and NAND gates to delay the signal. And inverters 530, 531, and 532 for outputting pulses by receiving the output signals of the motors 520, 521, and 522.

The delay circuit units 510, 511, and 512 have an odd number of inverters, and their delay values are set differently for each pulse to be generated (pulse 1, 2, 3). In the figure, the difference in the delay values is indicated by the number of inverters. In the embodiment shown in the figure, the inverter is shown as a means for delaying a signal. However, as is well known, a delay using various methods such as an RC delay circuit is possible, and each delay (pulse1, 2, 3) only needs to set a different delay value.

FIG. 6 is a diagram illustrating an embodiment of the temperature information output device 420 of FIG. 4.

Temperature information output device (On Die Thermal Sensor) is a band gap unit 610 for outputting a voltage corresponding to the temperature one-to-one; An analog-digital converter 620 for converting the voltage output from the bandgap unit into a digital code; And a flag signal generator 630 for receiving a digital code and generating a plurality of flag signals that are enabled at a specific temperature.

In detail, the band gap unit 610 has a change in base-emitter Vbe of a bipolar junction transistor (BJT) of about -1.8 mV / in a bandgap circuit which is not affected by temperature or power supply voltage. The temperature is sensed by using a temperature of ℃. The voltage VTEMP corresponding to the temperature is output 1: 1 by amplifying the base-emitter voltage Vbe of the slightly varying bipolar junction transistor. That is, the base-emitter voltage Vbe of the bipolar junction transistor that is lowered as the temperature is outputted is output.

The analog-to-digital converter 620 converts the voltage VTEMP output from the bandgap unit 610 into a digital code and outputs the digital-coded analog coder. Tracking Analog-Digital Convertor is widely used.

The flag signal generator 630 decodes the digital code and outputs a plurality of flag signals TEMPA, TEMPB, and TEMPC indicating a temperature section.

Each flag signal TEMPA, TEMPB, TEMPC is enabled when the temperature is above a certain temperature. In FIG. 7, when each flag signal TEMPA, TEMPB, and TEMPC is enabled, TEMPA, TEMPB, and TEMPC signals are enabled in order from low to high temperatures. Therefore, when TEMPA = 'low', TEMPB = 'low', and TEMPC = 'low', this indicates the lowest temperature range, and when TEMPA = 'high', TEMPB = 'high', TEMPC = 'high' Indicates that the interval is high.

For reference, the flag signals TEMPA, TEMPB, and TEMPC of the temperature information output device are used to adjust the refresh period of the memory device according to the temperature.

8 is a configuration diagram of an embodiment of the pulse output unit 430 of FIG. 4.

As shown in the drawing, the pulse output unit 430 includes: a plurality of pass gates PG1, PG2, and PG3 that receive a plurality of pulse signals pulse1, pulse2, and pulse3 one by one; And a controller 810 that receives a plurality of flag signals TEMPA, TEMPB, and TEMPC to turn on / off the plurality of passgates PG1, PG2, and PG3.

The passgates PG1, PG2, and PG3 may be configured to include a PMOS transistor and an NMOS transistor as commonly used.

The controller 810 includes: inverters 811 and 812 that receive flag signals TEMPA and TEMPB corresponding to the pass gates PG1 and PG2; And pass gates PG1 and PG2 to the outputs of the noah gates 813 and 814, including the NOA gates 813 and 814 that receive the outputs of the inverters 811 and 812 and the flag signals TEMPB and TEMPC. To control. However, the pass gate PG3 corresponding to the highest temperature allows the corresponding flag signal TEMPC to control directly.

The passgates PG1, PG2, and PG3 and the flag signals TEMPA, TEMPB, and TEMPC correspond to one-to-one, respectively, and the controller 810 controls the flag signals TEMPA, B, and When C) is enabled, passgates PG1, 2, and 3 are turned on. That is, when the flag signal TEMPA is enabled, 'high' is output from the NOA gate 813 to turn on the pass gate PG1. However, when a flag signal (a flag signal enabled at a higher temperature, the highest TEMPC is enabled) higher than the flag signals TEMPA, B, and C corresponding to the pass gates PG1, 2, and 3 is enabled, the path is passed. The gates PG1, 2, 3 are turned off. That is, even if TEMPA is enabled, when TEMPB is enabled, the output of the NOA gate 813 is 'low' and does not turn on the passgate PG1. This is because the passgate PG2 should be turned on at this time. Therefore, the passgate PG3 corresponding to the TEMPC enabled at the highest temperature is turned on unconditionally when the TEMPC is enabled because there is no higher flag signal.

In summary, PG1 for (high, low, low) in order of (TEMPA, TEMPB, TEMPC), PG2 for (high, high, low), and PG3 for (high, high, high). It is on.

To adjust the width of the over driving pulse to increase in proportion to the temperature, as shown in the figure, pulse1 may be input to PG1, pulse2 to PG2, and pulse3 to PG3. However, in order to adjust the width of the over driving pulse in inverse proportion to the temperature, pulse3 is input to PG1, pulse2 to PG2 and pulse1 to PG3 differently from the figure.

Therefore, the overdriving pulse generator according to the present invention can adjust the width of the overdriving pulse in proportion to the temperature or inversely.

Depending on the manufacturing process and the characteristics of the transistor used, the circuit design, etc., the overdriving pulse width required by the temperature conditions may be proportional to or inversely proportional to the temperature.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be appreciated by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention described above, it becomes possible to adjust the width of the overdriving pulse in accordance with the temperature.

Therefore, when the overdriving section needs to be longer as the temperature increases, the width of the overdriving pulse is proportional to the temperature, and when the overdriving section becomes shorter as the temperature increases, the width of the overdriving pulse can be adjusted in inverse proportion to the temperature. There is an advantage.

Claims (19)

delete delete delete A pulse generator for generating a plurality of pulse signals having different widths; A temperature information output device for outputting temperature information; And A pulse output unit for selecting and outputting one of the plurality of pulse signals using the temperature information; The temperature information may be a plurality of flag signals enabled at a predetermined temperature, The pulse output unit may include a plurality of pass gates receiving the plurality of pulse signals one by one; And a controller configured to receive the plurality of flag signals and turn on / off the plurality of passgates. The plurality of passgates and the plurality of flag signals correspond one-to-one, And the control unit turns on the passgate when the flag signal corresponding to the passgate is enabled. The method of claim 4, wherein The control unit, And when the flag signal higher than the flag signal corresponding to the passgate, which is enabled at a higher temperature, is enabled, the passgate is turned off. The method of claim 5, The control unit, An inverter receiving the flag signal corresponding to the passgate; And The pass gate is controlled by including an output of the inverter and a noah gate receiving the upper flag signal. And a passgate corresponding to the highest temperature so that a flag signal corresponding to the highest temperature is directly controlled. delete A pulse generator for generating a plurality of pulse signals having different widths; A temperature information output device for outputting temperature information; And A pulse output unit for selecting and outputting one of the plurality of pulse signals using the temperature information; The temperature information output device may include: a band gap part configured to output a voltage corresponding to a temperature in one-to-one correspondence; An analog-digital converter for converting the voltage into a digital code; And a flag signal generator configured to receive the digital code and generate a plurality of flag signals that are enabled at a specific temperature. A pulse generator for generating a plurality of pulse signals having different widths; A temperature information output device for outputting temperature information; And A pulse output unit for selecting and outputting one of the plurality of pulse signals using the temperature information; The pulse generator generates the plurality of pulse signals by logically combining an input signal with a delayed signal and an input signal, the signal being activated in an interval for enabling the bit line sense amplifier, and for each of the plurality of pulse signals. And a delay value of the input signal is different. delete delete delete delete A bit line sense amplifier for amplifying the voltage difference between the bit line pairs; A sense amplifier driver supplying driving power to the bit line sense amplifier for enabling the bit line sense amplifier, supplying the driving power as a high voltage for overdriving at an initial stage and a core voltage thereafter; And An over-driving pulse generator for generating pulses having different widths, selecting one of the plurality of pulses according to temperature information indicating the temperature of the memory device, and outputting the over-driving pulse to determine the size of the overdriving section. and, The over driving pulse generator may include a pulse generator configured to generate a plurality of pulse signals having different widths; A temperature information output device for outputting temperature information; And a pulse output unit configured to select and output one of the plurality of pulse signals using the temperature information. The temperature information may be a plurality of flag signals enabled at a predetermined temperature, The pulse output unit may include a plurality of pass gates receiving the plurality of pulse signals one by one; And a controller configured to receive the plurality of flag signals and turn on / off the plurality of passgates. The plurality of passgates and the plurality of flag signals correspond one-to-one, And the controller turns on the passgate when the flag signal corresponding to the passgate is enabled. The method of claim 14, The control unit, And when the flag signal higher than the flag signal corresponding to the passgate, which is enabled at a higher temperature, is enabled, the passgate is turned off. The method of claim 15, The control unit, An inverter receiving the flag signal corresponding to the passgate; And The pass gate is controlled by including an output of the inverter and a noah gate receiving the upper flag signal. And a pass gate corresponding to the highest temperature so that a flag signal corresponding to the highest temperature is directly controlled. delete A bit line sense amplifier for amplifying the voltage difference between the bit line pairs; A sense amplifier driver supplying driving power to the bit line sense amplifier for enabling the bit line sense amplifier, supplying the driving power as a high voltage for overdriving at an initial stage and a core voltage thereafter; And An over-driving pulse generator for generating pulses having different widths, selecting one of the plurality of pulses according to temperature information indicating the temperature of the memory device, and outputting the over-driving pulse to determine the size of the overdriving section. and, The over driving pulse generator may include a pulse generator configured to generate a plurality of pulse signals having different widths; A temperature information output device for outputting temperature information; And a pulse output unit configured to select and output one of the plurality of pulse signals using the temperature information. The temperature information output device may include: a band gap part configured to output a voltage corresponding to a temperature in one-to-one correspondence; An analog-digital converter for converting the voltage into a digital code; And a flag signal generator configured to receive the digital code and generate a plurality of flag signals that are enabled at a specific temperature. A bit line sense amplifier for amplifying the voltage difference between the bit line pairs; A sense amplifier driver supplying driving power to the bit line sense amplifier for enabling the bit line sense amplifier, supplying the driving power as a high voltage for overdriving at an initial stage and a core voltage thereafter; And An over-driving pulse generator for generating pulses having different widths, selecting one of the plurality of pulses according to temperature information indicating the temperature of the memory device, and outputting the over-driving pulse to determine the size of the overdriving section. and, The over driving pulse generator may include a pulse generator configured to generate a plurality of pulse signals having different widths; A temperature information output device for outputting temperature information; And a pulse output unit configured to select and output one of the plurality of pulse signals using the temperature information. The pulse generator generates the plurality of pulse signals by logically combining an input signal with a delayed signal and an input signal, the signal being activated in an interval for enabling the bit line sense amplifier, and for each of the plurality of pulse signals. And a delay value of the input signal is different.

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