JP4192504B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device.
[0002]
[Prior art]
FIG. 5 is a circuit diagram showing a configuration of a conventional semiconductor memory device. As shown in FIG. 5, the conventional semiconductor memory device includes a bit line pair BL0, / BL0 and a dummy bit line pair DBL, / DBL, a word line WL0, a precharge line PRE, an equalize line EQ, a column select line WR, a sense. An enable line SE, a memory cell MC, a dummy memory cell DMC, a sense amplifier SA, a dummy sense amplifier DSA, latch circuits 51 and 52, and a write driver 53 are provided.
[0003]
In the write operation of the semiconductor memory device having such a configuration, first, the precharge line PRE is activated to precharge the bit line pair BL0, / BL0, and the equalize line EQ is activated to activate the bit line. The potentials of the line BL0 and the complementary bit line / BL0 are made equal.
[0004]
Thereafter, when the input data DI is stored in the latch circuit 52 and the column select line WR is activated, the input data is transferred to the bit line pair BL0, / BL0 by the write driver 53 in a state where the sense amplifier SA is activated. And supplied to the memory cell MC.
[0005]
On the other hand, in the read operation, first, the precharge line PRE is activated to precharge the bit line pair BL0, / BL0, and the equalize line EQ is activated to activate the bit line BL0 and the complementary bit line / BL0. Are made equal to each other.
[0006]
When the word line WL0 is activated, the data stored in the memory cell MC is read to the bit line pair BL0, / BL0, and the difference voltage generated in the bit line pair BL, / BL0 is read by the sense amplifier SA. Amplified. At this time, the read data obtained by the amplification is stored in the latch circuit 51 and output from the latch circuit 51 to the outside as output data DO.
[0007]
Here, in general, in a semiconductor memory device such as a DRAM in which retained data is destroyed when data is read, data is rewritten to the memory cell MC after the potential difference between the bit line pair BL0 and / BL0 is amplified and maximized. Thereafter, normal operation is realized by allowing the precharge operation of the bit line pair BL0, / BL0 in the next cycle.
[0008]
The execution permission timing of the precharge operation is determined by activating the precharge execution permission signal / PRE. The precharge execution permission signal / PRE is detected by, for example, a sense amplifier as shown in FIG. The sense amplifier enable signal / SAE for starting SA is generated by being delayed for a predetermined time by the timing adjustment circuit 40 including the inverting circuits 41 and 42 and the capacitive elements C1 and C2.
[0009]
At this time, the delay amount for determining the execution permission timing of the precharge operation depends on the drive capability of the transistors constituting the inverting circuits 41 and 42 and the size of the capacitors C1 and C2. On the other hand, the timing at which the potential difference between the bit line pair BL0 and / BL0 is maximized (full amplitude) is mainly connected to the wiring resistance and wiring capacitance of the bit line pair BL0 and / BL0 or the bit line pair BL0 and / BL0. Depends on the drive capability of the access transistor.
[0010]
Accordingly, since both timings are determined by the parts formed independently, the delay amount for determining the execution permission timing of the precharge operation has a sufficient margin considering the process variation in the part. Therefore, there is a problem that the high-speed operation of the semiconductor memory device is hindered.
[0011]
In consideration of such a problem, in the conventional semiconductor memory device shown in FIG. 5, the dummy memory cell DMC and the dummy bit line pair DBL, / DBL are processed in the same process as the memory cell MC and the bit line pair BL0, / BL0. Is formed. The precharge operation execution permission timing is determined based on the dummy output data DS obtained by sensing the data read from the dummy memory cell DMC to the dummy bit line pair DBL, / DBL by the dummy sense amplifier DSA. It is determined.
[0012]
[Problems to be solved by the invention]
However, in the conventional semiconductor memory device shown in FIG. 5, the precharge timing is determined by the potential difference between the dummy bit line pair DBL and / DBL as described above, and the dummy bit line DBL or the complementary dummy bit line / DBL is Since it is determined regardless of the absolute value of the potential, a memory such as a dynamic random access memory (DRAM) in which data is destroyed at the time of reading has a problem that a so-called retention failure in which normal data reading is not performed occurs. is there. In the following, this problem will be described in more detail.
[0013]
FIG. 7 is a timing chart showing an operation of the conventional semiconductor memory device shown in FIG. Here, FIG. 7A shows potential changes of the equalize line EQ, the sense enable line SE, and the word line WL0, and FIG. 7B shows the cell potential of the memory cell MC and the potentials of the bit line pairs BL0 and / BL0. FIG. 7C shows the time change of the cell potential of the dummy memory cell DMC and the potential of the dummy bit line pair DBL, / DBL.
[0014]
In the conventional semiconductor memory device shown in FIG. 5, as shown in FIGS. 7 (a) and 7 (c), at time T1 before the potential difference between the dummy bit line pair DBL, / DBL becomes full amplitude, When the line WL0 is deactivated, data lower than the power supply voltage VCC is rewritten to the memory cell MC at time T2, as shown in FIG. 7B.
[0015]
At this time, in a volatile memory such as a DRAM, the charge accumulated in the memory cell MC leaks. Therefore, if the battery is not charged until it reaches the power supply voltage VCC at the time of rewriting, inverted data is read out. Retention failure may occur.
[0016]
Further, in the conventional semiconductor memory device shown in FIG. 5, it is necessary to form the dummy bit line pair DBL, / DBL and the dummy memory cell DMC connected to the word line WL0 by the same process as the memory cell array. There is also.
[0017]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device that reliably realizes high-speed data reading and writing with a simple configuration.
[0018]
[Means for Solving the Problems]
An object of the present invention is to provide a plurality of memory cells , a bit line pair connected to the memory cell, a dummy bit line having the same wiring resistance and wiring capacitance as one of the bit line pair, and the bit from the memory cell to the bit. Amplifying means for amplifying data read to the line pair ; dummy bit line driving means for driving the dummy bit line in response to an enable signal for activating the amplifying means; a preset reference potential; Comparing means for comparing the potential of the dummy bit line and the comparison by the comparing means permit a precharge operation for the bit line pair after it is determined that the potential of the dummy bit line has reached the reference potential. It is achieved by providing a control unit, a semi-conductor memory device Ru comprising a.
[0019]
According to such a means, the timing at which the potential difference of the bit line pair is amplified to the maximum by the amplifying means and the data is rewritten to the memory cell is determined without allowing for a margin due to process variations. The timing for permitting the execution of the precharge operation for the pair can be reliably maximized with a simple configuration.
[0020]
In the semiconductor memory device of the present invention, the dummy bit line has the same wiring resistance and wiring capacitance as one of the bit line pairs . Here, if the dummy bit line driving means drives the dummy bit line with the same driving force as that when the amplifying means drives the bit line pair, the potential fluctuation of the dummy bit line is detected as one potential of the bit line pair. Since the variation can be approximated, the ideal execution permission timing of the precharge operation can be accurately determined.
[0021]
Further, if the comparison means is inactivated when the control means permits the precharge operation for the bit line pair, the power consumption of the comparison means once the precharge operation is permitted can be reduced. Can do.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.
[0023]
FIG. 1 is a block diagram showing an overall configuration of a semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 1, a semiconductor memory device 1 according to an embodiment of the present invention includes a column unit 2 and a data bus 3, a sense amplifier unit 4, a memory cell unit 5, a control unit 6, a row decoder 7, and an external circuit. 10. The column unit 2 includes a column address decoder and a read amplifier that amplifies data read to the data bus 3.
[0024]
Here, the control unit 6 is connected to the external circuit 10, and the column unit 2, the sense amplifier unit 4, and the row decoder 7 are all connected to the control unit 6. The column section 2 and the sense amplifier section 4 are connected by a data bus 3, the bit line pair BL, / BL of the memory cell section 5 is connected to the sense amplifier section 4, and the word line WL is connected to the row decoder 7. Is done.
[0025]
FIG. 2 is a circuit diagram showing a configuration of memory cell unit 5 shown in FIG. As shown in FIG. 2, the memory cell unit 5 is, for example, a volatile DRAM, and includes word lines WL0 to WLn, bit line pairs BL0, / BL0 to BLm, / BLm, one of bit line pairs, and a word line. And memory cells MC00 to MCnm connected to each other. Each of the memory cells MC00 to MCnm is composed of one transistor and one capacitor element as shown in FIG. 2, for example.
[0026]
The outline of the operation of the semiconductor memory device having the above configuration will be described below.
[0027]
First, when an active command Cd and an address AD are supplied from the external circuit 10 to the control unit 6, the control unit 6 supplies a row address RAD to the row decoder 7 in accordance with the command and address, and the sense amplifier unit 4 is disabled. An active bit line enable signal BLE is supplied. The sense amplifier unit 4 equalizes the bit line pair BL, / BL when the bit line enable signal BLE supplied from the control unit 6 is activated, and the bit line pair BL, / BL when the bit line enable signal BLE is inactivated. Disconnect the electrical connection between the BLs.
[0028]
Next, the row decoder 7 decodes the supplied row address RAD and selectively activates the word line WL to a high level according to the row address RAD. Here, when the word lines WL0 to WLn shown in FIG. 2 are selectively activated, the bit line pairs BL0 and / BL0 to BL0 according to the data held in the memory cells connected to the activated word lines. A potential difference is generated between BLm and / BLm.
[0029]
Then, after the potential difference occurs, the control unit 6 supplies the activated sense amplifier enable signal / SAE to the sense amplifier unit 4, and the sense amplifier unit 4 responds to the sense amplifier enable signal / SAE to the bit line pair BL0. , / BL0 to BLm, / BLm are amplified to generate 0 or 1 data.
[0030]
Through such a series of operations, the semiconductor memory device 1 shown in FIG. 1 shifts from the standby state to the active state. In the read operation, after the active state is established, the column unit 2 selectively transfers the data generated by the sense amplifier unit 4 to the data bus 3 according to the column address CAD, and passes through the control unit 6. Output to the external circuit 10.
[0031]
On the other hand, in the write operation, after entering the active state, the write data received from the external circuit 10 by the control unit 6 is selectively transferred to the data bus 3 by the column unit 2 according to the column address CAD. The write data is written into the unit 5.
[0032]
After the read or write operation as described above is completed, a precharge command is supplied from the external circuit 10 to the control unit 6, and the word line WL is deactivated to a low level according to the command, and the sense amplifier enable Signal / SAE is inactivated to a high level. Further, the bit line enable signal BLE is activated to a high level, and the semiconductor memory device 1 changes from the active state to the standby state.
[0033]
Here, in the case of a so-called automatic precharge type semiconductor memory device that automatically executes precharge, the precharge command as described above is supplied from the external circuit 10 when transitioning from the active state to the standby state. Although not required, an automatic precharge execution permission signal / PRE is generated in the control unit 6 instead of the precharge command. At this time, the automatic precharge execution permission signal / PRE is generated by the timing adjustment circuit 20 included in the control unit 6 based on the sense amplifier enable signal / SAE or the like. Hereinafter, the timing adjustment circuit 20 will be described in detail with reference to FIG.
[0034]
As shown in FIG. 3, the timing adjustment circuit 20 includes a dummy bit line 22, a current mirror circuit 25, an N-channel MOS transistor NT1, a P-channel MOS transistor PT1, inversion circuits 21, 28, 31, a NOR circuit 27, and a NAND circuit. 29,30. Current mirror circuit 25 includes N channel MOS transistors NT2 to NT4 and P channel MOS transistors PT2 and PT3.
[0035]
In current mirror circuit 25, the sources of P channel MOS transistors PT2 and PT3 are commonly connected to the power supply voltage node, the gates of P channel MOS transistors PT2 and PT3 are interconnected, and the drain of P channel MOS transistor PT2 is connected. Connected to. N channel MOS transistor NT2 is connected to P channel MOS transistor PT2, and N channel MOS transistor NT3 is connected to P channel MOS transistor PT3. Further, the sources of N channel MOS transistors NT2 and NT3 are commonly connected to the drain of N channel MOS transistor NT4, and the source of N channel MOS transistor NT4 is connected to the ground node.
[0036]
On the other hand, the inverting circuit 21 and the NOR circuit 27 are supplied with a sense amplifier enable signal / SAE for activating the sense amplifier, and the output node of the inverting circuit 21 is connected to the dummy bit line 22. An N channel MOS transistor NT1 is connected between the output node of the inverting circuit 21 and the ground node, and a bit line enable signal BLE is supplied to the gate of the N channel MOS transistor NT1 and the inverting circuit 28.
[0037]
The other end of the dummy bit line 22 is connected to the gate of the N-channel MOS transistor NT3, and the reference voltage Vref is supplied to the gate of the N-channel MOS transistor NT2. The output node of NOR circuit 27 is connected to the gate of N channel MOS transistor NT4 and the gate of P channel MOS transistor PT1.
[0038]
In the timing adjustment circuit 20 having the above configuration, the dummy bit line 22 is made of the same material as the bit line pair BL, / BL formed in the memory cell portion 5 and has the same wiring resistance and wiring capacitance. . The dummy bit line 22 is driven by a transistor constituting the inverting circuit 21, and the transistor size of the transistor is the same as the transistor size of the transistor constituting the sense amplifier unit 4. As a result, the dummy bit line 22 can have the same electrical characteristics as the bit line pair BL, / BL in the memory cell portion 5.
[0039]
Hereinafter, the operation of the timing adjustment circuit 20 shown in FIG. 3 will be described in detail with reference to the timing chart of FIG. 4A shows potential changes of the bit line enable signal BLE, the sense amplifier enable signal / SAE, and the word line WL0, and FIG. 4B shows the cell potential of the memory cell MC and the bit line pair BL0, / BL0. 4C shows a change in potential of the dummy bit line 22, and FIG. 4D shows an automatic precharge execution permission signal / PRE.
[0040]
In the initial state up to time T1, as shown in FIG. 4A, the bit line enable signal BLE is set to the high level (H), and the potentials of the bit line pairs are equalized. At this time, as shown in FIG. 4C, the potential of the dummy bit line 22 is set to the ground level by turning on the N-channel MOS transistor NT1, and the low level (L) signal is output from the inverting circuit 28 to the NAND level. Since it is supplied to the circuit 30, the automatic precharge execution permission signal / PRE is set to the high level (H) as shown in FIG.
[0041]
At time T1, the bit line enable signal BLE transitions to a low level, thereby disconnecting the electrical connection between the bit line pair. Thereafter, as shown in FIGS. 4A and 4B, when the word line WL0 is activated at time T2, the data held in the memory cell MC is read to the bit line BL0, and the time At T3, the sense amplifier enable signal / SAE is activated to a low level, thereby amplifying the potential difference between the bit line pair BL0 and / BL0.
[0042]
As shown in FIG. 4A, since the bit line enable signal BLE is at a low level between time T1 and time T7, the N-channel MOS transistor NT1 is turned off and the inverter circuit 28 A high level signal is supplied to the NAND circuit 30. However, since the sense amplifier enable signal / SAE is kept at a high level until time T3, a low level signal is supplied from the inverting circuit 21 to the dummy bit line 22. Therefore, as shown in FIG. 4C, the potential of the dummy bit line 22 is set to the ground level (GND) until time T3.
[0043]
Since the low level signal is output from the NOR circuit 27 until time T3, the P-channel MOS transistor PT1 is turned on, so that the output node of the current mirror circuit 25 is set to the high level. Therefore, since the output signal of the NAND circuit 29 is at a low level, the automatic precharge execution permission signal / PRE is latched at a high level as shown in FIG.
[0044]
Here, when the sense amplifier enable signal / SAE is activated to the low level at time T3 as described above, the output signal of the inverting circuit 21 is set to the high level, so that the dummy signal as shown in FIG. The potential of the bit line 22 rises.
[0045]
When sense amplifier enable signal / SAE is activated to a low level, the signal output from NOR circuit 27 is set to a high level, so that P channel MOS transistor PT1 is turned off. Since the node is held at the high level, the automatic precharge execution permission signal / PRE is set to the high level as shown in FIG. Further, when the signal output from the NOR circuit 27 is set to the high level, the N-channel MOS transistor NT4 is turned on and the current mirror circuit 25 is activated.
[0046]
Here, as shown in FIG. 4C, when the potential of the dummy bit line 22 exceeds the reference voltage Vref at time T4, the current mirror circuit 25 passes through the N-channel MOS transistor NT3 and the N-channel MOS transistor NT4. Since current flows through the ground node, the output node of the current mirror circuit 25 is at a low level. At this time, since the output of the NAND circuit 29 is at a high level, the automatic precharge execution permission signal / PRE is transitioned to a low level and activated as shown in FIG.
[0047]
At time T5 after activation of the automatic precharge execution permission signal / PRE, the word line WL0 is inactivated as shown in FIG. 4A. At this timing, FIG. ), Since the potential difference between the bit line pair BL0 and / BL0 has a full amplitude, the data of the power supply voltage VCC is rewritten in the memory cell MC.
[0048]
Thereafter, as shown in FIG. 4A, the sense amplifier enable signal / SAE transitions to a high level at time T6. However, since the output of the NAND circuit 29 is set to a high level, FIG. As shown, the automatic precharge execution permission signal / PRE is latched at the low level.
[0049]
Then, as shown in FIG. 4A, when the bit line enable signal BLE is activated to a high level at time T7, the potentials of the bit line pair BL0, / BL0 as shown in FIG. 4B. Is equalized and N channel MOS transistor NT1 is turned on, so that the potential of dummy bit line 22 is lowered to the ground level as shown in FIG. At this time, since a low level signal is supplied from the inverting circuit 28 to the NAND circuit 30, the automatic precharge execution permission signal / PRE transitions to a high level as shown in FIG.
[0050]
As described above, in the timing adjustment circuit 20 shown in FIG. 3, the activation timing of the automatic precharge execution permission signal / PRE is the same as the time T4 that is a predetermined time after the time T3 when the sense amplifier enable signal / SAE is activated. Adjusted. Here, since the automatic precharge execution permission signal / PRE is activated only when the potential of the dummy bit line 22 exceeds the reference voltage Vref, data is transferred to the memory cell MC between time T4 and time T5. At the time of rewriting, the bit line pair BL0, / BL0 also has full amplitude, and as a result, the power supply voltage level (VCC) data can be reliably rewritten to the memory cell MC. This is effective in avoiding a retention failure in a memory such as a DRAM that causes destruction of retained data when data is read. After the rewriting, the bit line pair is precharged for the next cycle operation.
[0051]
Further, in the timing adjustment circuit 20 shown in FIG. 3, the magnitude of the reference voltage Vref supplied to the gate of the N-channel MOS transistor NT2 constituting the current mirror circuit 25 is changed, and the potential of the dummy bit line 22 is changed. By changing the arrival time to the reference voltage Vref, it is possible to adjust the activation timing of the automatic precharge execution permission signal / PRE.
[0052]
In the timing adjustment circuit 20 shown in FIG. 3, once the automatic precharge execution permission signal / PRE is activated to the low level, the output of the NOR circuit 27 becomes the low level, so that the N-channel MOS transistor NT4 The current mirror circuit 25 is deactivated by being turned off. As a result, useless current consumption in the current mirror circuit 25 is reduced after the automatic precharge execution permission signal / PRE is activated.
[0053]
As described above, according to the semiconductor memory device of the embodiment of the present invention, the activation timing of the automatic precharge execution permission signal / PRE is determined by comparing the potential of the dummy bit line 22 with the reference voltage Vref. It is necessary to consider the margin required due to process variations of the bit line pair BL, / BL, etc. and the retention failure can be avoided, and the activation timing of the automatic precharge execution permission signal / PRE can be surely maximized.
[0054]
Therefore, according to the semiconductor memory device of the embodiment of the present invention, high-speed data reading / writing can be reliably realized with a simple configuration that does not require dummy memory cells.
[0055]
【The invention's effect】
According to the semiconductor memory device of the present invention, the execution permission timing of the precharge operation for the bit line pair can be surely maximized with a simple configuration, and high-speed data reading / writing to the memory cell can be reliably realized. Can do.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a memory cell unit shown in FIG. 1;
FIG. 3 is a circuit diagram showing a configuration of a timing adjustment circuit included in the control unit shown in FIG. 1;
4 is a timing chart showing an operation of the semiconductor memory device shown in FIG. 1. FIG.
FIG. 5 is a circuit diagram showing a configuration of a conventional semiconductor memory device.
FIG. 6 is a circuit diagram showing a configuration of a conventional timing adjustment circuit.
FIG. 7 is a timing chart showing an operation of the semiconductor memory device shown in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor memory device, 2 Column part, 3 Data bus, 4 Sense amplifier part, 5 Memory cell part, 6 Control part, 7 Row decoder, 10 External circuit, 20, 40 Timing adjustment circuit, 21, 28, 31, 41, 42 inversion circuit, 22, DBL dummy bit line, 25 current mirror circuit, 27 NOR circuit, 29, 30 NAND circuit, 51, 52 latch circuit, 53 write driver, MC00, MC10, MCn0, MC0m, MC1m, MCnm, MC memory Cell, BL0, BLm bit line, / BL0, / BLm complementary bit line, WL0 to WLn word line, / DBL complementary dummy bit line, NT1 to NT4 N channel MOS transistor, PT1 to PT3 P channel MOS transistor, C1, C2 capacitance Element, DMC dummy memory cell, DSA dummy Nsuanpu, SA the sense amplifier, PRE precharge line, EQ equalizing line, WR column select lines, SE sense enable line.

Claims (3)

A plurality of memory cells ;
A pair of bit lines connected to the memory cell ;
A dummy bit line having the same wiring resistance and wiring capacitance as one of the bit line pairs ;
Amplifying means for amplifying data read from the memory cell to the bit line pair;
Dummy bit line driving means for driving the dummy bit line in response to an enable signal for activating the amplifying means;
A comparison means for comparing a preset reference potential with the potential of the dummy bit line;
Control means for permitting a precharge operation for the bit line pair after it is determined in the comparison by the comparison means that the potential of the dummy bit line has reached the reference potential ;
Ru comprising a semi-conductor memory device. The semiconductor memory device according to claim 1, wherein the dummy bit line driving unit drives the dummy bit line with the same driving force as when the amplification unit drives the bit line pair. The semiconductor memory device according to claim 1, wherein the comparison unit is deactivated when the control unit permits a precharge operation for the bit line pair.

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