JP2004014021A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device enabling the surely high speed reading and writing of data by a simple constitution. <P>SOLUTION: This device is a semiconductor memory device provided with a plurality of memory cells, a pair of bit lines, and a sense amplifier amplifying data read to the pair of bit lines, and further the device is provided with a dummy bit line 22, an reversing circuit 21 driving the dummy bit line 22 in accordance with a sense amplifier enable-signal /SAE activating the sense amplifier, a current mirror circuit 25 comparing the potential of a reference voltage Vref previously set with the potential of the dummy bit line 22, and NAND circuits 29, 30 activating an automatic pre-charge performance permitting signal /PRE permitting a pre-charge operation for the pair of bit lines after it is determined that the potential of the dummy line 22 reaches the reference voltage Vref in comparison by the current mirror circuit 25. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device.
[0002]
[Prior art]
FIG. 5 is a circuit diagram showing a configuration of a conventional semiconductor memory device. As shown in FIG. 5, the conventional semiconductor memory device includes a pair of bit lines BL0 and / BL0 and a pair of dummy bit lines DBL and / DBL, a word line WL0, a precharge line PRE, an equalize line EQ, a column select line WR, and a sense. It includes an enable line SE, a memory cell MC, a dummy memory cell DMC, a sense amplifier SA, a dummy sense amplifier DSA, latch circuits 51 and 52, and a write driver 53.
[0003]
In the write operation of the semiconductor memory device having such a configuration, the bit line pair BL0 and / BL0 is precharged by activating the precharge line PRE, and the bit line is activated by activating the equalize line EQ. The potential of the line BL0 and the potential of the complementary bit line / BL0 are made equal.
[0004]
Thereafter, when the input data DI is stored in the latch circuit 52 and the column select line WR is activated, the input data is sent to the bit line pair BL0, / BL0 by the write driver 53 in a state where the sense amplifier SA is activated. The data is supplied and written to the memory cell MC.
[0005]
On the other hand, in the read operation, the bit line pair BL0, / BL0 is precharged by activating the precharge line PRE, and the bit line BL0 and the complementary bit line / BL0 are activated by activating the equalize line EQ. Are made equal.
[0006]
When the word line WL0 is activated, the data stored in the memory cell MC is read out to the bit line pair BL0, / BL0, and the difference voltage generated on the bit line pair BL, / BL0 is sensed by the sense amplifier SA. Amplified. At this time, the read data obtained by the amplification is stored in the latch circuit 51, and is output from the latch circuit 51 to the outside as output data DO.
[0007]
Here, in general, in a semiconductor memory device such as a DRAM in which held data is destroyed at the time of data reading, data is rewritten to the memory cell MC after the potential difference between the pair of bit lines BL0 and / BL0 is amplified and maximized. Thereafter, the precharge operation of the bit line pair BL0, / BL0 in the next cycle is permitted, thereby realizing a normal operation.
[0008]
Then, the execution permission timing of the precharge operation is determined by activating the precharge execution permission signal / PRE. The precharge execution permission signal / PRE is, for example, as shown in FIG. The sense amplifier enable signal / SAE for activating SA is generated by delaying the sense amplifier enable signal / SAE for a predetermined time by the timing adjustment circuit 40 including the inversion circuits 41 and 42 and the capacitance elements C1 and C2.
[0009]
At this time, the amount of delay for determining the execution permission timing of the precharge operation depends on the driving capability of the transistors forming the inverting circuits 41 and 42 and the magnitude of the capacitance of the capacitance elements C1 and C2. On the other hand, the timing at which the potential difference between the bit line pair BL0 and / BL0 is maximized (full amplitude) is mainly connected to the wiring resistance and the wiring capacitance of the bit line pair BL0 and / BL0 or to the bit line pair BL0 and / BL0. Depends on the driving capability of the access transistor.
[0010]
Therefore, since the above-mentioned timings are respectively determined by the independently formed portions, the delay amount for determining the execution permission timing of the precharge operation has a sufficient margin in consideration of the process variation in the portion. Therefore, there is a problem that high-speed operation of the semiconductor memory device is hindered.
[0011]
In consideration of such a problem, in the conventional semiconductor memory device shown in FIG. 5, in the same process as memory cell MC and bit line pair BL0, / BL0, dummy memory cell DMC and dummy bit line pair DBL, / DBL are used. Is formed. Then, based on dummy output data DS obtained by sensing data read from dummy memory cell DMC to dummy bit line pair DBL, / DBL by dummy sense amplifier DSA, execution permission timing of the precharge operation is determined. It is determined.
[0012]
[Problems to be solved by the invention]
However, in the conventional semiconductor memory device shown in FIG. 5, the precharge timing is determined by the potential difference between the pair of dummy bit lines DBL and / DBL as described above, and the timing of the dummy bit line DBL or the complementary dummy bit line / DBL is determined. Since the potential is determined irrespective of the absolute value of the potential, in a memory such as a dynamic random access memory (DRAM) in which data is destroyed at the time of reading, there is a problem that a so-called retention failure occurs in which normal data reading is not performed. is there. Hereinafter, this problem will be described in more detail.
[0013]
FIG. 7 is a timing chart showing an operation of the conventional semiconductor memory device shown in FIG. Here, FIG. 7A shows the potential changes of the equalize line EQ, the sense enable line SE, and the word line WL0, and FIG. 7B shows the cell potential of the memory cell MC and the potential of the bit line pair BL0, / BL0. FIG. 7C shows a time change of the cell potential of the dummy memory cell DMC and a time change of the potential of the dummy bit line pair DBL and / DBL, respectively.
[0014]
In the conventional semiconductor memory device shown in FIG. 5, as shown in FIGS. 7 (a) and 7 (c), the word at time T1 before the potential difference between the pair of dummy bit lines DBL and / DBL becomes full amplitude. When the line WL0 is inactivated, as shown in FIG. 7B, at time T2, data lower than the power supply voltage VCC is rewritten in the memory cell MC.
[0015]
At this time, in a volatile memory such as a DRAM, the charge stored in the memory cell MC leaks, and if the charge is not performed until the power supply voltage VCC is reached during rewriting, inverted data is read. Retention defects may occur.
[0016]
Further, in the conventional semiconductor memory device shown in FIG. 5, there is a problem that the dummy memory cell DMC connected to the dummy bit line pair DBL, / DBL and the word line WL0 needs to be formed by the same process as the memory cell array. There is also.
[0017]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to provide a semiconductor memory device that reliably realizes high-speed data reading and writing with a simple configuration.
[0018]
[Means for Solving the Problems]
An object of the present invention is a semiconductor memory device comprising a plurality of memory cells and a bit line pair connected to the memory cells, and an amplifying means for amplifying data read from the memory cells to the bit line pairs, A dummy bit line, a dummy bit line driving unit that drives the dummy bit line according to an enable signal that activates the amplification unit, a comparison unit that compares a preset reference potential with a potential of the dummy bit line, A semiconductor memory device comprising: control means for permitting a precharge operation on a pair of bit lines after it is determined in comparison by a comparing means that the potential of a dummy bit line has reached a reference potential. This is achieved by:
[0019]
According to such means, the timing at which the potential difference between the bit line pair is amplified to the maximum by the amplifying means and the data is rewritten to the memory cell is determined without anticipating the margin due to the process variation. The timing at which the execution of the precharge operation for the pair is permitted can be reliably made the fastest with a simple configuration.
[0020]
Here, the dummy bit line has the same wiring resistance and the same wiring capacitance as one of the bit line pairs, or the dummy bit line driving means drives the dummy bit line with the same driving force as when the amplifying means drives the bit line pair. If driving is performed, the potential change of the dummy bit line can be approximated to the potential change of one of the bit line pairs, so that the ideal execution permission timing of the precharge operation can be accurately determined.
[0021]
Further, if the comparing means is deactivated when the control means permits the precharge operation for the bit line pair, it is possible to reduce the power consumption of the comparing means once the precharge operation is permitted. Can be.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.
[0023]
FIG. 1 is a block diagram showing an overall configuration of a semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 1, a semiconductor memory device 1 according to an embodiment of the present invention includes a column unit 2 and a data bus 3, a sense amplifier unit 4, a memory cell unit 5, a control unit 6, a row decoder 7, an external circuit 10 is provided. Note that the column unit 2 includes a column address decoder and a read amplifier that amplifies data read to the data bus 3.
[0024]
Here, the control section 6 is connected to the external circuit 10, and the column section 2, the sense amplifier section 4 and the row decoder 7 are all connected to the control section 6. The column section 2 and the sense amplifier section 4 are connected by the data bus 3, the bit line pair BL and / BL of the memory cell section 5 are connected to the sense amplifier section 4, and the word line WL is connected to the row decoder 7. Is done.
[0025]
FIG. 2 is a circuit diagram showing a configuration of the memory cell unit 5 shown in FIG. As shown in FIG. 2, the memory cell unit 5 is, for example, a volatile DRAM, and includes one of a word line WL0 to WLn, a bit line pair BL0, / BL0 to BLm, / BLm, a bit line pair, and a word line. And the memory cells MC00 to MCnm connected to the memory cells MC00 to MCnm. Note that each of the memory cells MC00 to MCnm is composed of, for example, one transistor and one capacitor as shown in FIG.
[0026]
Hereinafter, an outline of the operation of the semiconductor memory device having the above configuration will be described.
[0027]
First, when the active command Cd and the address AD are supplied from the external circuit 10 to the control unit 6, the control unit 6 supplies a row address RAD to the row decoder 7 in accordance with the command and the address, and sends the row address RAD to the sense amplifier unit 4. An active bit line enable signal BLE is supplied. The sense amplifier unit 4 equalizes the bit line pair BL and / BL when the bit line enable signal BLE supplied from the control unit 6 is activated, and equalizes the bit line pair BL and / BL when inactivated. Disconnect the electrical connection between the BLs.
[0028]
Next, the row decoder 7 decodes the supplied row address RAD, and selectively activates the word line WL to a high level according to the row address RAD. Here, when the word lines WL0 to WLn shown in FIG. 2 are selectively activated, bit line pairs BL0, / BL0 to BL0 according to the data held by the memory cells connected to the activated word lines. A potential difference occurs between BLm and / BLm.
[0029]
After the potential difference is generated, the control unit 6 supplies the activated sense amplifier enable signal / SAE to the sense amplifier unit 4, and the sense amplifier unit 4 responds to the sense amplifier enable signal / SAE so that the bit line pair BL0 , / BL0 to BLm and / BLm are amplified to generate 0 or 1 data.
[0030]
By such a series of operations, the semiconductor memory device 1 shown in FIG. 1 transitions from the standby state to the active state. Then, in the read operation, after the active state, the data generated by the sense amplifier unit 4 is selectively transferred to the data bus 3 by the column unit 2 in accordance with the column address CAD. Output to the external circuit 10.
[0031]
On the other hand, in the write operation, after the active state, the control section 6 selectively transfers the write data received from the external circuit 10 to the data bus 3 in accordance with the column address CAD. The write data is written to the unit 5.
[0032]
After the above-described read or write operation is completed, a precharge command is supplied from the external circuit 10 to the control unit 6, and the word line WL is inactivated to a low level in response to the command, and the sense amplifier is enabled. The signal / SAE is inactivated to a high level. Further, the bit line enable signal BLE is activated to a high level, and the semiconductor memory device 1 transitions from an active state to a standby state.
[0033]
Here, in the case of a so-called automatic precharge type semiconductor memory device that automatically executes precharge, the above-described precharge command is supplied from the external circuit 10 when transitioning from the active state to the standby state. Although not necessary, the control unit 6 generates an automatic precharge execution permission signal / PRE in place of the precharge command. At this time, the automatic precharge execution permission signal / PRE is generated by the timing adjustment circuit 20 included in the control unit 6 based on the sense amplifier enable signal / SAE and the like. Hereinafter, the timing adjustment circuit 20 will be described in detail with reference to FIG.
[0034]
As shown in FIG. 3, the timing adjustment circuit 20 includes a dummy bit line 22, a current mirror circuit 25, an N-channel MOS transistor NT1, a P-channel MOS transistor PT1, inverting circuits 21, 28, 31, a NOR circuit 27, and a NAND circuit. 29 and 30. The current mirror circuit 25 includes N-channel MOS transistors NT2 to NT4 and P-channel MOS transistors PT2 and PT3.
[0035]
In current mirror circuit 25, the sources of P-channel MOS transistors PT2 and PT3 are commonly connected to a power supply voltage node, the gates of P-channel MOS transistors PT2 and PT3 are connected to each other, and the drain of P-channel MOS transistor PT2 is connected. Connected to. Further, N-channel MOS transistor NT2 is connected to P-channel MOS transistor PT2, and N-channel MOS transistor NT3 is connected to P-channel MOS transistor PT3. Further, the sources of N-channel MOS transistors NT2 and NT3 are commonly connected to the drain of N-channel MOS transistor NT4, and the source of N-channel MOS transistor NT4 is connected to the ground node.
[0036]
On the other hand, a sense amplifier enable signal / SAE for activating the sense amplifier is supplied to the inversion circuit 21 and the NOR circuit 27, and an output node of the inversion circuit 21 is connected to the dummy bit line 22. An N-channel MOS transistor NT1 is connected between the output node of the inversion circuit 21 and the ground node, and a bit line enable signal BLE is supplied to the gate of the N-channel MOS transistor NT1 and the inversion circuit 28.
[0037]
The other end of the dummy bit line 22 is connected to the gate of the N-channel MOS transistor NT3, and the gate of the N-channel MOS transistor NT2 is supplied with the reference voltage Vref. The output node of NOR circuit 27 is connected to the gate of N-channel MOS transistor NT4 and the gate of P-channel MOS transistor PT1.
[0038]
In the timing adjustment circuit 20 having the above configuration, the dummy bit line 22 is made of the same material as the bit line pair BL, / BL formed in the memory cell portion 5 and has the same wiring resistance and wiring capacitance. . The dummy bit line 22 is driven by a transistor forming the inverting circuit 21, and the size of the transistor is the same as the size of the transistor forming the sense amplifier unit 4. This allows the dummy bit line 22 to have the same electrical characteristics as the bit line pair BL and / BL in the memory cell unit 5.
[0039]
Hereinafter, the operation of the timing adjustment circuit 20 shown in FIG. 3 will be described in detail with reference to the timing chart of FIG. 4A shows the bit line enable signal BLE, the sense amplifier enable signal / SAE, and the potential change of the word line WL0, and FIG. 4B shows the cell potential of the memory cell MC and the bit line pair BL0, / BL0. 4 (c) shows the potential change of the dummy bit line 22, and FIG. 4 (d) shows the automatic precharge execution permission signal / PRE.
[0040]
In the initial state until time T1, as shown in FIG. 4A, the bit line enable signal BLE is set to the high level (H), and the potential of the bit line pair is equalized. At this time, as shown in FIG. 4C, when the N-channel MOS transistor NT1 is turned on, the potential of the dummy bit line 22 is set to the ground level, and the low-level (L) signal is output from the inversion circuit 28 to the NAND. Since it is supplied to the circuit 30, the automatic precharge execution permission signal / PRE is set to a high level (H) as shown in FIG.
[0041]
Then, at time T1, the bit line enable signal BLE transitions to the low level, whereby the electrical connection between the bit line pair is disconnected. Thereafter, as shown in FIGS. 4A and 4B, when the word line WL0 is activated at time T2, the data held in the memory cell MC is read out to the bit line BL0, At T3, the sense amplifier enable signal / SAE is activated to a low level to amplify the potential difference between the pair of bit lines BL0 and / BL0.
[0042]
As shown in FIG. 4A, the bit line enable signal BLE is at a low level from time T1 to time T7, so that the N-channel MOS transistor NT1 is turned off and the inversion circuit 28 A high-level signal is supplied to the NAND circuit 30. However, since the sense amplifier enable signal / SAE is kept at the high level until time T3, a low-level signal is supplied from the inversion circuit 21 to the dummy bit line 22. Therefore, as shown in FIG. 4C, the potential of the dummy bit line 22 is kept at the ground level (GND) until time T3.
[0043]
Further, since a low-level signal is output from NOR circuit 27 until time T3, P-channel MOS transistor PT1 is turned on, so that the output node of current mirror circuit 25 is at a high level. Accordingly, the output signal of the NAND circuit 29 goes low, so that the automatic precharge execution permission signal / PRE is latched high as shown in FIG.
[0044]
Here, when the sense amplifier enable signal / SAE is activated to the low level at the time T3 as described above, the output signal of the inverting circuit 21 is set to the high level, so that the dummy signal is output as shown in FIG. The potential of the bit line 22 rises.
[0045]
When the sense amplifier enable signal / SAE is activated to a low level, the signal output from the NOR circuit 27 is set to a high level, so that the P-channel MOS transistor PT1 is turned off. Since the node is held at the high level, the automatic precharge execution permission signal / PRE is set to the high level as shown in FIG. When the signal output from the NOR circuit 27 goes high, the N-channel MOS transistor NT4 is turned on and the current mirror circuit 25 is activated.
[0046]
Here, as shown in FIG. 4C, when the potential of the dummy bit line 22 exceeds the reference voltage Vref at time T4, in the current mirror circuit 25, via the N-channel MOS transistor NT3 and the N-channel MOS transistor NT4. As a result, a current flows to the ground node, so that the output node of the current mirror circuit 25 goes low. At this time, since the output of the NAND circuit 29 is at the high level, the automatic precharge execution permission signal / PRE transitions to the low level and is activated as shown in FIG.
[0047]
Then, at time T5 after activation of the automatic precharge execution permission signal / PRE, the word line WL0 is inactivated as shown in FIG. 4 (a). ), The potential difference between the pair of bit lines BL0 and / BL0 has a full amplitude, so that the data of the power supply voltage VCC is rewritten in the memory cell MC.
[0048]
Thereafter, as shown in FIG. 4A, at time T6, the sense amplifier enable signal / SAE transitions to the high level, but the output of the NAND circuit 29 is at the high level. As shown, automatic precharge execution permission signal / PRE is latched at a low level.
[0049]
Then, as shown in FIG. 4A, when the bit line enable signal BLE is activated to a high level at time T7, as shown in FIG. 4B, the potential of the bit line pair BL0, / BL0 Is equalized and the N-channel MOS transistor NT1 is turned on, so that the potential of the dummy bit line 22 drops to the ground level as shown in FIG. At this time, since a low-level signal is supplied from the inversion circuit 28 to the NAND circuit 30, the automatic precharge execution permission signal / PRE transits to a high level as shown in FIG.
[0050]
As described above, in the timing adjustment circuit 20 shown in FIG. 3, the activation timing of the automatic precharge execution permission signal / PRE is the same as the time T4 which is a predetermined time after the time T3 when the sense amplifier enable signal / SAE is activated. Adjusted. Here, the automatic precharge execution permission signal / PRE is activated only when the potential of the dummy bit line 22 exceeds the reference voltage Vref, so that data is transferred to the memory cell MC between time T4 and time T5. At the time of rewriting, the bit line pair BL0, / BL0 also has a full amplitude, and as a result, data at the power supply voltage level (VCC) can be surely rewritten to the memory cell MC. This is effective for avoiding a retention failure in a memory such as a DRAM that causes the destruction of retained data when reading data. Then, after the rewriting is performed, the bit line pair is precharged for the operation in the next cycle.
[0051]
Further, in the timing adjustment circuit 20 shown in FIG. 3, the magnitude of the reference voltage Vref supplied to the gate of the N-channel MOS transistor NT2 constituting the current mirror circuit 25 is changed to change the potential of the dummy bit line 22. The activation timing of the automatic precharge execution permission signal / PRE can be adjusted by changing the time to reach the reference voltage Vref.
[0052]
In the timing adjustment circuit 20 shown in FIG. 3, once the automatic precharge execution permission signal / PRE is activated to a low level, the output of the NOR circuit 27 goes to a low level. It is turned off and the current mirror circuit 25 is inactivated. Thus, after the automatic precharge execution permission signal / PRE is activated, unnecessary current consumption in the current mirror circuit 25 is reduced.
[0053]
As described above, according to the semiconductor memory device of the embodiment of the present invention, the activation timing of automatic precharge execution permission signal / PRE is determined by comparing the potential of dummy bit line 22 with reference voltage Vref. It is possible to avoid the necessity of considering the margin required due to the process variation of the bit line pair BL, / BL and the like, and to prevent the retention failure, and to reliably speed up the activation timing of the automatic precharge execution permission signal / PRE.
[0054]
Therefore, from this, according to the semiconductor memory device according to the embodiment of the present invention, high-speed data reading and writing can be reliably realized with a simple configuration that does not require a dummy memory cell.
[0055]
【The invention's effect】
According to the semiconductor memory device of the present invention, the execution permission timing of the precharge operation for the bit line pair can be reliably maximized with a simple configuration, and high-speed reading and writing of data from and to the memory cell can be reliably realized. Can be.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a memory cell unit shown in FIG.
FIG. 3 is a circuit diagram showing a configuration of a timing adjustment circuit included in a control unit shown in FIG.
FIG. 4 is a timing chart showing an operation of the semiconductor memory device shown in FIG. 1;
FIG. 5 is a circuit diagram showing a configuration of a conventional semiconductor memory device.
FIG. 6 is a circuit diagram showing a configuration of a conventional timing adjustment circuit.
FIG. 7 is a timing chart showing an operation of the semiconductor memory device shown in FIG. 5;
[Explanation of symbols]
Reference Signs List 1 semiconductor memory device, 2 column section, 3 data bus, 4 sense amplifier section, 5 memory cell section, 6 control section, 7 row decoder, 10 external circuit, 20, 40 timing adjustment circuit, 21, 28, 31, 41, 41 42 inversion circuit, 22, DBL dummy bit line, 25 current mirror circuit, 27 NOR circuit, 29, 30 NAND circuit, 51, 52 latch circuit, 53 write driver, MC00, MC10, MCn0, MC0m, MC1m, MCnm, MC memory Cell, BL0, BLm bit line, / BL0, / BLm complementary bit line, WL0 to WLn word line, / DBL complementary dummy bit line, NT1 to NT4 N channel MOS transistor, PT1 to PT3 P channel MOS transistor, C1, C2 capacitance Device, DMC dummy memory cell, DSA dummy Nsuanpu, SA the sense amplifier, PRE precharge line, EQ equalizing line, WR column select lines, SE sense enable line.

Claims (4)

A semiconductor memory device comprising: a plurality of memory cells, a bit line pair connected to the memory cell, and amplification means for amplifying data read from the memory cell to the bit line pair,
A dummy bit line;
A dummy bit line driving unit that drives the dummy bit line according to an enable signal that activates the amplification unit;
Comparing means for comparing a preset reference potential with the potential of the dummy bit line;
Control means for permitting a precharge operation on the bit line pair after it is determined in the comparison by the comparing means that the potential of the dummy bit line has reached the reference potential. apparatus. 2. The semiconductor memory device according to claim 1, wherein said dummy bit line has the same wiring resistance and wiring capacitance as one of said bit line pairs. 2. The semiconductor memory device according to claim 1, wherein said dummy bit line driving means drives said dummy bit line with the same driving force as when said amplifying means drives said bit line pair. 2. The semiconductor memory device according to claim 1, wherein said comparing means is deactivated when said control means permits a precharge operation for said bit line pair.

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