KR100813524B1 - Bit-line Sense Amplifier Driver and Bit-line Sensing Method Using the Same - Google Patents

Abstract

A sense amplifier driver for overdriving a sense amplifier when performing a read (or write) operation after driving the sense amplifier and a sensing method using the same are provided.

The bit line sense amplifier driver according to the present invention is connected to the sense amplifier power line signal output terminal and includes a level compensator for supplying an external power voltage to the sense amplifier power line signal output terminal as a read or write command is enabled. The level compensator is driven by an output signal of a pulse width control means and a pulse width control means for outputting a first overdriving control signal as a read or write command is enabled, thereby providing an external power supply to the sense amplifier power line signal output terminal. And a switching element for supplying a voltage.

According to the present invention, by overdriving the sense amplifier when a read or write command is input, the reliability of the device can be improved by preventing the potential of the bit line from changing when performing a current-consuming read or write operation.

Bitline Sense Amplifiers, Overdriving

Description

Bit-line Sense Amplifier Driver and Bit-line Sensing Method Using the Same}

1 is a circuit diagram of a general bit line sense amplifier driver,

FIG. 2 is a view for explaining potential changes of bit lines and bit line bars after driving a sense amplifier using the bit line sense amplifier driver shown in FIG. 1;

3 is a circuit diagram of a bit line sense amplifier driver according to an embodiment of the present invention;

4A and 4B are circuit diagrams according to an embodiment of the level compensator shown in FIG. 3;

5 is a circuit diagram according to another embodiment of the level compensator shown in FIG. 3;

6 is a detailed circuit diagram of the pulse width control means shown in FIGS. 4 and 5;

7 is a view illustrating a potential change of a bit line and a bit line-bar after driving a sense amplifier using a bit line sense amplifier driver according to the present invention;

8 is a circuit diagram of a bit line sense amplifier driver according to another embodiment of the present invention;

9 is a flowchart illustrating a bit line sensing method according to the present invention.

<Description of the symbols for the main parts of the drawings>

200: level compensator 212, 222: pulse width control means

306: delay circuit

The present invention relates to a bit line sense amplifier driver and a sensing method using the same. More specifically, the sense amplifier driver for overdriving the sense amplifier when performing a read (or write) operation after driving the sense amplifier and a sensing method using the same It is about.

In general, in the sensing operation of the memory cell, overdriving for supplying a potential higher than an internal potential to the sense amplifier power line for a predetermined time in order to stably and quickly drive the sense amplifier.

A general bit line sensing process will be described with reference to FIG. 1.

1 is a circuit diagram of a general bit line sense amplifier driver, and serves to generate a control signal for driving a bit line sense amplifier.

When the bit line equalization signal BLEQ is high, the N-type transistors 102, 104, and 106 are turned on so that the voltages of the sense amplifier power line RTO and the sense amplifier ground line SB are first. It becomes the voltage VBLP.

Thereafter, when the active command is enabled and the BLEQ signal becomes low, and the word line selection signal is enabled, charge sharing is started on the bit line pairs BL and BLb.

Bit line sensing senses the amount of charge shared by the memory cell on the bit line pair. To this end, the bit line sensing amplifier driver enable signal SAP is required because the voltage applied to the bit line pair BL and BLb must be amplified. And SAN), wherein the first enable signal SAP is applied at a low level and the second enable signal SAN is applied at a high level.

Accordingly, the P-type transistor 108 and the N-type transistor 110 are each turned on so that the voltage level of the sense amplifier power line RTO transitions from the first voltage to the second voltage by the internal power supply voltage VCORE. do. In addition, the voltage applied to the sense amplifier ground line SB transitions from the first voltage to the ground voltage VSS.

The potential applied to the sense amplifier power line RTO and the sense amplifier ground line SB is a power source of the sense amplifier, so that the sensing is performed by amplifying the voltage level of the pair of bit lines BL and BLb which started charge sharing. do. At this time, since the accurate sensing is performed when the difference between the voltage levels applied to the bit line pairs BL and BLb is equal to or greater than a predetermined value, the overdriving control signal OVD is enabled to sense the amplifier through the P-type transistor 112. By applying the external power supply voltage VDD to the power line RTO, the time for charge to be charged in the bit line can be shortened, and as a result, the sensing time can be shortened.

However, after the bit line sensing is started in this manner, when a read or write operation is performed in the actual sense amplifier, a large amount of current is consumed, thereby changing the potential of the bit line.

FIG. 2 is a diagram illustrating a potential change of a bit line and a bit line-bar when driving a sense amplifier using the bit line sense amplifier driver shown in FIG. 1.

As shown, after a read command READ is enabled, for example, at time t1, a read operation is performed to transfer data to the local input / output line LIO, thereby causing the bit line BL to be time t2 to t3. And the voltage applied to the bit line-bar BLb gradually decreases, and as the read command is disabled, the potentials of the bit line BL and the bit line-bar BLb rise again until time t4. .

If this process is repeated, the potentials of the bit lines and the bit line bars continue to be lowered, and thus, the reliability of data transmitted to the local input / output lines cannot be guaranteed and the operation speed is delayed. . This problem is further exacerbated in memory devices using low power supply voltage.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. After driving the sense amplifier by the bit line sense amplifier driver, if an operation command (read or write) is enabled, the data is sensed by overdriving the sense amplifier. There is a technical problem to improve the reliability of the.

According to an aspect of the present invention, a bit line sense amplifier driver is connected to a sense amplifier power line signal output terminal and responds to a time point at which a read or write command is enabled. And a level compensator for supplying an external power supply voltage to the signal output terminal.

The level compensator may include pulse width control means for outputting a first over driving control signal as a read or write command is enabled; And a switching element driven by an output signal of the pulse width control means to supply an external power supply voltage to the sense amplifier power line signal output terminal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a bit line sense amplifier driver according to an embodiment of the present invention.

As shown, the sense amplifier driver of the present invention is connected to the sense amplifier power line signal RTO output terminal N, and is driven by an operation command (READ or WRITE) to drive the sense amplifier power line. The apparatus may further include a level compensator 200 for supplying the external power voltage VDD to the signal output terminal N.

More specifically, the sense amplifier driver of the present invention may be connected between the internal power supply voltage terminal VCORE and the sense amplifier power line signal output terminal N to be driven by the first enable signal SAP. 208, a first N-type transistor 202 connected between the sense amplifier power line signal output terminal N and the bit line precharge voltage supply terminal VBLP and driven by the bit line equalization signal BLEQ, a sense amplifier A second N-type transistor 204 and a sense amplifier power line signal output terminal connected between the ground line signal SB output terminal and the bit line precharge voltage supply terminal VBLP and driven by the bit line equalization signal BLEQ. A third N-type transistor 206 and a sense amplifier ground line signal output terminal connected between the (N) and sense amplifier ground line signal output terminals and driven by the bit line equalization signal BLEQ; A fourth N-type transistor 210 connected between the ground terminals VSS and driven by the second enable signal SAN, and further connected to the sense amplifier power line signal RTO output terminal N; Enable the first overdriving control signal by means of a READ or WRITE command and apply an external power supply voltage (VDD) to the sense amplifier power line signal output terminal as the read (or write) command is enabled. It further comprises a level compensator 200 for supplying.

That is, the sense amplifier driver according to the present invention drives the level compensator 200 by a read or write command as the read or write command is enabled after the sense amplifier is driven. The potential of the amplifier power line signal is raised to prevent the potential of the bit line from dropping during current consuming read or write operations.

Meanwhile, in another embodiment of the present invention, not only after the read or write command is enabled, but also when the first and second enable signals (SAP and SAN) for driving the sense amplifier are enabled, the driver may overdrive the sense amplifier. Can be. When the first and second enable signals SAP and SAN are enabled, the level compensator 200 is driven by the second overdriving control signal so that an external power supply voltage may be applied to the sense amplifier power line signal RTO. VDD) to be applied so that the operation of the sense amplifier is started at a high speed. Then, as the read or write command is enabled, the level compensator (BDD) is generated by the first overdriving control signal generated by the read or write command. In operation 200, the potential of the sense amplifier power line signal is increased when the sensing operation is performed, so that the potential of the bit line does not drop during a read or write operation in which current consumption is high.

The configuration of the sense amplifier driver described with reference to FIG. 3 is not limited thereto, and may be configured in any possible form capable of driving the sense amplifier, and the level compensator 200 of the present invention may be connected and used.

4A and 4B are circuit diagrams of an embodiment of the level compensator shown in FIG. 3.

As shown in FIG. 4A, the level compensator 200 outputs a pulse width control means for outputting a first overdriving control signal OVD1 that is enabled as a read or write command signal is enabled. 212, a switching element 214 connected to the external power supply voltage terminal VDD and the sense amplifier power line signal output terminal N and driven by an output signal of the pulse width control means 212.

If overdriving is to be performed even while driving the sense amplifier, the level compensator 200 may apply the first overdriving control signal OVD1 and the second overdriving control signal OVD2 as illustrated in FIG. 4B. As an input, it may further include a logic element 216 for outputting an enabled state of the two input signals as a drive signal of the switching element 214.

Here, the second overdriving control signal OVD2 is a signal enabled when the first and second enable signals SAP and SAN are enabled, and the switching element 214 may be implemented as a MOS transistor. In particular, when the switching element 214 is implemented as an N-type transistor, an inverting means 218 can be further implemented between the output terminal of the logic element 216 and the switching element 214. In addition, the logic device 216 may be implemented with a NOR gate.

The second overdriving control signal OVD2 is enabled together with the first and second enable signals SAP and SAN, and since the read or write command is not yet input, the logic element 216 and the inverting means. 218 outputs the overdriving control signal as it is to turn on the switching element 214, thereby supplying an external power supply voltage VDD to the sense amplifier power line signal output terminal N, whereby the sense amplifier has a primary over. Driving.

Thereafter, when the second overdriving control signal OVD2 is disabled and the read or write command is enabled, the pulse width control means 212 receives the first overdriving control signal OVD1 synchronized with the read or write command. This signal is output as a pulse having a predetermined width that is driven when a read or write command is enabled. In a preferred embodiment of the present invention, the first overdriving control signal OVD1 is enabled at the time when the read or write command is enabled and can be controlled to have a narrower pulse than the read or write command.

The output signal OVD1 of the pulse width control means 212 drives the switching element 214 through the logic element 216 and the inverting means 218, and thus, after the read or write operation is started, the sense amplifier power The external power supply voltage VDD is supplied to the line output terminal N so that the sense amplifier is secondly overdried.

FIG. 5 is a circuit diagram according to another embodiment of the level compensator shown in FIG. 3 and illustrates a level compensator for overdriving the sense amplifier when the sense amplifier is driven and when an operation command is input to the sense amplifier.

In this case, the level compensator 200 may output pulse width control means 224 and pulse width control means 224 to output a first overdriving control signal OVD1 that is enabled as a read or write command signal is enabled. Is driven by the first switching element 226 and the second overdriving control signal OVD2 for supplying the external power supply voltage VDD to the sense amplifier power line signal output terminal N. And a second switching element 222 for supplying an external power supply voltage VDD to the sense amplifier power line signal output terminal N.

The first and second switching elements 226 and 222 may be implemented with MOS transistors such as N type transistors.

As in FIG. 4B, the second switching element 222 is driven by the second overdriving control signal OVD2 to apply an external power supply voltage VDD to the sense amplifier power line signal output terminal N, thereby starting sensing. The first switching element 226 is driven by the first overdriving control signal OVD1 output from the pulse width control means 224 at a time when a read or write command is enabled. The external power supply voltage VDD is applied to the sense amplifier power line signal output terminal N to compensate for a potential drop during a read or write operation.

FIG. 6 is a detailed circuit diagram of the pulse width control means shown in FIGS. 4 and 5.

The pulse width control means 212, 222 has a read or write command as the first input signal and the inversion delay signal of the read or write command as the second input, and has a predetermined width when the read or write command is enabled. The logic element 302 outputs a pulse signal.

Here, the inversion delay signal of the read or write command can be implemented by connecting the first inverting means 304 and the delay circuit 306 in series, and although not shown, the delay circuit 306 can be connected by connecting an even number of inverting means in series. Can be implemented. In addition, the logic element 302 may be implemented as a NAND gate, and in this case, it is preferable to connect the second inverting means 308 to the output terminal of the NAND gate.

FIG. 7 is a view illustrating a potential change of a bit line and a bit line-bar when driving a sense amplifier using a bit line sense amplifier driver according to the present invention.

As illustrated, the level compensation unit may be driven at time t11 to first overdrive the sense amplifier to accelerate the start of sensing. Subsequently, when a read command is input and a read or write operation is performed at time t12, the potential applied to the bit line does not drop by driving the level compensator 200 to second overdrive the sense amplifier. You will be able to maintain your initial level.

In the above description, the sense amplifier driver having one level compensator has been described. However, by connecting the plurality of level compensators in series, a higher voltage may be applied to the sense amplifier power line signal output terminal.

8 is a circuit diagram of a bit line sense amplifier driver according to another embodiment of the present invention.

The bit line sense amplifier driver according to the present embodiment provides a level compensator 200 and a sense amplifier driver for supplying an external power voltage VDD to the sense amplifier power line signal output terminal RTO when a read or write command is input. And an over-driving unit 400 for supplying an external power supply voltage VDD to the sense amplifier power line signal output terminal RTO when the first and second enable signals SAP and SAN are enabled. do.

When the bit line sense amplifier is configured as shown in FIG. 8, an external power supply voltage is applied to the sense amplifier power line signal output terminal RTO by the over-driving unit 400 when driving the sense amplifier for sensing operation. The voltage on the bitline-bar can be changed quickly. After shortening the sensing start time in this manner, when a read or write command is input, the level compensator 200 applies an external power supply voltage to the sense amplifier power line signal output terminal RTO again, thereby reading. It is possible to compensate for the potential drop due to the large current consumption during the write / write operation.

Here, the level compensator 200 may be configured as shown in FIG. 4A, and the overdriving unit may be configured using the second switching element 222 illustrated in FIG. 5, and the detailed description thereof has been described above. It will be omitted.

The configuration of the sense amplifier driver described with reference to FIG. 3 is not limited thereto, and may be configured in any possible form capable of driving the sense amplifier, thereby connecting the level compensator 200 and the overdriving unit 400 of the present invention. Can be used.

9 is a flowchart illustrating a bit line sensing method according to the present invention.

After the bit line equalization signal is disabled, the word line selection signal is enabled to start charge sharing on the bit line pair (S101).

Thereafter, the first and second enable signals SAP and SAN for driving the bit line sense amplifier driver are enabled (S103) to drive the sense amplifier.

Next, the second overdriving control signal OVD2 is enabled (S105), and an external power supply voltage VDD is applied to the sense amplifier power line signal output terminal RTO to first overdrive the sense amplifier.

In this manner, the difference between the voltage applied to the sense amplifier ground line SB and the voltage applied to the sense amplifier power line RTO is rapidly increased to a predetermined value or more. This in turn causes the voltage difference between the bit line and the bit line-bar to rapidly increase above a certain value, so that the sensing operation can be started quickly.

Thereafter, when the read or write command is enabled, the first overdriving control signal is enabled to apply an external power supply voltage to the sense amplifier power line signal output terminal to perform second overdriving (S107), and By sensing together (S109), it is possible to prevent the potential of the bit line and the bit line-bar from being changed in the sensing process.

In FIG. 9, an example in which the primary overdriving is performed when the sense amplifier is driven and the second overdriving is performed when a read or write command is input, the first overdriving process is omitted and the second overdriving process is omitted. Of course it is also possible to perform only.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

According to the present invention, when a read or write command is input after driving the sense amplifier, the driving of the sense amplifier is overdried so that the potential of the bit line does not change during a current consuming read or write operation, thereby improving reliability of the device. Can be improved.

This advantage is more effective in the memory device using a low power supply voltage can ensure a stable operation of the memory device.

Claims (19)

A bit line connected to a sense amplifier power line signal output terminal and including a level compensator for supplying an external power voltage to the sense amplifier power line signal output terminal in response to a read or write command being enabled; Sense Amplifier Driver. The method of claim 1, The level compensator may include pulse width control means for outputting a first overdriving control signal as the read or write command is enabled; And A switching element driven by an output signal of the pulse width control means to supply an external power supply voltage to the sense amplifier power line signal output terminal; Bit line sense amplifier driver comprising a. The method of claim 2, And the switching device is connected between an external power supply voltage terminal and the sense amplifier power line signal output terminal. The method of claim 1, The level compensator may include pulse width control means for outputting a first overdriving control signal as a read or write command signal is enabled; The second overdriving control signal and the first overdriving control signal, which are activated when the first and second enable signals SAP and SAN are enabled, are input, so that a signal in an enabled state of the two input signals is input. Output logic elements; And A switching element driven by an output signal of the logic element to supply an external power supply voltage to the sense amplifier power line signal output terminal; Bit line sense amplifier driver comprising a. The method of claim 4, wherein And the logic element is a NOR gate. The method of claim 4, wherein And the switching device is connected between an external power supply voltage terminal and the sense amplifier power line signal output terminal. The method of claim 6, And said switching element is an N-type transistor, and further comprising inverting means between an output terminal of said logic element and a switching element. The method of claim 1, The level compensator may include pulse width control means for outputting a first overdriving control signal as the read or write command is enabled; A first switching element driven by an output signal of the pulse width control means to supply an external power supply voltage to the sense amplifier power line signal output terminal; And A second switching driven by a second overdriving control signal activated when the first and second enable signals SAP and SAN are enabled to supply an external power voltage to the sense amplifier power line signal output terminal; device; Bit line sense amplifier driver comprising a. The method of claim 8, And the first and second switching elements are MOS transistors. The method according to any one of claims 2, 4 or 8, The pulse width control means uses the read or write command as a first input signal and the inverted delay signal of the read or write command as a second input so that the pulse having a predetermined width when the read or write command is enabled. And a logic element for outputting a signal. The method of claim 10, And the logic element is a NAND gate, and further includes second inverting means connected to an output terminal of the NAND gate. The semiconductor device is driven by a bit line sense amplifier by a bit line sense amplifier driver controlled by the first and second enable signals to generate a sense amplifier power line signal and a sense amplifier ground line signal for driving the bit line sense amplifier. A method for sensing a bit line of a memory device, Selecting a word line according to an active command to activate the first and second enable signals after charge sharing is started on a pair of bit lines; And Enabling the first overdriving control signal when a read or write command is enabled to apply an external power supply voltage to the sense amplifier power line signal output terminal to overdrive the sense amplifier; Bit line sensing method comprising a. The method of claim 12, And the first overdriving control signal is a pulse signal of a predetermined width generated by a combination of the read or write command and an inversion delay signal of the read or write command. The method of claim 12, The enabling of the first and second enable signals may include enabling a second overdriving control signal and applying an external power supply voltage to the sense amplifier power line signal output terminal to overdrive the sense amplifier. Bit line sensing method comprising the. A level compensator for supplying an external power supply voltage to a sense amplifier power line signal output terminal in response to a time point at which a read or write command is enabled; And An over-driving unit for supplying an external power voltage to the sense amplifier power line signal output terminal as the first and second enable signals SAP and SAN are enabled; Bit line sense amplifier driver comprising a. The method of claim 15, The level compensator may include pulse width control means for outputting a control signal as a read or write command is enabled; And A switching element driven by an output signal of the pulse width control means to supply an external power supply voltage to the sense amplifier power line signal output terminal; Bit line sense amplifier driver comprising a. The method of claim 16, And the switching device is connected between an external power supply voltage terminal and the sense amplifier power line signal output terminal. The method of claim 15, And the overdriving portion is a switching element connected between an external power supply voltage terminal and the sense amplifier power line signal output terminal and driven by an overdriving control signal. The method of claim 18, And said switching element is a MOS transistor.

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